KR100211754B1 - Asynchronous memory control circuit - Google Patents

Abstract

end. FIELD OF THE INVENTION The invention described in the claims relates to an asynchronous memory control circuit having different read / write clock timings.

I. SUMMARY OF THE INVENTION An object of the present invention is to provide an asynchronous memory control circuit that can reduce access time of an asynchronous memory by eliminating the glitch clock caused by the asynchronous of the light clock and the read clock.

All. SUMMARY OF THE INVENTION A synchronous memory control circuit comprising: a first multiplexer for selectively outputting one of read / write addresses input according to a logic level of a write enable signal to the asynchronous memory, a write enable signal, The read / write operation is controlled by selectively outputting one of the read clock and the write clock input to the asynchronous memory according to the logical combination of the read enable signal, and a constant level when both the write enable signal and the read enable signal are inactive. And a second multiplexer having a third signal input terminal having a predetermined level so as to output the clock to the asynchronous memory.

la. Important use of the invention: It can be used for XGA converter for LCD monitor.

Description

Asynchronous Memory Control Circuit

The present invention relates to an XGA converter for an LCD monitor, and more particularly to a circuit for controlling read / write asynchronous memory inside the XGA converter.

In order to use LCD panels, which are commonly used in notebook PCs, as monitors for desktop personal computers, the resolution needs to be improved. That is, it is necessary to convert a VGA (resolution; 640 x 1.6 = 1024) signal or an SVGA (resolution; 800 x 1.25 = 1000) signal into an XGA (resolution; 1024 x 768) signal. Horizontal component conversion in the video signal is possible by increasing the number of sampling data (VGA; 640 × 1.6 = 1024, SVGA; 800 × 1.25 = 1000), and vertical component conversion is possible by using a line extension algorithm. In other words, in order to increase the number of vertical lines (480 lines) of VGA to the number of vertical lines (768 lines) of XGA, an algorithm for converting 5 lines to 8 lines is used, and the number of vertical lines of SVGA (600 lines) is vertical to XGA. To increase the number of lines (768 lines), an algorithm is needed to increase 4 lines to 5 lines. Memory is required in the XGA converter to implement this algorithm.

In order to convert the vertical line of the VGA into the vertical line of the XGA, 5 lines must be written to the memory and 8 lines are read at the same time, so that the read clock RCK becomes 1.6 times that of the write clock WCK. On the other hand, in order to convert the vertical line of the SVGA into the vertical line of the XGA, it is necessary to write four lines to the memory and read five lines at the same time, so that the read clock (RCK) becomes 1.25 times faster than the write clock (WCK). That is, since the memory used in the XGA converter has one clock port as a line memory (SRAM), a glitch clock occurs because of the light clock WCK and the read clock RCK of different speeds.

Hereinafter, a process of generating the glitch clock and an error generating process of the line memory control operation will be described with reference to FIGS. 1 and 2 as follows.

(Read Enable Bar)신호에 따라 입력클럭중 하나를 라인메모리로 출력한다. 예를들어 도 2에 도시된 바와 같은 타이밍주기를 갖는 클럭(WCK, RCK)과 WE/

신호가 도 1에 도시된 MUX(10A)에 입력되면 상기 MUX(10A)의 출력단 Y로부터는 도 2에 도시된 클럭(CK)이 발생되어 라인메모리(20A)의 클럭단으로 입력되게 된다. 이러한 경우 상기 클럭(CK)에는 라이트동작에서 리드동작(혹은 리드동작에서 라이트동작)으로 전환되는 시점에서 양 클럭(WCK,RCK)의 비동기에 기인된 글리치클럭(D)이 발생되게 된다. 따라서 종래 XGA 컨버터에서는 라인메모리 액세스시 양 클럭(WCK,RCK)의 비동기에 기인하여 발생된 글리치클럭(D)에 의해 라인메모리(20A)를 액세스하기 위한 시간이 지연되는 문제점이 있었다.FIG. 1 is a block diagram illustrating an asynchronous timing of a read clock RCK and a write clock WCK for accessing a line memory provided in a conventional XGA converter, and FIG. 2 is a diagram illustrating the configuration of FIG. A timing diagram of each clock is shown. In general, three line memories exist in the XGA converter for an LCD monitor as shown in FIG. The reason is that the video signal is processed into R, G, and B in the video signal processing system, and a separate line memory is required for vertical line expansion of each R, G, and B signal to prevent duplication of read and write operations. Because. Referring to FIG. 1, the clock terminal CK of each of the line memories 20A, 20B, and 20C has an output terminal Y of the MUXs 10A, 10B, and 10C having two inputs of the light clock WCK and the read clock RCK. ), And the MUXs 10A, 10B, and 10C are each WE (Write Enable) /

Outputs one of the input clocks to the line memory according to the (Read Enable Bar) signal. For example, the clocks WCK and RCK and WE / having a timing period as shown in FIG.

When the signal is input to the MUX 10A shown in FIG. 1, the clock CK shown in FIG. 2 is generated from the output terminal Y of the MUX 10A and input to the clock terminal of the line memory 20A. In this case, the clock CK generates a glitch clock D due to the asynchronous of both clocks WCK and RCK at the time of switching from the write operation to the read operation (or the write operation from the read operation). Therefore, in the conventional XGA converter, there is a problem in that the time for accessing the line memory 20A is delayed by the glitch clock D generated due to the asynchronous of both clocks WCK and RCK when the line memory is accessed.

Accordingly, an object of the present invention is to provide an asynchronous memory control circuit capable of shortening the access time of an asynchronous memory by removing the glitch clock caused by the asynchronous of the light clock and the read clock.

The present invention for achieving the above object in the LCD monitor XGA converter having a plurality of line memories,

First multiplexers for selectively outputting one of the read / write addresses input according to the logic level of the write enable signal to the respective line memories;

According to the logical combination of the write enable signal and the read enable signal, one of the input read clock and the write clock is output to the respective line memories to control read / write operations, and the write enable signal and the read enable signal are controlled. Is composed of second multiplexers having a third signal input terminal of a predetermined level to output a predetermined level of clock to each of the line memories when all of them are inactive.

1 is a block diagram illustrating asynchronous timing of a read clock RCK and a write clock WCK for accessing a line memory provided in a conventional XGA converter.

2 is a timing diagram of each clock according to the configuration of FIG. 1;

3 is an asynchronous memory control circuit diagram according to an embodiment of the present invention.

4 is a timing diagram of each clock CK and address AD according to the configuration of FIG.

Hereinafter, an operation according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 illustrates an asynchronous memory control circuit diagram according to an embodiment of the present invention, and FIG. 4 illustrates timing diagrams of respective clocks CK and AD according to the configuration of FIG. 3. First, referring to FIG. 3, each of the address input terminals AD of the line memories 50A, 50B, and 50C present in the XGA converter for LCD monitors for vertical line expansion of the R, G, and B signals has a 9-bit write address ( It is connected to the output terminal Y of the MUXs 30A, 30B, and 30C having two inputs of RAD) and the lead address RAD, and the MUXs 30A, 30B, and 30C are respectively inverters INV2, INV4, and INV6. One of the input addresses is output to the line memories 50A, 50B, and 50C according to the WEB (Write Enable Bar) signal input to the selection terminal S through. That is, as shown in FIG. 3, the MUXs 30A, 30B, and 30C that input the read address RAD and the write address WAD output the write address WAD only when WE is activated, and otherwise, the read address WAD. Outputs (RAD). On the other hand, the clock stages CK of the line memories 50A, 50B, and 50C each have an output terminal of the MUX 40A, 40B, 40C having three inputs of a read clock RCK, a light clock WCK, and a high level. Y), and the MUXs 40A, 40B, and 40C are logic of REB (Read Enable Bar) and WEB (Write Enable Bar) signals input to the selection terminals S0 and S1 through the inverters INV1 to INV6, respectively. Depending on the combination, one of the input clocks RCK, WCK is output to the line memories 50A, 50B, 50C. That is, the MUXs 40A, 40B, and 40C output the light clock WCK when WE is activated and the read clock RCK when RE is activated. Otherwise, the MUX 40A, 40B, 40C outputs a high level line memory 50A. , 50B, 50C) Output as a clock.

Hereinafter, referring to FIG. 4, the operation of the asynchronous memory control circuit having the configuration of FIG. 3 will be described. First, in FIG. 4, the WCK and the RCK represent light clocks and lead clocks input to the MUXs 30A, 30B, and 30C, respectively. MUX 30A, 30B, 30C if the WEB is active with a timing cycle as shown in 4 to sequentially write data to line memory 0 (50A), line memory 1 (50B), and line memory 2 (50C). Each outputs a write address WAD only when WEB is active, and outputs a read address RAD otherwise. MUX 40A, 40B, 40C if the REB is active at a timing cycle as shown in FIG. 4 to sequentially read data from line memory 1 50B, line memory 2 50c, and line memory 0 50a. Each of them outputs a light clock (WCK) when WEB is active and a read clock (RCK) when REB is active. Otherwise, it outputs a high level to the line memory (50A, 50B, 50C) clock. do. Therefore, it can be seen that the input clocks CK0, CK1, and CK2 are maintained at the high level in the line memories 50A, 50B, and 50C where the write / read operation is not performed. Glitch clocks are not generated when the write / read operation is switched. Therefore, the delay of the line memory access time can be prevented.

As described above, the present invention eliminates the glitch clock caused by the timing difference between the light clock and the read clock in controlling the asynchronous memory of the LCD monitor XGA converter, thereby reducing the access time of the asynchronous memory and at the same time correcting read / write operations. There is an advantage to doing this.

Claims (3)

In the asynchronous memory control circuit, A first multiplexer for selectively outputting one of the read / write addresses input according to the logic level of the write enable signal to the asynchronous memory; According to the logical combination of the write enable signal and the read enable signal, one of the input read clock and the write clock is output to the asynchronous memory to control read / write operations, and both the write enable signal and the read enable signal are both And a second multiplexer having a third signal input terminal of a predetermined level to output a predetermined level of clock to the asynchronous memory when inactive. The asynchronous memory control circuit of claim 1, wherein the asynchronous memory is a line memory. In the XGA converter for LCD monitor having a plurality of line memory, First multiplexers for selectively outputting one of the read / write addresses input according to the logic level of the write enable signal to the respective line memories; According to the logical combination of the write enable signal and the read enable signal, one of the input read clock and the write clock is output to the respective line memories to control read / write operations, and the write enable signal and the read enable signal are controlled. And a plurality of second multiplexers having a third signal input terminal of a predetermined level to output a predetermined level of clock to each of the line memories when all are inactive.

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