KR0165518B1 - Fifo of graphic control - Google Patents

Abstract

The present invention relates to a FIFO of a graphics controller, and more particularly, to a data packing FIFO of a graphics controller that packs data coming from a system bus of a personal computer and outputs it to a frame buffer.

According to the present invention, when n-bit address, m-byte data, and m-bit byte enable data are continuously input from the system bus, the continuously input m-byte data is packed into 2m bytes and output to the frame buffer. As a result, there is no data delay and an advantage of preventing the overall system slowdown.

Description

Data Packing FIFO of the Graphics Controller

1 is a block diagram showing an example of data packing FIFO use according to the present invention;

2 is a block diagram of a data packing FIFO of a graphics controller according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to FIFO (First In First Out) of a Graphic Controller, and in particular, a graphic controller that packs data coming from a system bus of a personal computer and outputs it to a frame buffer. Data packing FIFO.

In general, the FIFO is used when the data processing speed between the front and rear of the FIFO is different, that is, when the speed of reading data from the FIFO at the rear is slower than the speed of writing data to the FIFO at the rear. Will act as the buffering.

Therefore, the need for the FIFO is indispensable when receiving continuous data as input.

Peripheral Component Interconnect (PCI), the system bus of personal computers (PCs), has a command to continuously write data.

Therefore, when the command is executed, a case of writing continuous data at a high speed to a graphic controller in a personal computer occurs, and the graphic controller must write data input through the system bus to a frame buffer which is its own memory. do.

Accordingly, if the graphic controller does not continuously output the data continuously input to the plane buffer, a delay is generated and the overall system speed is reduced.

In addition, there is a problem in that the number of bits of the input data coming from the system bus is different from the number of bits written to the frame buffer.

Accordingly, an object of the present invention is to provide a data packing FIFO of a graphics controller that packs data coming from a system bus and outputs it to a frame buffer in order to solve the above problem.

The data packing FIFO of the graphic controller according to the present invention for achieving the above object, n-bit (Address), m-byte (Byte) data, m-bit Byte Enable Data (Byte Enable Data) A FIFO of a continuously input graphic controller, comprising: first address storage means for receiving the n-bit address and storing only n-1 bit addresses, and m-byte data corresponding to odd and even addresses of the addresses; First and second data storage means for storing, and first and second byte enable for storing byte enable data logic 0 values at valid byte positions among m-byte data corresponding to the odd and even addresses, respectively. The logic 1 value is set where data is written and where data is written among the first and second data storage means, and data is not written. An input unit including first and second flags in which logic 0 values are set;

When the address does not come in continuously, the logic having a logic 0 value among the first and second flags is checked to make the logic 1 invalid for the corresponding position of the first and second byte enable data storage means. Write and output the m-byte data of each of the first and second data storage means into 2 m-bytes, and output each of the m and m data of the first and second byte-enabled data storage means. A control circuit unit for packing the enable data of bits into 2m bits and outputting them;

Second address storage means for receiving and storing an address of n-1 bits of the first address storage means of the input unit, and data packed with 2 m bytes of data of each m byte of the first and second data storage means. A third data storage means for receiving and storing the first and second byte enable data storage means for receiving and storing the byte enable data packed with 2 m bits of byte enable data of each m-bit; An output unit configured of byte enable data storage means;

Mxing an address of n-1 bits, 2m bytes of data, and 2m bits of byte enable data, respectively, from the second address storage means, the third data storage means, and the third byte enable data storage means. It characterized in that it comprises a multiplexer to selectively output.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram illustrating an example of using a data packing FIFO according to the present invention, and illustrates the concept of the present invention.

Referring to FIG. 1, the FIFO 3 inside the graphics controller 3 receives m bytes of data from the system bus 1 and packs them in 2 m bytes to output to the frame buffer 7. do.

Accordingly, data continuously input at high speed from the system bus can be output to the frame buffer without delay.

FIG. 2 is a block diagram of a data packing FIFO of the graphic controller according to the present invention. Referring to FIG.

n-bit addresses (iaddr [n: 0]) are successively input so that only n-1 bits of addresses (iaddr [n-1: 0]) are stored in the first address storage means 1, and m-byte data When (idata [8m-1: 0]) is input, data corresponding to the odd-numbered address (the least significant bit is 0) and the even-numbered address (the least significant bit is 1) are separated and respectively the first and It is stored in the second data storage means (3, 5).

At the same time, byte enable data (ibe [m-1: 0]) is input, and a logic 0 value of byte enable data is first only at a valid byte position among m-byte data corresponding to the odd and even addresses. And second byte enable data storage means (7, 9).

At this time, the logic 1 value is set in the first and second flags 11 and 13 where data is written among the first and second data storage means 3 and 5, and the logic where the data is not written. 0 is set.

Although not shown, when the control circuit unit of the data packing FIFO does not continuously enter the address iaddr [n: 0], the logic 0 value of the first and second flags 11 and 13 is changed. The position of the first and second byte enable data storage means 7 and 9 is written, and logic 1 having an invalid meaning is written to the corresponding position of the first and second byte enable data storage means 7 and 9, and the first and second data storage means 3 and 5 Each m-byte of the data) is packed into 2 mbytes and output, and the m-bit enable data of the first and second byte enable data storage means 7 and 9 is packed into 2 mbits. To output

Next, an n-1 bit address (iaddr [n-1: 0]) output from the first address storage means 1 is stored in the second address storage means 15, and the first and second data are stored. Data packed with 2 m bytes of data of each m byte of the storage means 3 and 5 is stored in the third data storage means 17, and the first and second byte enable data storage means 7 and 9 are stored. The byte enable data packed with 2 m bits of byte enable data of each m-bit) is stored in the third byte enable data storage means 19.

Finally, the multiplexer 21 receives n-1 bits of address and packed 2m bytes from the second address storage means 15, the third data storage means 17, and the third byte enable data storage means 19, respectively. And muxing the packed 2m-bit byte enable data and selectively outputting the data.

Therefore, since the data packing FIFO of the graphic controller according to the present invention packs data continuously input from the system bus and outputs the data to the frame buffer, there is no data delay and the overall system speed can be prevented.

In addition, the present invention is not limited to the above embodiments, and it is apparent that various modifications are possible by those skilled in the art within the technical idea of the present invention.

Claims (1)

A first address storage for receiving the n-bit address and storing only n-1 bits of addresses in the FIFO of the graphic controller in which n-bit address, m-byte data, and m-bit byte enable data are continuously input. Means, first and second data storage means for storing m-byte data corresponding to the odd-numbered and even-numbered addresses, and at valid byte positions of the m-byte data corresponding to the odd- and even-numbered addresses, respectively. First and second byte enable data storage means for storing the byte enable data logic 0 value respectively, and a logic 1 value is set where data is written out of the first and second data storage means, and data is not written. An input part including first and second flags in which a logic zero value is set; When the address does not come in continuously, the logic having a logic 0 value among the first and second flags is checked to make the logic 1 invalid for the corresponding position of the first and second byte enable data storage means. And output each of the m-byte data of the first and second data storage means by packing 2 m-bytes, and printing each of the m-bits of the first and second byte-enabled data storage means. A control circuit unit for packing and outputting the enable data into 2 m bits; Second address storage means for receiving and storing an n-1 bit address of the first address storage means of the input unit, and data packed with 2 m bytes of data of each m byte of the first and second data storage means. Third data storage means for receiving and storing, and a third data receiving and storing byte enable data packed with 2 m bits of byte enable data of each of the first and second byte enable data storage means of the input unit. An output unit configured of byte enable data storage means; Mxing an address of n-1 bits, 2m bytes of data, and 2m bits of byte enable data, respectively, from the second address storage means, the third data storage means, and the third byte enable data storage means. And a multiplexer for selectively outputting the data packing FIFO.