JP2002050172A - Fifo control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an FIFO control circuit capable of performing the writing and reading of input data to/from an FIFO with plural byte widths without imposing any load on a CPU. SOLUTION: Input data are inputted through an input bus switch 13 to the input side of an FIFO 14 with plural byte widths, and data read from the FIFO 14 are outputted through an output bus switch 15. At the time of writing, the data are written through an input control part 203 having a byte enable terminal 11 and an address counter 204, and at the time of reading, the data are read through an output control part 210 having an address counter 211.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a memory FIFO.
The present invention relates to a (first-in, first-out) control circuit, particularly to a FIFO control circuit capable of byte access.

[0002]

2. Description of the Related Art The prior art of such a FIFO control circuit is as follows.
For example, "Data transfer circuit of magnetic disk" in JP-A-10-260786, "Data transfer control device and method" in JP-A-7-84932, and
183440, "Encoding device and decoding device"
Etc.

[0003]

Conventionally, when data is exchanged between a magnetic disk or the like and an external interface, the magnetic disk inputs and outputs data in units of 512 bytes, whereas the external interface has an odd data amount. In some cases. First data is F
If the data is stored in the IFO format, the remaining data
U (Central Processing Unit) had to pick up the data, store the bytes together in a FIFO, and combine the data. That is, the above-described conventional FIFO control circuit or method has a problem that the load on the CPU increases because the CPU must be involved in data transfer.

Accordingly, it is an object of the present invention to provide a FIFO control circuit which enables data transfer without imposing a load on a CPU.

[0005]

A FIFO control circuit according to the present invention is a circuit for writing and reading input data to and from a FIFO having a plurality of byte widths. The FIFO control circuit is arranged on the input side of the FIFO and receives input data in byte units. An input bus switch for outputting, and a FIFO arranged on the output side of the FIFO.
An output bus switch for inputting / outputting an output from O in units of bytes, and an input / output control unit which has a byte enable terminal and an address counter and controls writing and reading of the FIFO, respectively.

According to a preferred embodiment of the FIFO control circuit of the present invention, the FIFO comprises a plurality of FIFOs each having a 1-byte width. Each of the input bus switch and the output bus switch includes a plurality of multiplexers. The output side of the output bus switch includes a buffer for outputting output data or setting a high impedance according to a read signal.

There is an address comparator for comparing the input address from the input control unit and the output address from the output control unit to generate a full or empty output, and performs writing and reading in units of a plurality of bytes or in units of one byte.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure and operation of a preferred embodiment of a FIFO control circuit according to the present invention will be described below in detail with reference to the accompanying drawings.

A FIFO control circuit according to the present invention enables input / output of data in byte units to / from a FIFO memory having a plurality of byte widths. FIG. 1 is a block diagram showing a basic configuration of a preferred embodiment of a FIFO control circuit according to the present invention. The FIFO control circuit of FIG.
O (first-in first-out memory) 14, input address counter 12, input bus switch 13, output bus switch 15,
It comprises an output address counter 16 and an address comparator 17.

The input bus switch 13 receives, for example, 16-bit input data, and outputs its output to a FIFO 14.
To enter. The input address counter 12 has a byte enable BE terminal 11, to which a byte enable signal is input and to which a write is performed.
A signal is input to the address counter 12 and the FIFO 14. The input address which is the output of the input address counter 12 is input to the FIFO 14 and the address comparator 17.

On the other hand, the output address counter 16 receives a byte enable signal and a read (read) signal. The output address output from the output address counter 16 is provided by an address comparator 17 and a FIFO 14
Is input to The output read from FIFO 14 is
Via the output bus switch 15, the output data becomes, for example, 16 bits. The address comparator 17 compares the input address and the output address from the input address counter 12 and the output address counter 16, respectively, and outputs FULL (full) or EMPTY (empty).

At the time of writing (writing) of the FIFO control circuit shown in FIG. 1, when data is written while inputting a byte enable indicating a valid byte of data to an input byte enable BE terminal 11, an input address counter 12
Counts up by the number of valid bytes. The data is swapped through the input bus switch 13 in ascending order of the address, and is simultaneously written to the FIFO 14.

At the time of reading (reading) of the FIFO control circuit, byte enable B of read data is used.
When E is read, data of the number of valid bytes is output from the byte having the lower address via the output bus switch 15. The output address counter 16 counts up by the effective address. The address comparator 17 compares the two addresses of the input address counter 12 and the output address counter 16, determines whether the valid data is empty or full in the FIFO 14, and outputs a signal EMP indicating the state.
Outputs a TY or FULL signal.

FIG. 2 is a block diagram showing a specific example of the FIFO control circuit according to the present invention. In this specific example, two Fs with a data width of 16 bits and a capacity of 1024 bytes are used.
4 shows a control circuit of the IFOs 205 and 206. This FIFO
The control circuit includes multiplexers 201 and 202, an input control unit 203, FIFOs 205 and 206, and an output control unit 21.
0, multiplexers 208 and 209, buffer 213,
214 and an address comparator 207.
The input control unit 203 and the output control unit 210 have address counters 204 and 211, respectively.

Here, input data having a 16-bit width is 8 bits.
Each of the bits (one byte) is divided (that is, a high byte and a low byte).
2 is input. The output of the multiplexer 201 is determined by the value of the H signal output from the input control unit 203 described later. On the other hand, the multiplexer 202 is determined by the value of the L signal output from the input control unit 203. When the H signal is “0” (or the L signal is “1”),
When the low byte data is from the multiplexer 202 and the H signal is “1” (or the L signal is “0”), the high byte data is output from the multiplexer 201. Here, both multiplexers 201 and 202 have the same function. The output of the multiplexer 201 is
Is input to On the other hand, the output of the multiplexer 202 is
The data is input to the FIFO 206. The address counter 204 incorporated in the input control unit 203 counts (counts) the number of valid data.

Output data of FIFO 205 and FIFO
The output data of O206 is
8 and 209. The output of the multiplexer 208 is determined by the H signal output from the output control unit 210. On the other hand, the output of the multiplexer 209 is determined by the L signal of the output control unit 210. Output control unit 2
When the H signal of No. 10 is "0" (that is, the L signal is "1"), the output data of the FIFO 205 is output. Also,
When the H signal of the output control unit 210 is “1” (that is, the L signal is “0”), the output data of the FIFO 206 is output. An address counter 211 incorporated in the output control unit 210 counts the number of valid data. Buffer 21
3 and 214 output the output data of the multiplexers 208 and 209 when the READ (read) signal is “0”. When the READ signal is “1”, the multiplexers 213 and 214 are set to high impedance, and no output data is output.

The memory capacity of each of the FIFO 205 and the FIFO 206 is, for example, 512 bytes.
It is 24 bytes. The address counter 204 is "0"
This is an 11-bit counter that counts up to "1023" (hexadecimal 3FF). F of the input control unit 203
The output address H_A to the IFO 205 outputs the value of the upper 10 bits of the address counter 204. FIFO
The output address L_A to the address counter 206 is the address counter 2
A value obtained by adding the value of the upper 10 bits of 04 and the value of 1 bit is output. The output signal IN_A of the input control unit 204 is
The same value as the output address L_A is input to the address comparator 207.
Output to

As the input signals BE_L and BE_H of the input control unit 203, signals indicating valid bytes of write data are input. If the input signal BE_L is “0”, the low byte of the input data is valid data, and if it is “1”, it is invalid data. On the other hand, if the input signal BE_H is "0", the high / low byte of the input data is valid data, and if it is "1", it is invalid data. Input signals BE_L, B of the input control unit 203
When one of E_H is 0, the address counter 204 counts up by one at the rising edge of the input signal WR. When both the input signals BE_L and BE_H are “0”, the address counter 204 counts up by two at the rising edge of the input signal WR.

The address counter 211 incorporated in the output control unit 210 is, like the address counter 204,
This is an 11-bit counter that counts from "0" to "1023" (3FF in hexadecimal). Output control unit 21
The output address H_A of 0 to the FIFO 205 outputs the value of the upper 10 bits of the address counter 204. F
As the output address L_A to the IFO 206, a value obtained by adding the value of the lower 10 bits to the upper 10 bits of the address counter 204 is input to the output address comparator 207.

As the input signals BE_L and BE_H of the output control section 210, signals indicating valid bytes of data to be written are input. Input signal BE_L is “0”
If so, the low byte of the input data is valid data, and if "1", it is invalid data. If the input signal BE_H is "0", the high / low byte of the input data is valid data, and if it is "1", it is invalid data. Input signal B of output control section 210
When one of E_L and BE_H is “0”, the address counter 211 at the rising edge of the input signal RD.
Counts up by one. Also, the input signal BE_L
When both of the address counter BE_H are “0”, the address counter 211 counts up by two at the rising edge of the input signal RD.

The address comparator 207 is connected to the input control unit 20
3 and the address IN output from the output control unit 210
_A and O_A are compared. "Address counter 20
4 = the value of the address counter 211 ”, F
Assuming that there is no valid data in IFOs 205 and 206,
The signal EMPTY is output as "1". On the other hand, “value of address counter 204 = value of address counter 211−1”
In this case, it is considered that there is no free space in the FIFOs 205 and 206, and the signal FULL is output as "1".

FIG. 3A shows output conditions of the L signal and the H signal of the input control unit 203 shown in FIG. FIG. 3B shows an output signal L_W of the input control unit 203.
And H_W output conditions. 3A and 3B, the input signals BE_L and BE_H are both “1”.
In this case, the address counter 204 is not counted up. The output conditions of the H signal and the L signal of the output control unit 210 are the same as those in FIGS. 3A and 3B described above.

Next, the operation of the FIFO control circuit shown in FIG. 2 will be described. The write operation will be described with reference to FIGS. 4 to 7, and the read operation will be described with reference to FIGS. First, when the FIFO control circuit of FIG.
The value of the address counter 204 is “0”, and the output control unit 2
The value of the eleventh address counter 211 is also “0”. The FULL signal of the address comparator 207 is “0”, EMPT
The Y signal becomes "1".

In the above-mentioned initial state, when 16-bit input data is written, the operation is as follows.
“0” is input to the input signals BE_L and BE_H of the input control unit 203. The output signal of the input control unit 203 is H
The signal is “1”, the L signal is “0”, the output signals H_A and L_A are “0”, and the output signal IN_A is “0”. Subsequently, when the WR signal is input (shift to L level), this signal is output as output signals H_W and L_W of the input control unit 203. At the rise of the WR signal, FIFO2
05 stores the high byte of the input data and the FIFO 206 stores the low byte of the input data.
The value of 4 becomes 2. EMPT of address comparator 207
The Y signal becomes “0”. FIG. 4 shows a timing chart of this series of operations.

Next, when one byte is written from the low byte data side, the operation is performed based on the input data and the input control unit 2.
03, “0” is input to the input signal BE_L, and “1” is input to BE_H. The output signal of the input control unit 203 is “1” for the H signal, “0” for the L signal, “1” for the H_A signal, and L_A for the H_A signal.
The signal is “1” and the IN_A signal is “1”. Here, when the WR signal is input, this signal is input to the input control unit 2
03 is output from L_W. At the rise of the WR signal, the low byte of the input data is stored in the FIFO 206, and the value of the address counter 204 becomes 3. FIG. 5 shows a timing chart of this series of operations.

Next, when writing 16-bit input data, "0" is input to the input data and the input signals BE_L and BE_H of the input control unit 203. The output signals of the input control unit 203 are “0” for the H signal, “1” for the L signal, “1” for the H_A signal, “2” for the L_A signal, and “2” for the IN_A signal. Therefore, when the WR signal is input, the signal is output to the H_W, L
_W. At the rising edge of the WR signal,
O205 stores the low byte of the input data, and the FIFO 206 stores the high byte of the input data. Then, the value of the address counter 204 becomes 5. FIG. 6 shows a timing chart of this series of operations.

Next, when one byte is written from the low byte data side, the operation is performed based on the input data and the input control unit 2.
03, “0” is input to the input signal BE_L, and “1” is input to BE_H. The output signals of the input control unit 203 are “0” for the H signal, “1” for the L signal, “1” for the H_A signal, and L_A
The signal is “1” and the IN_A signal is “1”. Here, when the WR signal is input, the signal is input to the input control unit 2.
03 is output from H_W. At the rise of the WR signal, the low byte of the input data is stored in the FIFO 205, and the value of the address counter 204 becomes 6. FIG. 7 shows a timing chart of this series of operations.

Next, when 16-bit data is read, the operation of BE_L and BE_H
"0" is input. The output signal of the output control unit 210 is
The H signal is “1”, the L signal is “0”, the H_A signal is “0”, the L_A signal is “0”, and the IN_A signal is “0”. At this time, the output of the multiplexer 208 outputs the output data of the FIFO 205, and the multiplexer 209 outputs the output data of the FIFO 206.
Next, RD (READ: read) of the output control unit 210
Are input to the buffers 213 and 214.
Outputs data. At the rise of RD, the value of the address counter 211 becomes 2. FIG. 8 shows a series of operation timing charts.

Next, in the operation when one byte is read from the low byte data side, "0" is input to BE_L and "1" is input to BE_H of the output control unit 210. The output signals of the output control unit 210 are “1” for the H signal, “0” for the L signal, “1” for the H_A signal, “1” for the L_A signal, and “1” for the IN_A signal. Next, when “0” is input to the RD signal, the buffer 214 outputs the output data of the FIFO 206 as valid data. FIF
The output data of O205 is output from the buffer 213, but this is not valid data. At the rise of the RD signal, the value of the address counter 211 becomes 3. FIG. 9 shows a series of operation timing charts.

Next, when 16-bit data is read, the operation of BE_L and BE_H
"0" is input. The output signal of the output control unit 210 is
The H signal is “0”, the L signal is “1”, the H_A signal is “1”, the L_A signal is “2”, and the IN_A signal is “2”. Therefore, when "0" is input to the RD signal, the output data of the FIFO 205 from the buffer 213,
The output data of the FIFO 206 is output from the buffer 214. At the rising edge of the RD signal, the address counter 2
The value of 11 becomes 5. FIG. 10 shows a series of operation timing charts.

Finally, when one byte is read from the low byte data side, the operation of the BE_L
"0" for BE and "1" for BE_H. The output signals of the output control unit 210 are “0” for the H signal, “1” for the L signal, “2” for the H_A signal, “3” for the L_A signal, and “3” for the IN_A signal. Therefore, when "0" is input to the RD signal, the output data of the FIFO 205, which is valid data, is output from the buffer 213. FIF
The output data of O206 is output from the buffer 214, but this is not valid data. At the rise of the RD signal, the value of the address counter 211 becomes “4”. FIG. 11 shows a series of operation timing charts.

The configuration and operation of the preferred embodiment of the FIFO control circuit according to the present invention have been described above in detail. However, such an embodiment is merely an example of the present invention and does not limit the present invention in any way. It will be readily apparent to those skilled in the art that various modifications can be made in accordance with the particular application without departing from the spirit of the invention.

[0033]

As will be understood from the above description, the FIFO control circuit according to the present invention has the following remarkable practical effects. First, while data of a plurality of bytes can be written and read at the same time, it is possible to input / output data from a byte (high byte, low byte in FIG. 2) desired to be accessed in byte units. Second
In a case where, for example, data transfer of a total of 10 bytes is performed in a data transfer of 16 bits width, for example,
Even if the write to O is interrupted at 5 bytes and the remaining 5 bytes of data are restarted and the first 16-bit data is valid for both bytes, the FIFO stores the data packed in byte units. 1 when reading
It becomes possible to output 6-bit data in five cycles.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a preferred embodiment of a FIFO control circuit according to the present invention.

FIG. 2 is a block diagram of a specific example of the FIFO control circuit shown in FIG.

FIG. 3 is an operation explanatory diagram of the input control unit shown in FIG. 2;
(A) shows the output conditions of the L and H signals, and (B) shows the L_W signal.
FIG. 7 is a diagram illustrating output conditions of the H_W signal and the H_W signal.

FIG. 4 is a timing chart showing a write operation of the FIFO control circuit shown in FIG. 2;

FIG. 5 is a timing chart illustrating a write operation of the FIFO control circuit illustrated in FIG. 2;

FIG. 6 is a timing chart showing a write operation of the FIFO control circuit shown in FIG. 2;

FIG. 7 is a timing chart showing a write operation of the FIFO control circuit shown in FIG. 2;

FIG. 8 is a timing chart showing a read (read) operation of the FIFO control circuit shown in FIG. 2;

FIG. 9 is a timing chart showing a read operation of the FIFO control circuit shown in FIG. 2;

FIG. 10 is a timing chart showing a read operation of the FIFO control circuit shown in FIG. 2;

FIG. 11 is a timing chart showing a read operation of the FIFO control circuit shown in FIG. 2;

[Explanation of symbols]

 11 Byte enable terminal 12, 204 Input address counter 13 Input bus switch 15 Output bus switch 16, 211 Output address counter 17, 207 Address comparator 203 Input control unit 210 Output control unit 14, 205, 206 FIFO 201, 202, 208, 209 Multiplexer 213, 214 Buffer

Claims (6)

[Claims] 1. A FIFO control circuit for writing and reading input data to and from a FIFO (first-in first-out memory) having a plurality of byte widths, comprising: an input bus switch arranged on an input side of the FIFO for inputting and outputting input data in byte units; An output bus switch disposed on the output side of the FIFO for inputting / outputting an output from the FIFO in byte units, and an input / output control having a byte enable terminal and an address counter, respectively, for controlling writing and reading of the FIFO A FIFO control circuit, comprising: 2. The FIFO control circuit according to claim 1, wherein said FIFO comprises a plurality of FIFOs each having a 1-byte width. 3. The FIFO control circuit according to claim 1, wherein said input bus switch and said output bus switch each include a plurality of multiplexers. 4. The FIFO control circuit according to claim 1, further comprising a buffer on the output side of said output bus switch for outputting output data in response to a read signal or for providing high impedance. 5. An address comparator according to claim 1, further comprising an address comparator for comparing the input address from said input control section and the output address from said output control section to generate a full or empty output. Or a FIFO control circuit. 6. The method according to claim 1, wherein writing and reading are performed in units of a plurality of bytes or in units of one byte.
6. The FIFO control circuit according to any one of claims 1 to 5,