JP2009140040A - Data processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To execute data processing at high speed for selecting only necessary data from a plurality of data, and storing the data in a memory by packing the data in an arbitrary width. <P>SOLUTION: This data processor is configured to process a plurality of data making a pair with a validity flag having "0" showing invalidity or "1" showing validity to be continuously input with a sequential relation in each cycle, and provided with a validity flag integrator 20 which fetches every prescribed number of data in each cycle along the sequential relation, and outputs the total value of the validity flags of all the data whose sequence is prior to the data as the validity flag integrated value of the data; and a storage device 10 in which the data designated as validity by the validity flag are written in an address corresponding to the "quotient" of the memory of the number corresponding to "remainder" in dividing the validity flag integrated value corresponding to the data by the number of memories. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a data processing device that selects only necessary data from a plurality of input data, arranges them at arbitrary intervals at high speed, and stores them in a storage device.

  In some cases, it is necessary to perform a thinning process in which only necessary data is extracted from a plurality of input data, and written in the storage device in order. The normal method is to determine the necessity / unnecessity of the target input data one by one and write the input data determined to be necessary to the next address of the previously written input data. . As a conventional method for performing this processing by hardware, there is a method using a FIFO memory 100 shown in FIG.

  In this method, first, each set of input data and a valid flag indicating necessity / unnecessity of the input data are paired and input one by one. At this time, only the input data whose validity flag value is “1” indicating validity is packed and stored in the FIFO memory 100 in the order of input. In the example of FIG. 15, only D1 and D4 of the input data D1, D2, D3, D4, and D5 are stored in the FIFO memory 100 and stored. Input data is input in the order of D1, D2, D3, D4, and D5, and each time the input data is input, it is determined whether the valid flag is “1” or “0”, and only D1 and D4 that are “1”. Is stored in the FIFO memory 100. As a result, only the input data D1 and D4 to be stored can be stored in the FIFO memory 100 in a packed manner.

As another conventional technique, Patent Document 1 describes a method of filling only necessary input data from serial input data, outputting the data in parallel, and writing the data in a register. In this method, when serial data is converted into parallel data, the required input data is shifted in data position by the shift register by the number of unnecessary input data immediately before that. This makes it possible to convert serial data that has been skipped due to a mixture of necessary / unnecessary input data into parallel data in which only necessary input data is packed.
JP-A-8-123683

  However, the method of storing the data in the FIFO memory 100 has a problem that it is impossible to increase the data processing speed because input data must be processed sequentially one by one. Further, even with the method described in Patent Document 1, the processing speed cannot be increased because it is necessary to sequentially determine the shift amount and determine the storage location for each serial input data. There's a problem.

  Furthermore, when writing target data to a memory such as a RAM instead of a register, there is a restriction that data can be written only in units of one word at a time (the size of one word depends on the memory). There also arises a problem that data must be written after it has been packed until the minute data is packed. For example, when writing to a memory of 4 bits per word, it is impossible to write data for only 1 bit in the first write, and write the remaining 3 bits in the second write. Therefore, when this conventional method is used, there is a problem that data must be buffered and written until 4 bits of data are collected.

  It is an object of the present invention to perform high-speed data processing by selecting only necessary data from a plurality of data, and storing the data in a memory with an arbitrary width stored in a memory in parallel. And

In order to achieve the above object, a data processing apparatus according to a first aspect of the present invention is compatible with a valid flag having “0” indicating invalidity, a positive integer value indicating validity, or a negative integer value indicating validity. In a data processing apparatus that processes a plurality of data that are successively input with an order relationship, every cycle, the data is fetched in a predetermined number along the order relationship for each cycle, and from the data A valid flag integrator that outputs the sum of the valid flag values of all the data in the previous order, or the value obtained by adding the valid flag value of the data to the valid flag accumulated value of the data, and a plurality of addresses The data designated as valid by the valid flag is “remainder when the valid flag integrated value corresponding to the data is divided by the number of memories. Characterized in that it comprises a storage device to be written into the corresponding address in the "quotient" of the memory in the corresponding number.
According to a second aspect of the present invention, in the data processing device according to the first aspect, the storage device is a binary number of the effective flag integrated value when the number of data to be fetched by the predetermined number is represented by n 2. Writing is performed based on the “remainder” and the “quotient” obtained directly from the display.
According to a third aspect of the present invention, in the data processing device according to the first aspect, the storage device stores the effective flag integrated value in the memory when the predetermined number of data to be captured is not represented by 2 to the nth power. Writing is performed based on the “remainder” and the “quotient” obtained by a divider that divides by a number.
According to a fourth aspect of the present invention, in the data processing device according to the first, second, or third aspect, when two or more continuous data of the input data is a grouped data, each grouped data A valid flag having the same value is assigned to each.
According to a fifth aspect of the present invention, in the data processing device according to the first, second, or third aspect, the effective flag integrated value obtained by the effective flag integrator is multiplied by an enlargement factor and output as a new effective flag integrated value. The multiplication means to perform is provided.
According to a sixth aspect of the present invention, there is provided a data processing device that is paired with a valid flag having “0” indicating invalidity or “1” indicating validity and that sequentially inputs a plurality of pieces of data input in an order relationship. In the data processing apparatus that processes each time, the data is fetched in a predetermined number along the order relationship for each cycle, and the order of the valid flag values of the previous data in the cycle from the data, or It consists of a valid flag integrator that outputs a value obtained by adding the value of the valid flag of the data as a valid flag integrated value of the data and a plurality of memories having a plurality of addresses, and is designated as valid by the valid flag. A storage device in which data is written at an address corresponding to the cycle of the specific memory indicated by the effective flag integrated value corresponding to the data. And wherein the Rukoto.

  According to the present invention, it is possible to perform parallel processing on a plurality of data by selecting arbitrary data from a plurality of data and storing the data in an arbitrary width. Thereby, for example, processing such as compression and expansion of information data such as images and sounds can be executed at high speed.

<Outline of the invention>
1A and 1B show the flow of data processing by the data processing apparatus of the present invention. In this figure, as an example, among the eight data D0, D1, D2, D3, D4, D5, D6, and D7, six data D0, D3, D4 to D7 are selected, and the order of the data numbers It shows the case where it is packed and stored. Four pieces of data are input simultaneously, arranged in the order of memories M0, M1, M2, and M3 from the youngest address of the four memories M0 to M3 of the storage device 10, and written simultaneously. In this way, since two or more data are not simultaneously written in one memory by one writing process, a maximum of four data can be written by simultaneous parallel processing.

  FIG. 1A shows processing of the first four input data D0 to D3. Each data has a valid flag (“1” is valid and “0” is invalid) indicating the necessity / unnecessity by 1 bit. In this data processing apparatus, the necessity / unnecessity of the data is determined by the validity flag. Among the input data D0 to D3, the validity flags of the data D0 and D3 are “1”, and the validity flags of the remaining D1 and D2 are “0”. Assuming that data has already been written to the address AD0 of the memories M0, M1, and M2, the data D0 is written to the address AD0 of the next memory M3, and the data D3 is written to the address AD1 of the memory M0.

  The processing of the next input data D4 to D7 is shown in FIG. 1B. Since all the input data D4 to D7 are to be stored, their valid flags are all “1”. The input data D4 is written to the address AD1 of the memory M1, the input data D5 is written to the address AD1 of the memory M2, the input data D6 is written to the address AD1 of the memory M3, and the data D7 is written to the address AD2 of the memory M0.

  In this way, among the eight input data D0 to D7, six input data D0, D3, and D4 to D7 to be stored are written in the memories M0 to M3 from the lowest address.

  2A and 2B are explanatory diagrams of data processing operations by the data processing apparatus of the present invention. In this data processing apparatus, input data lines DATA0 to DATA3 are connected to valid flags V0 to V3 that indicate necessity / unnecessity by 1 bit for each input data. Then, the data to be input there and a valid flag are combined, and four sets are input simultaneously and processed in parallel.

  In FIG. 2A, data D0 to D3 are input to the input data lines DATA0 to DATA3 as the first input data, and among these, the valid flags V0 and V3 of the data D0 and D3 to be stored are “1”, and the remaining data The valid flags V1 and V2 of the data D1 and D2 are set to “0”. FIG. 2B shows processing for the second input. Data D4 to D7 are input to the input data lines DATA0 to DATA3, respectively. Since all the data D4 to D7 are stored, the valid flags V0 to V3 for the data D4 to D7 are all “1”.

  With respect to the input data, the effective flag integrator 20 calculates an integrated value obtained by summing up the effective flag values of all the data in the previous order for each data, and outputs this as an effective flag integrated value. The valid flag integrator 20 includes an effective flag integration head value storage unit 21, three adders 22 that add the valid flag values, and the addition result of the adder 22 and the validity flag integration head value storage unit 21. And four adders 23 for adding the flag integrated head value.

  In this example, since three pieces of data have already been written in the address AD0 of the memory M0, the memory M1, and the memory M2, “3” is given as the effective flag integrated start value that is the start value of the effective flag integrated value. Then, the effective flag integrated value for data D0 to D3 and the effective flag integrated head value used in the next calculation cycle (calculation cycle for data D4 to D7) are calculated as follows.

D0 valid flag integrated value = valid flag accumulated start value D1 valid flag accumulated value = valid flag accumulated start value + D0 valid flag value D2 valid flag accumulated value = valid flag accumulated start value + D0 valid flag value + D1 valid flag Value D3 valid flag accumulated value = valid flag accumulated start value + D0 valid flag value + D1 valid flag value + D2 valid flag value Valid flag accumulated start value of next calculation cycle = valid flag accumulated start value + D0 valid flag value + D1 Valid flag value + D2 valid flag value + D3 valid flag value

  As a result, as shown in FIG. 2A, the effective flag integrated values for the data D0, D1, D2, and D3 are “3”, “4”, “4”, and “4”, respectively. The value is “5”.

FIG. 2B shows calculation processing for data D4 to D7 in the next cycle. Using the value “5” calculated in the previous calculation cycle as the effective flag integration head value, the same calculation is performed as follows.
D4 valid flag integrated value = valid flag accumulated start value D5 valid flag accumulated value = valid flag accumulated start value + D4 valid flag value D6 valid flag accumulated value = valid flag accumulated start value + D4 valid flag value + D5 valid flag Value D7 valid flag accumulated value = valid flag accumulated head value + D4 valid flag value + D5 valid flag value + D6 valid flag value Valid flag accumulated top value in next calculation cycle = valid flag accumulated top value + D4 valid flag value + D5 Valid flag value + D6 valid flag value + D7 valid flag value

  As a result, as shown in FIG. 2B, the effective flag integrated values for the data D4, D5, D6, and D7 are “5”, “6”, “7”, and “8”, respectively. The value is “9”.

  The effective flag integrated value obtained in this way indicates the number of the data from the beginning of all the data of the effective flag “1”. However, the top data at the address AD0 of the memory M0 is counted as 0th. Therefore, the data D0 is the third. On the other hand, in the example of FIGS. 2A and 2B, the data having the valid flag “1” is sequentially written to the addresses of the memories M0 to M3.

  Accordingly, the “remainder” obtained by dividing the effective flag integrated value of each data by 4 indicates which memory in the memory M0 to the memory M3 is written, and the “quotient” obtained by dividing the effective flag integrated value by 4 is the address of the memory to be written. Is shown. Further, in this example, when the effective flag integrated value is written in binary, the lower 2 bits are the “remainder” obtained by dividing the effective flag integrated value by 4, and the numerical value of the third bit or more is the effective flag integrated value of 4. Since the divided “quotient” is obtained, the effective flag integrated value of each data indicates to which address of which memory the data is written.

  For example, the effective flag integrated value for the data D4 in FIG. 2B is “5”, which is “0101” when displayed in binary. Of these, the lower 2 bits are “01”, which is “1” when displayed in decimal, and the third and subsequent bits are “01”, which is “1” when displayed in decimal. Therefore, the data D4 is written to the address AD1 of the memory M1.

  In this way, after calculating the effective flag integrated value of each data, for the data for which the effective flag is “1”, the memory is selected by the lower 2 bit value of the effective flag integrated value, and the numerical value of the third bit or more Is written in the memory using the address of the memory. According to this method, it is possible to simultaneously perform parallel processing of selecting data to be written for four pieces of input data and sequentially writing the data to the memory.

  In the above description, the configuration in which four pieces of data are input has been described. This means that 2 n bytes such as 4 bytes, 8 bytes, and 16 bytes are normally used as the data unit of the digital circuit, and the number of input data is 2 such as 2, 4, 8, and 16 This is explained in this example because the configuration is simpler to the nth power, and even if the number of input data is not a second power of 2, such as 3, 5, 6, etc., the present invention Is applicable.

  The reason why the configuration is simpler when the number of input data is 2 to the power of n is as follows. In the embodiment, it is necessary to obtain “remainder” and “quotient” obtained by dividing the effective flag integrated value by the number of input data (4 in the above example), but when the number of input data is 2 to the nth power, There is no need to provide an arithmetic circuit. Since the valid flag integrated value is represented by a binary number, for example, when the number of input data is 4, the last two digits of the valid flag integrated value are “remainder”, and the third and higher digits are “quotient”. When the number of input data is 8, it is necessary to obtain the “remainder” and “quotient” obtained by dividing the effective flag integrated value by 8, but the last 3 digits of the effective flag integrated value is “remainder”, the fourth digit and higher. This part is a “quotient”, and in this case, it is not necessary to provide a division circuit.

  On the other hand, even when the number of input data is not 2 to the power of n, if the “remainder” and “quotient” obtained by dividing the effective flag integrated value by the number of inputs are calculated, the same processing can be performed. be able to. However, in this case, it is necessary to provide a division circuit that divides the effective flag integrated value by the number of input data. This example will be described later.

<Example 1>
FIGS. 3A and 3B show Embodiment 1 in which only necessary data is selected from a plurality of input data and written into a storage device 10 such as a register by using the data processing apparatus of the present invention. Is. As in the example of FIGS. 2A and 2B, among the first input data D0 to D3 and the second input data D4 to D7, six data D0, D3, and D4 to D7 are stored in the memories M0 to M3 with younger addresses. A case where data is written in the direction from the side will be described.

  First, the configuration of the data processing apparatus will be described. Out of the effective flag integrated values of each data calculated by the effective flag integrator 20, the lower 2 bits are output as AD0_X to AD3_X, respectively. The AD0_X to AD3_X and the valid flags V0 to V3 are input to the selector control signal generation circuit 30. On the other hand, among the valid flag integrated values of the respective data, values of the third bit or more are output as AD0_Y to AD3_Y, respectively. The AD0_Y to AD3_Y and the input data lines DATA0 to DATA3 are connected to the data selector 40. The control signals SEL0_S to SEL3_S of the data selector 40 are output from the selector control signal generation circuit 30 and input to the data selector 40. The data selector 40 outputs data signals OUT_DATA0 to OUT_DATA3, data write address signals OUT_AD0 to OUT_AD3, and data write control signals OUT_WE0 to OUT_WE3, which are input to the memories M0 to M3, respectively.

  FIG. 4 shows the configuration of the selector control signal generation circuit 30. This module is composed of a plurality of comparators 31 and an AND circuit 32, and inputs valid flags V0 to V3 and AD0_X to AD3_X which are lower two bit values of the valid flag integrated value, and outputs data selector control signals SEL0_S to SEL3_S. To do. Each of the data selector control signals SEL0_S to SEL3_S is a 4-bit signal and is calculated as follows.

SELn_S [0] = (AD0_X = n) & V0
SELn_S [1] = (AD1_X = n) & V1
SELn_S [2] = (AD2_X = n) & V2
SELn_S [3] = (AD3_X = n) & V3
However, n = 0-3
The meaning of the above expression “SELn_S [0] = (AD0_X = n) & V0” means SELn_S [0] = True when AD0_X = n and V0 = True. [0] indicates the 0th bit.

For example, in the example of FIG. 3A, AD0_X = 3, AD1_X = 0, AD2_X = 0, AD3_X = 0, and V0 = 1, V1 = 0, V2 = 0, V3 = 1, so SEL0_S is
SEL0_S [0] = 0
SEL0_S [1] = 0
SEL0_S [2] = 0
SEL0_S [3] = 1
It becomes. That is, SEL0_S = 1000. Similarly, SEL1_S = 0000, SEL2_S = 0000, and SEL3_S = 0001 are output.

  FIG. 5 shows the configuration of the data selector 40. The data selector 40 receives input data lines DATA0 to DATA3 and values AD0_Y to AD3_Y of the third bit or more of the valid flag integrated value of each data. DATA0 and AD0_X, DATA1 and AD1_X, DATA2 and AD2_X, and DATA3 and AD3_X are set as a set and input to all four selectors SEL0 to SEL3 of the data selector 40. The selectors SEL0 to SEL3 switch the output signals as follows according to the control signals SEL0_S to SEL3_S from the selector control signal generation circuit 30, respectively.

When SELn_S = 0001
OUT_DATAn ← DATA0
OUT_ADn ← AD0_Y
OUT_WEn ← True
When SELn_S = 0010
OUT_DATAn ← DATA1
OUT_ADn ← AD1_Y
OUT_WEn ← True
When SELn_S = 0100
OUT_DATAn ← DATA2
OUT_ADn ← AD2_Y
OUT_WEn ← True
When SELn_S = 1000
OUT_DATAn ← DATA3
OUT_ADn ← AD3_Y
OUT_WEn ← True
When SELn_S is a value other than the above
OUT_DATAn ← Don't care (any value may be set)
OUT_ADn ← Don't care (any value may be set)
OUT_WEn ← False
However, n = 0-3
Here, OUT_WEn is a write enable signal of the memory Mn, and a write operation is performed when True.

For example, in the example of FIG. 3A, as described above,
SEL0_S = 1000
Therefore, the output of the selector SEL0 is OUT_DATA0 = D3 (= DATA3), OUT_AD0 = 1 (= AD3_Y), and OUT_WE0 = True (= V3). Similarly,
OUT_DATA1 = Don't care, OUT_AD1 = Don't care, OUT_WE1 = False
OUT_DATA2 = Don't care, OUT_AD2 = Don't care, OUT_WE2 = False
OUT_DATA3 = D0 (= DATA0), OUT_AD3 = 0 (= AD0_Y), OUT_WE3 = True (= V0)
It becomes.

  With such a configuration, only the data having the valid flag value “1” among the input data is designated by ADn_Y of the memory designated by the lower 2-bit value ADn_X of the valid flag integrated value. Written to the address.

  The valid flag accumulator 20 of the present invention has a simple structure including an adder 22 that adds valid flags to each other, and an adder 23 that adds the addition result of the adder 22 and the valid flag accumulated head value. Depending on the scale of parallelism and the performance of the adder, it is possible to calculate the effective flag integrated value and write the data into the memory usually in one clock. Since a plurality of input data can be simultaneously processed in parallel, data processing can be performed at a very high speed.

<Example 2>
In the first embodiment, four pieces of input data are simultaneously input and written in the four memories M0 to M3 of the storage device 10. However, in the second embodiment, as shown in FIG. Four pieces of data are input simultaneously and written in the eight memories M0 to M7 of the storage device 10A. In this case, the “remainder” obtained by dividing the effective flag integrated value of each data by 8 indicates which memory in the memories M0 to M7 is written, and the “quotient” obtained by dividing the effective flag integrated value by 8 is the memory to be written. Indicates the address.

  Therefore, in this example, the lower 3 bits of the valid flag integrated value of each data are set as AD0_X to AD3_X, and the value of the fourth bit or more of the effective flag integrated value is written as AD0_Y to AD3_Y at the address indicated by this value. do it.

<Example 3>
In the third embodiment, as shown in FIG. 7, four pieces of input data are simultaneously inputted and written into the six memories M0 to M5 of the storage device 10B. This apparatus has a divider 50 that divides the effective flag integrated value of each data by “6”. Then, it is determined which memory of the memories M0 to M5 is written according to the “remainder” obtained by dividing the effective flag integrated value by 6, and the memory of the memory to be written is determined by “quotient” obtained by dividing the effective flag integrated value by “6”. The address is determined.

<Example 4>
In the valid flag integrator 20 shown in FIGS. 2A, 2B, 3A and 3B, the valid flags of all the data preceding the data are obtained as the sum of the valid flags of each data. On the other hand, in the fourth embodiment shown in FIGS. 8A and 8B, the valid flag integrated value of each data is obtained by adding the valid flags of all the data before the data and the valid flag of the data itself. I have to. On the other hand, the effective flag integration head value is set to a value smaller by “1” than the method of FIGS. 2A, 2B, 3A, and 3B. Also by this method of the present embodiment, the same effective flag integrated value as in the first embodiment can be calculated, and only data with the effective flag “1” can be selected and written in order. Become.

8A and 8B show a data processing method and configuration according to the fourth embodiment when the same input data as in the first embodiment (FIGS. 3A and 3B) is input. First, in FIG. 8A, “2” is given as the initial value of the effective flag integration head value. Then, the effective flag integrated value for the input data D0 to D3 and the effective flag integrated head value used in the next calculation cycle (the calculation cycle for D4 to D7) are calculated as follows.
D0 effective flag integrated value = effective flag integrated start value + D0 effective flag value D1 effective flag integrated value = effective flag integrated start value + D0 effective flag value + D1 effective flag value D2 effective flag integrated value = effective flag integrated start Value + D0 valid flag value + D1 valid flag value + D2 valid flag value D3 valid flag accumulated value = valid flag accumulated head value + D0 valid flag value + D1 valid flag value + D2 valid flag value + D3 valid flag value Effective flag integrated head value of cycle = effective flag integrated value of D3

  As a result, as shown in FIG. 8A, the effective flag integrated values for the input data D0 to D3 are “3”, “3”, “3”, and “4”, respectively. 4 ".

FIG. 8B shows calculation processing for input data D4 to D7 in the next cycle. Using the value 4 calculated in the previous calculation cycle as the effective flag integration head value, the same calculation is performed as follows.
D4 effective flag integrated value = effective flag integrated start value + D4 effective flag value D5 effective flag integrated value = effective flag integrated start value + D4 effective flag value + D5 effective flag value D6 effective flag integrated value = effective flag integrated start Value + D4 valid flag value + D5 valid flag value + D6 valid flag value D7 valid flag accumulated value = valid flag accumulated head value + D4 valid flag value + D5 valid flag value + D6 valid flag value + D7 valid flag value Next calculation Effective flag integrated value of cycle = Effective flag integrated value of D7

    As a result, as shown in FIG. 8B, the effective flag integrated values for the input data D4 to D7 are “5”, “6”, “7”, and “8”, respectively. 8 ”.

  As described above, also by the method according to the fourth embodiment, the same value as the value obtained in the first embodiment can be calculated as the valid flag integrated value of the data whose valid flag is “1”. Using the obtained effective flag integrated value, data can be packed and written in the memories M0 to M3 of the storage device 10 in the same manner as in the first embodiment.

<Example 5>
In this embodiment, the method of the present invention is applied to input data having different sizes. In the example shown in FIGS. 9A and 9B, the input data D0, D1, and D3 are 1 byte, D2 is 2 bytes, and D4 is 3 bytes. Of these, only D0, D2, and D4 shown by shading are selected and packed in order. In this case, the data is stored in the storage device 10. Each data has a valid flag for each byte that is the unit data amount. That is, the 2-byte D2 has two valid flags and the 3-byte D4 has three valid flags. Then, the valid flag of the data desired to be stored in the storage device 10 is set to “1”. For such a pair of input data and valid flag, a valid flag integrated value is calculated for each byte of each data by the same calculation as in the first to fourth embodiments.

  In FIG. 9A, the effective flag integrated value of the data D0 is “0”, and the effective flag integrated values of the first byte and the second byte of the data D2 are “1” and “2”, respectively. From now on, the first byte of D0 and D2 and the second byte of D2 are written to the address AD0 of the memories M0, M1 and M2, respectively. Thus, D0 and D2 can be packed and written to the memories M0, M1 and M2.

  Similarly, in FIG. 9B, the effective flag integrated values of the first byte, the second byte, and the third byte of the data D4 to be stored are obtained as “3”, “4”, and “5”, respectively. Are written in the address AD0, the address AD1 of the memory M0, and the address AD1 of the memory M1. As a result, it is possible to execute a process of extracting only 1-byte data D0, 2-byte data D2, and 3-byte data D4 and sequentially storing them in the memory as shown in FIG. .

<Example 6>
In the above Examples 1 to 5, the valid flag value of each data is set to “0” or “1”. On the other hand, in the sixth embodiment, by setting the effective flag value of each data to a value other than “1” such as “0”, “2”, “3”, etc. This makes it possible to extend the interval from the original input interval.

  In the example shown in FIG. 10A, the valid flag values for the input data D0 to D3 are all set to “2”, and the valid flag integrated value is calculated by the same method as in the first embodiment. Then, the effective flag integrated values for the data D0 to D3 are “0”, “2”, “4”, and “6”, respectively. From these values, the data D0, D1, D2, and D3 are written to the address AD0 of the memories M0, M2, M4, and M6 of the storage device 10A. As a result, as shown in FIG. 10A, data D0 to D3 are written in every other memory of the storage device 10A, and the data interval can be increased.

  However, in this example, if the memory of the write destination is a type that can only write to one address at a time, 8 or more times twice the number of input data (in this case 4) It is necessary to prepare the number of memories. If the number is less than 8, the writing operation may be performed simultaneously on different addresses in the same memory, so care must be taken.

  In the example shown in FIG. 10A, data is not written in the memories M1, M3, M5, and M7, and is left blank. On the other hand, in the example of FIG. 10B, data D0 is written in the memories M0 and M1, data D1 is written in the memories M2 and M3, data D2 is written in the memories M4 and M5, and data D3 is written in the memories M6 and M7. You can also. For each data, the effective flag integrated value is used as a head address, and each data is written to memory locations corresponding to the number of effective flag values. Thereby, for example, the present invention can be applied to enlargement processing of image data into an image having a larger area.

  As shown in FIG. 10C, it is also possible to select only arbitrary data from the input data and arrange them at specified intervals. In the example of FIG. 10C, among the input data D0 to D3, the valid flags of D0, D2, and D3 are set to “2”, and the valid flag of D1 is set to “0”. When the effective flag integrated value of each data of D0 to D3 is calculated by the same calculation as in the first embodiment, it becomes “0”, “2”, “2”, “4”, respectively. Among these, when D0, D2, and D3 whose valid flag is not “0” are written in the storage device using the valid flag integrated value as an address, D0, D2, and D3 are stored in the memories M0, M2, and M4 as shown in FIG. 10C. It is written at address AD0.

  FIG. 10D shows the same input data, valid flag value, and calculated valid flag integrated value as in FIG. 10C, but, as in FIG. 10B, each data is not left blank and is filled with the previous data. It is. For each data, the effective flag integrated value is used as a head address, and each data is written to memory locations corresponding to the number of effective flag values. Thereby, for example, the image data can be enlarged to an image having a larger area. In the case of FIG. 10B, the data can be expanded uniformly. However, as shown in FIG. 10D, it is also possible to select an arbitrary area of the image data and expand it.

  As shown in FIG. 10E, the valid flag value of each data can be arbitrarily set, and the data selection and the data interval can be arbitrarily set. When the valid flag values for the input data D0 to D3 are set to “2”, “0”, “3”, “2”, respectively, the valid flag integrated values are “0”, “2”, “2”, “5”, respectively. " Among these, the data D0, D2, and D3 whose valid flag values are not “0” are written in the addresses AD0 of the memories M0, M2, and M5, respectively, according to the respective valid flag integrated values.

  As described above, except for the data D1 in which the valid flag is set to “0”, other data D0, D2, and D3 can be written to the storage device 10A at intervals of the set valid flag values. Also in this case, it goes without saying that the data before and after the data can be written in the blank area between the data as in FIGS. 9A and 9B. As shown in the present embodiment, according to the method of the present invention, it becomes possible to select arbitrary data by setting the effective flag value and arrange it at arbitrary intervals.

<Example 7>
In the above-described sixth embodiment, the method of outputting the data by expanding the interval at the time of input by setting the data expansion rate such as “2” or “3” as the valid flag value of each data has been shown. On the other hand, in the present embodiment, the valid flag accumulator 20 accumulates values obtained by multiplying the input valid flag value by an enlargement factor.

  In the example shown in FIG. 11A, input data D0, D1, D2, and D3 and valid flag values “1”, “0”, “1”, and “1” are input. On the other hand, the valid flag accumulator 20 accumulates values obtained by multiplying each valid flag value by the data enlargement magnification 2. As a result, the effective flag integrated values to be output are “0”, “2”, “2”, and “4”, respectively. Among these, the data D0, D2, D3 whose effective flag integrated value is not “0” is written in each memory of the storage device 10A based on the effective flag integrated value based on the method of the first embodiment or the like. As a result, the data D0, D2, and D3 excluding the data D1 are written to the address AD0 of the memories M0, M2, and M4, and can be arranged on the storage device 10A with the specified interval “2” expanded.

  FIG. 11B shows a configuration around the valid flag integrator 20 of the present embodiment. The output value of the valid flag integrator 10 of the first embodiment shown in FIG. 3A is input to a multiplier 60 that multiplies by the data enlargement magnification, and the result is output.

  FIG. 11C uses a shift computing unit 60 </ b> A instead of using the multiplier 60. For example, when the data enlargement magnification is set to 2 × or 4 ×, the input value may be shifted by 1 shift or 2 shift to the left. 11A and 11B show the case where the input data is multiplied by a uniform data enlargement ratio, but the data enlargement ratio may be variably set for each data. Further, similarly to the sixth embodiment shown in FIGS. 10A to 10E, data before and after the data may be written in a blank area between the data.

<Example 8>
In the first to seventh embodiments described above, all the input data whose valid flag values are not “0” are sequentially packed and arranged so that the valid flag values of all the input data are integrated. On the other hand, in this embodiment, the effective flag integrator 20B calculates the effective flag integrated value for each input data and writes it in the memory of the storage device 10D. For this reason, the same fixed value is set as the effective flag integration head value every time.

  The example of FIG. 12A is configured such that only the data with the valid flag value “1” out of each input data is left-justified and output, and this is written to the storage device 10C using the FIFO memory. . First, with respect to the first input data 0 (= D0, D1, D2, D3, valid flag = “1”, “0”, “0”, “1”), the effective flag integration head value is set to “0”. The effective flag integrated value of each data is calculated to obtain “0”, “1”, “1,” “1”, respectively. Among these, the data D0 and D3 having the valid flag value “1” are arranged and output sequentially from the left according to the value of the valid flag integrated value. As a result, D0 and D3 whose valid flag value is “1” are output left justified.

  Next, for the second input data 1 (= D4, D5, D6, D7, valid flag = “1”, “0”, “1”, “0”), the valid flag integration top value is “ The effective flag integrated value of each data is calculated as “0”. As a result, “0”, “1”, “1”, and “2” are obtained, respectively. Among these, D4 and D6 whose valid flag value is “1” are arranged and output in order from the left according to the value of the valid flag integrated value. Then, the output data is written in the two memories FIFO_0 and FIFO_1 of the storage device 10D. With this configuration, it is possible to write only the selected data in the two memories FIFO_0 and FIFO_1 in order.

  The example of FIG. 12B uses the storage device 10D having the memory M0 and the memory M1 to be written by addressing instead of the storage device 10C having the two memories FIFO_0 and FIFO_1 in the configuration of FIG. A counter 24 for counting the number of data inputs is provided in 20B, and the value indicated by the counter value is used as a write address to the storage device 10D.

  First, with respect to the first input data 0, the effective flag integrated values of the data D0 and D3 whose effective flag value is “1” are calculated as “0” and “1”, respectively, so that they are stored in the memories M0 and M1, respectively. Write. The write address AD_Y is set to AD0 according to the data number counter value.

  Next, for the second input data 1, the valid flag integrated values of the data D4 and D6 whose valid flag value is “1” are “0” and “1”, respectively, and the data number counter value is “1”. Are written to the next address AD1 of the memories M0 and M1, respectively. With this configuration, it is possible to write only selected data in the two memories M0 and M1 in order.

  In the valid flag integrator 20B shown in FIGS. 12A and 12B, the valid flag integrated value of each data is obtained by summing up the valid flags of the data before the data for each input. Instead, an effective flag integrator 20C having the structure shown in FIG. 12C may be used. In the valid flag integrator 20C shown in FIG. 12C, the valid flag accumulated value of each data is obtained by adding the total value of the valid flags of the data before the data and the valid flag of the data itself for each input. I have to. On the other hand, the effective flag integrated value is set to “−1”. Even if the output value of the valid flag integrator 20C configured in this way is used, the same function as that of FIGS. 12A and 12B can be obtained.

  In the eighth embodiment, it is necessary that the number of data having the valid flag “1” is within two. In other cases, a means for error processing is provided. In the above description, the case where the effective flag integration top value is fixed to “0” (FIGS. 12A and 12B) or “−1” (FIG. 12C) has been described as an example. It may be set to a value other than “−1”, or this value may be variably set for each input. This makes it possible to change the output destination memory of the first valid data for each input.

<Example 9>
In the valid flag integrators 20, 20A, 20B, and 20C of the first to eighth embodiments described above, the valid flag value is input from the outside. However, as shown in FIG. The valid flag integrator 20D may be set internally. At this time, the valid flag value to be set may be a fixed value or may be dynamically set for each data.

<Example 10>
In the first to ninth embodiments, the case where “0” or “positive integer value” is taken as an example of the valid flag value has been described as an example. Instead, “0” or “negative integer value” is taken. You may do it. At this time, the calculated effective flag integrated value is “0”, “−1”, “−2”, etc., and the corresponding data is written to the addresses AD0, AD1, and AD2 of the storage device. Thus, the same data processing can be performed.

<Example 11>
The valid flag value is not limited to either “0” or “positive integer value”, or “0” or “negative integer value”. By taking “0”, “positive integer value”, and “negative integer value” as valid flag values, the order of input data can be changed.

  14A and 14B are diagrams for explaining the eleventh embodiment. In this example, the valid flag integrator 20A having the structure of the fourth embodiment shown in FIGS. 8A and 8B is used, and the valid flag leading value is set to “−1”. First, as the first set of inputs, input data D0 to D3 having valid flag values “1”, “2”, “−1”, and “2” are input. (FIG. 14A). When the effective flag integrated values are obtained from these, they become “0”, “2”, “1”, and “3”, respectively. Accordingly, the input data D0 to D3 whose valid flag value is not “0” are written in the memories M0, M2 and M3 of the storage device 10 respectively according to the valid flag integrated value. As a result, the data input in the order of the data D0, D1, D2, and D3 can be written to the memory by changing the order of D0, D2, D1, D3, and D2.

  Next, FIG. 14B illustrates the processing of the second set of input data D4 to D7. In this example, the valid flag values of the input data D4 to D7 are “3”, “0”, “−1”, and “−1”, respectively. When the effective flag integrated values are obtained from this, they become “6”, “6”, “5”, and “4”, respectively. Among these, the input data D4, D6, D7 whose valid flag value is not “0” are written in the memories M2, M1, M0, respectively, according to the valid flag integrated value. As a result, the three pieces of data excluding D5 from the input data D4 to D7 can be written in the memory by changing the order of D7, D6, and D4. As described above, according to the eleventh embodiment, only selected data can be exchanged in an arbitrary order and written to the memory of the storage device.

It is a schematic explanatory drawing of the data processing of this invention. It is a schematic explanatory drawing of the data processing of this invention. It is operation | movement explanatory drawing of the data processor of this invention. It is operation | movement explanatory drawing of the data processor of this invention. It is operation | movement explanatory drawing of the data processor of Example 1 of this invention. It is operation | movement explanatory drawing of the data processor of Example 1 of this invention. It is a circuit diagram which shows the structure of the selector control signal generation circuit of the data processor of Example 1 of this invention. It is a circuit diagram which shows the structure of the data selector of the data processor of Example 1 of this invention. It is a schematic explanatory drawing of the data processing of Example 2 of this invention. It is a schematic explanatory drawing of the data processing of Example 3 of this invention. It is operation | movement explanatory drawing of the data processor of Example 4 of this invention. It is operation | movement explanatory drawing of the data processor of Example 4 of this invention. It is a schematic explanatory drawing of the data processing of Example 5 of this invention. It is a schematic explanatory drawing of the data processing of Example 5 of this invention. It is a schematic explanatory drawing of the data processing of Example 6 of this invention. It is a schematic explanatory drawing of the data processing of Example 6 of this invention. It is a schematic explanatory drawing of the data processing of Example 6 of this invention. It is a schematic explanatory drawing of the data processing of Example 6 of this invention. It is a schematic explanatory drawing of the data processing of Example 6 of this invention. It is a schematic explanatory drawing of the data processing of Example 7 of this invention. It is operation | movement explanatory drawing of the data processor of Example 7 of this invention. It is operation | movement explanatory drawing of the data processor of Example 7 of this invention. It is operation | movement explanatory drawing of the data processor of Example 8 of this invention. It is operation | movement explanatory drawing of the data processor of Example 8 of this invention. It is operation | movement explanatory drawing of the data processor of Example 8 of this invention. It is operation | movement explanatory drawing of the data processor of Example 9 of this invention. It is operation | movement explanatory drawing of the data processor of Example 11 of this invention. It is operation | movement explanatory drawing of the data processor of Example 11 of this invention. It is operation | movement explanatory drawing of the conventional data processing apparatus.

Explanation of symbols

10, 10A, 10B, 10C, 10D: Storage device 20, 20A, 20B, 20C, 20D: Valid flag multiplier 30: Selector control signal generation circuit 40: Data selector 50: Divider 60: Multiplier 70: Shift operation vessel

Claims (6)

A plurality of data that is paired with a valid flag having “0” indicating invalidity, a positive integer value indicating validity, or a negative integer value indicating validity, and continuously input in an order relationship, is included in each cycle. In a data processing device for processing
Capture a predetermined number of the data along the order relationship for each cycle, and add the value of the valid flag of all the data whose order is earlier than the data, or add the value of the valid flag of the data to this An effective flag integrator that outputs the calculated value as the effective flag integrated value of the data,
Data composed of a plurality of memories having a plurality of addresses, and data designated as valid by the valid flag corresponds to a “remainder” when the valid flag integrated value corresponding to the data is divided by the number of the memories. A storage device to be written to an address corresponding to the “quotient” of the number memory;
A data processing apparatus comprising: The data processing apparatus according to claim 1,
The storage device writes data based on the “remainder” and the “quotient” obtained directly from the binary display of the effective flag integrated value when the number of data to be fetched by the predetermined number is represented by 2 to the power of n. A data processing apparatus characterized by being performed. The data processing apparatus according to claim 1,
In the storage device, when the number of data to be fetched by the predetermined number is not represented by 2 to the power of n, the “remainder” obtained by the divider that divides the effective flag integrated value by the number of the memories and the “ A data processing apparatus in which writing is performed based on a quotient. The data processing device according to claim 1, 2, or 3,
When two or more continuous data of the input data is a unitary data, a data processing apparatus is characterized in that a valid flag having the same value is assigned to each united data. The data processing device according to claim 1, 2, or 3,
A data processing apparatus comprising: multiplication means for multiplying the effective flag integrated value obtained by the effective flag integrator by an enlargement factor and outputting the result as a new effective flag integrated value. In a data processing apparatus that processes a plurality of data that is paired with a valid flag having “0” indicating invalidity or “1” indicating valid and that is sequentially input with an order relationship, for each cycle.
A predetermined number of the data is fetched in accordance with the order relation for each cycle, and the total value of the valid flag values of the previous data in the cycle from the data, or the valid flag value of the data An effective flag integrator that outputs a value obtained by adding as an effective flag integrated value of the data;
A memory composed of a plurality of memories having a plurality of addresses, in which data designated as valid by the valid flag is written to an address corresponding to the cycle of a specific memory indicated by the valid flag integrated value corresponding to the data Equipment,
A data processing apparatus comprising:

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