JP2541697B2 - Pipeline arithmetic unit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pipeline arithmetic unit, and more particularly to a pipeline arithmetic unit that repeatedly uses the same arithmetic unit to output an arithmetic result.

[Conventional technology]

Conventionally, in this type of pipeline arithmetic unit, as shown in FIG. 5, there is an arithmetic unit 53 that repeats the process for one data a desired number of times and then starts the process for the next data.

When the arithmetic unit 53 outputs the result 3 clocks after the data is input, and the result obtained by repeating the arithmetic unit 53 twice is output as the arithmetic result,
The selector 51 inputs the control signal from the control means 50 through the signal line 61, and selects either the input data input through the signal line 60 or the output from the signal line 63 of the calculator 53 to select the signal line 62. To the register 52 through.

The arithmetic unit 53 inputs the data set in the register 52 through the signal line 62 and outputs the arithmetic result after 3 clocks in the signal line.
Output through 63. In this case, the control means 50 controls the selector 51 to select the input data from the signal line 60 every time when the operation for one data is completed, that is, every 6 clocks (3 clocks × 2 times).

This operation will be described with reference to the time chart of FIG. 6. The flow of data will be described. First, A ₀ , B _0, ... Are input data, and each time the arithmetic unit 53 operates, the subscript increases by one. (For example, A ₀ → A ₁ → A ₂ ).

At the 0th clock, the selector 51 selects the data A ₀ from the signal line 60 by the control means 50, and the data A ₀ is set in the register 52.

Data set in register 52 at the first clock
A ₀ is calculated by the calculator 53 and the output data A ₁ is output after 3 clocks.

At the third clock, the selector 51 selects the output data A ₁ of the arithmetic unit 53 through the signal line 63 by the control means 50, and outputs the data.
A ₁ is set in register 52.

Data set in register 52 at the 4th clock
A ₁ is calculated by the calculator 53 and output data A ₂ is output after 3 clocks.

At the sixth clock, the selector 51 selects the data B ₀ from the signal line 60 by the control means 50, and the data B ₀ is set in the register 52.

 After that, the same processing is repeated.

Furthermore, as shown in FIG. 7, another conventional pipeline arithmetic device has an arithmetic circuit 500 including an arithmetic unit 201, 301, a register 302 for storing the result of the arithmetic unit 301, and a pipeline register 303 for the required number of times. It was structured vertically.

FIG. 4 shows a time chart when the arithmetic circuit 500 is repeated twice and the arithmetic result is output every two unit time.

First, at timing t ₀ , the data A1 and B1 are input as the first data, pass through the arithmetic units 201 and 301, and at timing t ₂ , the calculation result D1 is stored in the register 302 and the constant B1 is stored in the register 303. Then, passing through the arithmetic units 201 and 301 in the second arithmetic circuit 500, at timing t ₄ ,
The calculation result F1 is stored in the register 302 and the constant B1 is stored in the register 303, respectively, and becomes the output data F1, B1.

Second and subsequent input data A _{i + 1} , B _{i + 1} (i = 1,2,3 ...)
It is inputted in the same manner as the timing t _2i and the input data A1, B1, is outputted at a timing t _{2i + 2.}

[Problems to be Solved by the Invention]

The above-described conventional pipeline arithmetic unit has a drawback that the arithmetic interval becomes long because the arithmetic operation for one data ends and the arithmetic operation for the next data starts.

In addition, another conventional pipeline arithmetic unit has a drawback that when performing repetitive arithmetic, it has the same number of times of repeating the same arithmetic circuit, and the larger the number of times of repeating, the larger the amount of hardware.

[Means for solving the problem]

The pipeline arithmetic device of the present invention includes a first arithmetic means for outputting a result for every one unit time after n unit time (n is a natural number) after inputting data, and an output of the first arithmetic means. As an input, and a second arithmetic means for outputting a result every 1 unit time after m unit time (m is a natural number) from the input, and an input of the first arithmetic means to the second arithmetic means. It has an input data selection means for selecting either output or new input data from the outside.

Further, in another pipeline arithmetic device of the present invention, after a unit time (m is an integer of 1 or more) after a plurality of data including one or more constants are input, the operation result and the constant are calculated every 1 unit time. A first arithmetic means for outputting and an output of the first arithmetic means as an input, and after n unit time from the input (n is an integer of 1 or more), outputs an arithmetic result and a constant every 1 unit time. It has two calculation means and an input data selection means which allows the output of the second calculation means to be input-selectable as an input of the first calculation means.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.
Referring to FIG. 1, an embodiment of the present invention comprises a first calculation means 20 for outputting a result every unit time after n unit time (n is a natural number) from the input of data, and the first calculation means 20. The input of the output of the calculation result 20 of (1) and the input of the first calculation means 20 and the second calculation means 30 that outputs the result every 1 unit time (m is a natural number) after the input It has an input data selection means 10 for selecting either the output of the second calculation means 30 or new input data from the outside.

The input data selection means 10 selects a register 12 that repeatedly generates "0" and "1" for each clock, and selects the input data input from the signal line 100 if the value of the register 12 is "0". If it is "1", the output of the second computing means 30 is a signal line.
It has a selector 11 for inputting and selecting through the 130, and the selected data is output to the first calculating means 20 through the signal line 110. In the first arithmetic means 20, a register 21 for inputting the output of the input data selecting means 11 through the signal line 110 and setting the value thereof, and an arithmetic unit for executing the arithmetic operation by inputting the output of the register 21 through the signal line 111 twenty two
And a register 23 for setting the calculation result through the signal line 112 one clock later.

The register 23 outputs the set data to the second arithmetic means 30 through the signal line 120.

In the second arithmetic means 30, the arithmetic unit 31 which inputs the output of the register 23 of the first arithmetic means 20 through the signal line 120 and executes the arithmetic operation, and the arithmetic result is set through the signal line 121 one clock later, and this set Signaled signal 130
And a register 32 for outputting through.

Next, the data flow will be described with reference to the time chart of FIG.

In FIG. 2, A ₀ , B ₀ , C ₀ , ... Are input data,
The subscript is 1 each time it is calculated by the calculator 22 and the calculator 31.
It is assumed to increase in steps (for example, A ₀ , A ₁ , A ₂ ...).

At the 0th clock, the register 12 is set to "0". Since the register 12 is “0”, the selector 11 selects the input data A ₀ from the signal line 100, and the data A ₀ is the register 2
Set to 1.

At the first clock, the register 12 is set to "1". Since the register 12 of the selector 11 is "1", the second calculating means
It is controlled to select the output of 30, and the data from the signal line 100 is not input. The data A ₀ set in the register 21 is calculated by the calculator 22, and the output data
A ₁ is set in register 23.

At the second clock, the register 12 is set to "0". The selector 11 selects the input data B ₀ from the signal line 100 because the register 12 is “0”, and the data B ₀ is set in the register 21. Data A ₁ set in register 23 is the arithmetic unit
The output data A ₂ calculated by 31 is set in the register 32.

At the third clock, the register 12 is set to "1". Since the register 12 is “1”, the selector 11 selects the data A ₂ set in the register 32 from the signal line 130 and outputs the data A ₂
Is set in register 21. The data B ₀ set in the register 21 is calculated by the calculator 22 and registered in the register 23.
Is set to

At the fourth clock, the register 12 is set to "0". Since the register 12 of the selector 11 is “0”, the input data C ₀ is selected from the signal line 100, and the data C ₀ is set in the register 21. The data A ₂ set in register 21 is the arithmetic unit
The calculation is performed by 22 and its output data A ₃ is set in the register 23. Data B ₁ set in register 23
Is calculated by the calculator 31, and its output data B ₂ is set in the register 32.

5 register 12 clock cycle is set to "1", the selector 11 is data B ₂ that has been set in the register 32 from the register 12 is "1" because the signal line 130 is selected. The data C ₀ set in the register 21 is calculated by the calculator 22 and its output data C ₁ is set in the register 23.
The data A ₃ set in the register 23 is calculated by the calculator 31, and the output data A ₄ is set in the register 32.

 After that, the same processing is repeated.

This embodiment of the present invention is a pipeline arithmetic unit that repeatedly outputs the result by using the same arithmetic unit a plurality of times, and a timing at which data does not collide with each other before the operation for one data is completed. By controlling to input the next data in, the pipeline can process the operation at high speed.

FIG. 3 is a block diagram showing another embodiment of the present invention. In FIG. 3, another practical example of the present invention includes a first arithmetic circuit 200 for outputting a result every 1 unit time after n unit time (n is a natural number) after inputting data,
The input of the output of the arithmetic circuit 200 is the input of the second arithmetic circuit 300 that outputs the result every 1 unit time after m unit time (m is a natural number) and the input of the first arithmetic circuit 200.
It has an input data selection circuit 100 for selecting either the output of the second arithmetic circuit 300 or new input data from the outside.

The input data selection circuit 100 has a register 101 that holds a selection signal, selectors 102 and 103 that select input data by the output of the register 101, and registers 104 and 105 that store the data of the selectors 102 and 103, respectively. The circuit 200 includes an arithmetic unit 201 that receives the outputs of the registers 104 and 105 and a register 202 that stores the arithmetic result of the arithmetic unit 201.
And a register 203 for storing the output of the register 105. Further, the second arithmetic circuit 300 stores the arithmetic unit 301 which receives the outputs of the registers 202 and 203 and the arithmetic result of the arithmetic unit 301 as a selector. It has a register 302 for outputting to 102 and a register 303 for storing the data of the register 203 and outputting to the selector 103.

Regarding the operation of the other embodiment, as shown in FIG. 4, after the data is input, the data passes through the first and second arithmetic circuits twice, and the registers 104 and 105 store the input data every two unit time. It will be described including a time chart in the case.

First, at timing t ₀ , data A1 and B1 are input as the first data, and at timing t ₁ , register 10
The output of 1 (“1”) changes the input data A1 and B1 to the selector 10
2, 103 are stored in the registers 104 and 105, respectively, and then at timing t ₂ , the outputs of the registers 104 and 105 are calculated by the calculator 201, and the calculation result C1 is obtained in the register 203.
Then, at timing t ₃ , the registers 202, 20 are stored.
The output of 3 is calculated by the arithmetic unit 301 and is stored in the register 302 as the calculation result D1, and at timing t ₄ , the outputs of the registers 302 and 303 pass through the selectors 102 and 103 by the output of the register 101 (“0”), It is stored in 104,105.

Also the timing t _3, 2-th input data A2, B2 passes through the selectors 102 and 103 are input to the registers 104 and 105, at a timing t _4, the first input data A
As in the case of 1 and B1, the calculation result C2 of the calculator 201 is registered in register 2
The output B2 of the register 105 is stored in the register 203.

As shown in FIG. 4 below, the input data input every two unit time progresses through the register every one unit time and is output as output data every two unit time.

〔The invention's effect〕

As described above, according to the present invention, in a pipeline arithmetic device that outputs the result by repeatedly using the same arithmetic unit a plurality of times, before the arithmetic operation on one data is completed,
By controlling so that the next data is input at a timing such that the data do not collide with each other, there is an effect that the pipeline can process the operation at high speed.

Furthermore, the present invention has the effect of significantly reducing the amount of hardware by reducing the pipeline arithmetic unit used for repetitive arithmetic to the minimum unit arithmetic unit.

Furthermore, the present invention is more effective as the processing time (n + m) of the calculation means repeatedly used is longer.

[Brief description of drawings]

FIG. 1 is a block diagram showing a pipeline arithmetic unit according to one embodiment of the present invention, FIG. 2 is a diagram showing a time chart for explaining the operation of one embodiment of the present invention, and FIG. 4 is a block diagram showing another embodiment, FIG. 4 is a diagram showing a time chart of another embodiment of the present invention, FIG. 5 is a block diagram showing a conventional arithmetic circuit, and FIG. 6 is a conventional diagram shown in FIG. FIG. 7 is a diagram showing an example time chart, FIG. 7 is a block diagram showing another conventional arithmetic circuit, and FIG. 8 is a time chart of the conventional example shown in FIG. 10 …… Input data selection means, 11,51 …… Selector, 12,2
1,23,32,52 ... Register, 20 ... First computing means, 22,3
1,53 ... arithmetic unit, 30 ... second arithmetic means, 100 ... input data selection circuit, 101,104,105,202,203,302,303 ... register, 102,103 ... selector for selecting input data, 2
00 ... first arithmetic circuit, 201,301 ... arithmetic unit, 300 ... second arithmetic circuit, 500 ... conventional arithmetic circuit.

Claims (2)

(57) [Claims] 1. n unit time after the data is input (n
Is a natural number) and outputs the result every 1 unit time, and the output of the 1st operation unit is input, and every m unit time (m is a natural number) after the input, every 1 unit time Second calculation means for outputting a result to the first calculation means, and input data selection means for selecting either the output of the second calculation means or new input data from the outside as an input of the first calculation means. A pipeline arithmetic unit having: and the first arithmetic means is repeatedly used l times (l is a natural number of 2 or more), and the output of the first arithmetic means or the second arithmetic means is used as an arithmetic result. Output, t unit time (t ≠ j (n +
m), kt ≠ n + m, l ≦ t <(l-1): t is a natural number of 2 or more, and j, k is an arbitrary natural number), the pipeline is characterized by enabling data input once. Arithmetic unit. 2. A first operation for outputting an operation result and a constant every 1 unit time after m unit time (m is an integer of 1 or more) after inputting a plurality of data including one or more constants. Means and second output means for receiving an output of the first operation means and outputting an operation result and a constant every unit time after n unit time (n is an integer of 1 or more) after the input A pipeline arithmetic unit having an input data selecting means for allowing the output of the second arithmetic means to be input-selectable as an input of the first arithmetic means, wherein the first and second arithmetic means are Repeatedly used 1 times (1 is an integer of 2 or more),
The output of the second calculating means is output as a calculation result together with a constant, and t unit time (t ≠ j (m + n), kt ≠ m + n,
l <t <(l−1) · (m + n): t is an integer, j and k are arbitrary natural numbers, and the next input data can be selected once.