JP2771628B2 - Timer counter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a timer counter provided in a semiconductor integrated circuit such as a one-chip microcomputer, and provides a timer counter capable of reducing the circuit size and improving the resolution. A first counter unit having a plurality of counters for counting carry input signals, a first holding circuit for holding carry output signals from each of the counters, and a first holding circuit for holding the carry output signals. A selector for selecting one of the carry outputs and outputting a select carry output signal; a first carry unit for carrying the select carry output signal as an input; and a first carry unit. A second counter unit having a plurality of count data registers for counting in common; A timing generator for generating a timing signal for controlling the operation timing of the holding circuit, wherein one of the carry output signals held in the first holding circuit is selected based on the timing signal, and the value thereof is set to a second value. Is configured to count by adding or subtracting to or from the data stored in the counter unit.

[Industrial applications]

The present invention relates to a timer counter provided in a semiconductor integrated circuit such as a one-chip microcomputer.

In recent years, semiconductor integrated circuits are required to have multifunction and high resolution. A timer counter, which is a functional module built in a semiconductor integrated circuit, is also required to have high resolution. However, the high resolution of the timer counter and the high integration required of the semiconductor integrated circuit are in conflict with each other, and there is still a problem to be solved in how to obtain high resolution while reducing the circuit scale. Have been.

[Conventional technology]

There are roughly two types of timer counters built in semiconductor integrated circuits. One is a system in which each of a plurality of timer counters has one carry circuit individually, and the other is that a plurality of timer counters share one carry circuit in a time-division manner. It is a method that is.

[Problems to be solved by the invention]

The system in which each of the timer counters has a carry circuit is excellent in terms of resolution, but the circuit scale becomes very large correspondingly, and there is a problem in terms of high integration. On the other hand, when one carry circuit is shared by a plurality of (n) timer counters in a time-division manner, the circuit scale is reduced by that amount, but the resolution is reduced to 1 / n. is there.

Therefore, an object of the present invention is to provide a timer counter capable of reducing the circuit scale and improving the resolution.

[Means for solving the problem]

In order to solve the above problems, the invention according to claim 1 is:
As shown in FIG. 1, a first counter unit 2 for counting the carry input signal CI ₁ ~CI _n has a plurality of counters 2 _-1 to 2 _-n, the counters 2 _-1 to 2 _- the first and the holding circuit 3 _-1, the first holding circuit 3 _-1 carry output signal is held by the CO ₁ to CO for holding a carry output signal CO ₁ to CO _n from _n
by selecting one of the _n selectors _3-2 to output a select carry output signal ECO _1, wherein the first carry portion 4 ₁ and the performing carry a select carry output signal ECO ₁ as an input first share the carry unit _4-1 and the second counter portion 4 having a plurality of count data register Reg.1~Reg.n counting, the second counter unit 4 and the first holding circuit 3 timing signal T ₁₁ for controlling the operation timing of the _-1, T _12, the timing generating unit 1 for generating ...
With the door, the timing signal T _11, T _12, ... carry output signals held by the first holding circuit 3 _-1 based on C
Any one of O _{1 to} CO _n is selected, and the value is added to or subtracted from the data stored in the second counter unit 4 and counted.

According to a second aspect of the invention, as shown in FIG. 2, the first holding circuit 3 carry output signal is held by the _-1 CO ₁ to CO
other selector _5-1 for selecting and outputting one of _n, the first by a select carry output signal ECO ₂ selected 2
The carry of the count value from the counter unit 4 of the second
The carry portion _4-3 is included.

According to a third aspect of the invention, as shown in FIG. 3, the first holding circuit 3 carry output signal is held by the _-1 CO ₁ to CO
other selector _5-1 for selecting and outputting one of _n, holds a select carry output signal ECO ₂ selected, corresponding to the count data read-write signal R / W ₁ ~R / W _n Select Second holding circuit that outputs carry output signal ECO ₂
Configure to include 5 _-2 .

Fourth aspect of the present invention, as shown in FIG. 4, the first holding circuit 3 carry output signal is held by the _-1 CO ₁ to CO
other selector _5-1 for selecting and outputting one of _n, the first by a select carry output signal ECO ₂ selected 2
Second carry portion for performing carry the count value from the counter 4 4 _-3, selected select the carry output signal E
Holds CO ₂ and counts data read / write signal R / W ₁
Configured to include a second holding circuit _5-2 for outputting a select carry output signal ECO ₂ corresponding to to R / W _n.

Invention of claim 5, wherein, as shown in FIG. 5, the counter 2 _-1 and a carry output signal CO ₁ to CO _n from to 2 _n, the carry output signal C ₁ -C from the second counter portion 4 _It is configured to include an AND circuit 23 that calculates a logical product with _n .

[Action]

According to the first aspect of the present invention, the carry input signal CI ₁
If ～CI _n is "1", the counter 2 _-1 to 2 _-n lock signal K
_A, countdown in synchronization with the K _B (or counts up) performs, each outputting a carry output signal CO ₁ to CO _n. Each carry output signal CO ₁ to CO _n are respectively latched in the first holding circuit 3 _-1. Any of the latched carry output signals CO _{1 to} CO _n is used as a timing signal T ₁₁ , T ₁₂ from timing generator 1.
... synchronization is select by the selector 3 _-2, the select carry output signal ECO ₁ is input to the first carry portion _4-1. Second counter unit 4 is composed of n counters which share a first carry portion _4-1. First carry
4 one of the count data _{D Reg.1} ~D Reg.n of the count data register Reg.1~Reg.n and corresponding select carry output signal ECO ₁ to _-1 is temporarily loaded, first carry portion 4 _-1 is the load value and select carry output signal ECO
₁ is added, and the operation value is set again in the original count data registers Reg.1 to Reg.n. Thus, the first
Count data D _Reg.1 carry output signal CO ₁ to CO _n select the carry output signal ECO ₁ of the counter unit 2 counter 2 from _-1 to 2 _-n and a second counter unit ₄ ~D Reg.n Are added, and the count value is sent to the data bus BUS.

According to the second aspect of the present invention, either the first holding circuit 3 carry output signal CO ₁ latched in the _-1 to CO _n is selected by the selector 5 _-1, its selection carry output signal ECO ₂ It is sent to the second carry section _4-3 . The second carry portion 4 _-3 entered either count data _{D Reg.1} ~D Reg.n from the second counter unit 4, the count data _{D Reg.1} ~D Reg.n Any of the corresponding data and select carry output signal ECO ₂ are added, carry operation is performed, and the result is transmitted to data bus BUS. With this configuration, the timer counter operates as a single timer counter, and performs a counting operation without depending on an instruction from the CPU.

According to the third aspect of the present invention, either the first holding circuit 3 carry output signal CO ₁ latched in the _-1 to CO _n is selected by the selector _5-1, the select carry output signal ECO ₂ is The signal is latched by the second holding circuit _5-2 . Latched value is read by the read-write signal R / W ₁ ~R / W _n from CPU, sent to the data bus BUS. By doing so, this timer counter operates as a timer counter that performs a count operation in accordance with an instruction from the CPU.

According to the fourth aspect of the present invention, the second holding circuit _5-2 includes C
Latched value by the read-write signal R / W ₁ ~R / W _n from PU can dispatch the data bus BUS, and sends the count value to the data bus BUS on the second carry portion 4 _-3 A highly versatile timer counter that can be used arbitrarily as a single timer counter can be configured.

According to the invention of claim 5 wherein each carry output signal CO ₁ to CO _n output from the counter 2 _-1 to 2 _-n are inputted to the AND circuit 23, and output from the second counter portion 4 Carry output signals C _{1 to} C _n are input to the AND circuit 23. AND circuit 23 ANDs the carry output signal C ₁ -C _n corresponding to respective carry output signal CO ₁ to CO _n, the carry signal of the operation period of the counter 2 _-1 to 2 _-n externally outputs . In this case, AND
The output of the circuit 23 is synchronized with a clock signal that regulates the operation cycle of the counters _2-1 to _2-2 , and a highly accurate carry signal can be externally output.

〔Example〕

 Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 6 shows an embodiment of the present invention. This embodiment is an embodiment corresponding to the invention described in claim 4 (see FIG. 4). This detailed circuit is shown in FIG.

The basic configuration of the timer counter according to the present invention includes a first counter section 2, a second counter section 4, and a first counter section 2 and a second counter section 4 interposed between the first counter section 2 and the second counter section 4. And a selector _3-2. The first holding circuit _3-1 and the selector _3-2 correspond to the configuration of FIG. 1 (FIG. 1).

The timer counter according to the present invention can be configured as hardware that operates the timer counter as a single counter. The configuration in that case is based on the above basic configuration (first
2), a selector 5 _-1 and a second carry section _4-3 are combined, and corresponds to the configuration of FIG. 2 (FIG. 2). Such a configuration is effective in reducing the load on the software of the CPU when incorporated in a one-chip microcomputer.

Further, the timer counter according to the present invention can be configured as a counter that operates according to software. In that case, in addition to the above basic configuration (FIG. 1), the selector 5 _-1 ,
This is a combination of the second holding circuit _5-2 , and corresponds to the configuration described in claim 3 (FIG. 3). Such a configuration,
In particular, this timer counter is built in a one-chip microcomputer, and is suitable for the case where the counter is operated by instruction processing from the CPU, which is effective in simplifying hardware.

Also, as in the present embodiment (FIG. 6), when the basic configuration (FIG. 1) is combined with the embodiment of FIG. 2 and FIG. And can be used arbitrarily as a counter according to software processing by an external instruction or as a counter composed of a single piece of hardware.

Further, the timer counter according to the present invention can be configured to externally output a carry signal without reducing accuracy. In that case, the configuration is AND
This is a combination of the circuit 23, and corresponds to the configuration described in claim 5 (FIG. 5).

In Figure 6, the first counter unit 2 inputs the carry input signal CI ₁ ~CI _n, consisting of a clock signal K _A, the counter 2 _-1 to 2 _-n performing a counting operation in synchronization with the K _B. Each counter 2 _-1 to 2 _-n are read / write is performed by a read-write signal _{R / W 1 ~R / W n} . Each counter 2 _{-1 to} 2- _n is
For example, the lower two bits including the LSB are counted, and the carry output signal CO is counted down (counted up).
And outputs a _{1 ~CO n.} The above first counter portion 2 of the detail shown in Figure 7, typically eighth counter 2 _-1 of the
Shown in the figure. In FIG. 8, the counter _2-1 uses two inverter latches 7, and is constructed by combining various logic gates.

First holding circuit 3 _-1 is individually latch the carry output signal CO ₁ to CO _n from the counter 2 _-1 to 2 _-n. FIG. 9 shows a specific example of the first holding circuit _3-1 . In Figure 9, a first holding circuit 3 _-1 Each carry output signal CO ₁ to CO _n
Corresponding to the number of AND latches 8, inverter latches 9, and various logic gates.
The value CO ₁ '~CO _{n' -1)} to the selector _3-2. A specific example of the AND latch 8 is shown in FIG.

The selector 3 _-2, the value of the first hold circuit 3 carry output signal CO ₁ latched in the _-1 to CO _n to select the timing of the timing signal T ₁₂ through T ₄₂ from the timing generator unit 1,
The signal is output to the second counter section 4 as the select carry output signal ECO ₁ .

The second counter section 4 includes a plurality of registers 14 as shown in FIG. 11, and the configuration of one register 14 is shown in FIG. Register 14 and the first carry portion _4-1 composed of logic gates, and a count data register Reg.1~Reg.n consisting inverter latch, the address input signal AD ₁ to A
D ₄ and the count data register by a read signal RDX Reg.1
... Reg.n count data D _{Reg.1 to} D _Reg.n are output to the data bus BUS.

The selector _5-1, as shown in FIG. 9, is provided with a selector _3-2, a timing signal T ₁₂ through T _42, the value CO of the first holding circuit of the output of the inverter latch 9 (3 _{-1) 1} '~
The NAND outputs of CO _n ′ and the address input signals AD _{1 to} AD ₄ are output as the select carry output signal ECO ₂ via the final stage inverter latch 9.

A specific example of the timing generator 1 is shown in FIG. Timing generation unit 1 clock signal K _A, in synchronism with the K _B and outputs a timing signal T ₁₁ through T _42. The details of the latch 20 are shown in FIG.

 Next, the operation will be described.

First, the basic operation will be described with reference to FIG.
The clock signals K _A and K _{B correspond} to the respective counters _2-1 to 2- _n and the selector 3
_{-2 is given to} the timing generator 1 and the second counter 4 (FIG. 7). Clock signals K _A and K _B are 2
It is a phase clock signal, and oscillates in opposite phases with a pulse width whose timing does not overlap with each other. The timing generator 1 synchronizes with the clock signals K _A and K _B to generate the timing signals T _{11 to} T ₄₂
The generated and transmitted to the first of each count data registers Reg.1~Reg.n holding circuit 3 _-1 and the second counter portion 4 (Figure 7). On the other hand, the carry input signal CI ₁ ~CI _n each counter
2 _{-1 to} 2 _-n and carry input signals CI _{1 to} CI _n are set to “H”
At the level, the counters _2-1 to 2- _n perform counting operation,
Stops at the "L" level and holds the count data at that time. Carry output signals CO _{1 to} CO _n are supplied to first holding circuit 3
_{The value} is latched at _-1 and then one of the values is selected by the selector _3-2 (FIG. 9). The select carry output signal ECO ₁ is sent to the second counter unit 4. Select carry output signal ECO ₁ includes values CO ₁ ′ to CO _n ′ of first holding circuit (3 ₋₁ ) in time series. Select the carry output signal ECO ₁ is input to the first carry portion _4-1 of the second counter portion 4 (FIG. 11). At this time,
The first carry section 4 counts _-1 data D _Reg.1 ~D
_Reg.n is loaded as the load value LD (first
2). The first carry part _4-1 is a select carry output signal.
ECO ₁ is added to _one of the count data D _{Reg.1 to} D _Reg.n. Carry calculation is performed by this addition,
The added value is again stored in the corresponding count data register Reg.
eg.n. Latched data D
Read and write signals, if necessary _{R / W 1 ~R / W n} (RDX)
And sent to the data bus BUS (FIG. 12).

In this way, by coupling the first counter unit 2 and the second counter unit 4 via the first holding circuit _3-1 and the selector _3-2 , as shown in FIG. If the number of count bits of the counter unit 2 is, for example, 2 bits and the number of count bits of the second counter unit 4 is 14 bits, the obtained data D is obtained with a total of 16 bits. Therefore, the resolution can be improved. The operation of this timer counter is based on whether carry input signals CI _{1 to} CI _n are “H” level or “L”.
Since it is determined by the level, the count operation can be arbitrarily controlled according to an external event. Therefore, it can be controlled by software under the control of the CPU or the like, and an operation depending on the host device when the present timer counter is used as a single timer counter can be performed.

Next, the above operation will be described with reference to FIG. Now, the timing of the timing signals T _12, the carry input signal CI ₁ for counter 2 _-1 is "H" level, the count value CNT ₁ of the counter 2 _-1 and was "11". Then, the carry output signal CO ₁ is changed to "L" level from "H" level, the carry output signal CO ₁ is first
AND latch 8 in the holding circuit 3 _-1, since it is latched by inverter latch 9 (Fig. 9), the value CO ₁ of the first holding circuit (3 _-1) 'is maintained at the "H" level. This first
The value CO ₁ 'of the holding circuit (3 _-1 ) is the select carry output signal
Is input to the first carry portion _4-1 of the second counter portion 4 as ECO _1. The time count data D _Reg.1 the count data register R _Eg.1 are latched, the the data value is assumed to be a "A", the count in the first carry portion 4 _-1 data D _Reg.1 “A” is taken in as the load value LD, and “A” is added to the value CO ₁ ′ of the first holding circuit (3 ₋₁ ).
As a result, the added value becomes “A ₁ ”, and this “A ₁ ” is latched again in the count data register R _eg.1 . In the same manner, repeating the same thing for each timing of each timing signal _{T 12, "A 2",} "A 3", performing the carry and so .... This operation is the same for the counter _2-2 .
In Figure 15, focusing on the timing signal T _22, the first holding circuit (3 _-1) values of CO ₂ 'is output at "L" level,
Select carry output signal ECO ₁ is “O” and the first carry
Sent to 4 _-1 . When the count data D _Reg.2 was "B" at this time, the addition result of the first carry portion 4 _-1 never change remains "B", again the count data register R
will be latched to _eg.2 . In this way, a carry is carried out by adding the value of the select of the carry output signal ECO ₁ value and the load value LD is.

Next, the operation of FIG. 2 will be described. When reads the count value of the timer counter at a certain bus cycle, select the carry output signal ECO ₂ at that time is sent to the second carry portion 4 _-3 via the selector _25-1. Performs subtraction of "11" to the count value from the second counter portion 4 when the second carry portion 4 _-3 The select carry output signal ECO ₂ is at "H" level, the data bus the value Send to BUS.

Next, the operation of FIG. 3 will be described. In some bus cycle, read-write signal R / W1 ₁ ~R / W _n by incorporation a select carry output signal ECO ₂ at that time in the second holding circuit _5-2 via the selector _5-1, the second The holding circuit _5-2 performs subtraction (or addition), and stores the value on the data bus BUS.
Send up.

Next, the operation of FIG. 5 will be described. First counter unit 2
And carry output signals CO ₁ -CO _n and carry output signal C ₁ with the count operation by second counter section 4.
CC _n are input to the AND circuit 23, and when the AND condition of both is satisfied, the carry information is externally output from the AND circuit 23. The carry information at this time is accurately synchronized with the clock signals K _A and K _B , and a correct value is obtained.

〔The invention's effect〕

As described above, according to the present invention, when a large number of high-resolution timer counters are provided, the circuit scale can be reduced.

[Brief description of the drawings]

1 is a diagram illustrating the principle of the first invention, FIG. 2 is a diagram illustrating the principle of the second invention, FIG. 3 is a diagram illustrating the principle of the third invention, and FIG. 4 is a diagram illustrating the principle of the fourth invention. FIG. 5, FIG. 5 is an explanatory view of the principle of the fifth invention, FIG. 6 is a block diagram showing an embodiment of the fourth invention, FIG. 7 is a detailed block diagram of FIG. 6, and FIG. FIG. 9, FIG. 9 is a circuit diagram of the first holding circuit and the selector, FIG. 10 is a circuit diagram of the latch, FIG. 11 is a circuit diagram of the second counter unit, and FIG. 12 is a register of the second counter unit FIG. 13 is a circuit diagram of a timing generator, FIG. 14 is a circuit diagram of a latch, FIG. 15 is an operation time chart, and FIG. 16 is an operation explanatory diagram. 1 ...... timing generator 2 ...... first counter portion 2 _-1 to 2 _-n ...... counter 3 _-1 ...... first holding circuit 3 _-2 ...... selector 4 ...... second counter unit 4 _{- 1} … First carry section 4 _-3 … Second carry section 4 _-4 … Data latch bus driver _5-1 … Selector 5 _-2 … Second holding circuit 7… Inverter Latch 8 AND latch 9 Inverter latch 10 NOR circuit 11 Inverter 12 NAND circuit 13 Inverter 14 Register 15 Inverter 16 Register (Reg.1 to Reg.n) 18 ...... the AND circuit 19 ...... NAND circuit 20 ...... latch 21 ...... inverter 22 ...... NOR circuit 23 ...... the AND circuit AD ₁ to AD _n ...... address input signal bUS ...... data bus CNT ₁ to CNT _n ...... count value C ₁ ~C _n ...... carry output signal CI ₁ ~CI _n ...... carry input signal CO ₁ ~CO _n ...... carry output signal CO ₁ '~CO _n' ... The value _{D Reg.1} ~D Reg.n ...... count data D ...... data ECO _1, ECO ₂ ...... select the carry output signal K _A of the first holding circuit (3 _-1), K _B ...... clock signal LD ... … Load values R / W _{1 to} R / W _n … Read / write signals RDX… Read signals Reg.1 to Reg.n… Count data registers T ₁₁ , T ₁₂ , T ₂₁ , T ₂₂ , T ₃₁ , _{T 32, T 41, T 42} ...... timing signal

Continuation of the front page (56) References JP-A-55-13502 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G06F 1/14 H03K 17/28

Claims (5)

(57) [Claims] 1. A first counter for counting the carry input signal (CI ₁ ~CI _n) has a plurality of counters (2 _-1 to 2 _-n) and (2), wherein each counter (2 _{- 21} to carry output signals from _-n) and (CO ₁ to CO _n) first holding circuit for holding (3 _-1), retained carry output to the first holding circuit (3 _-1) signal (CO ₁ to CO _n) select the carry output signal by selecting one of a selector _(3-2) for outputting (ECO _1), the select carry output signal (ECO ₁₎
The first carry section for performing a carry as an input _(4-1) and the first carry portion _(4-1) a plurality of count data register that counts share (Reg.1～Reg.N ), And timing signals (T ₁₁ , T ₁₂ ,...) For controlling the operation timing of the second counter unit (4) and the first holding circuit (3 _-1 ). , And a carry output signal (C) held in the first holding circuit (3 _-1 ) based on the timing signals (T ₁₁ , T ₁₂ ,...).
O _{1 to} CO _n ), wherein the timer counter is configured to select and count the value by adding or subtracting the value to or from the data stored in the second counter section (4). 2. The semiconductor integrated circuit according to claim 1, wherein
Another selector (5 _-1 ) for selecting and outputting any of the carry output signals (CO _{1 to} CO _n ) held in the first holding circuit (3 _-1 ), and a selected select carry output signal timer counter, characterized in that it comprises a second carry portion for performing a carry count value (4 _-3) from the second counter portion (4) by (ECO _2). 3. The semiconductor integrated circuit according to claim 1, wherein
Another selector (5 _-1 ) for selecting and outputting any of the carry output signals (CO _{1 to} CO _n ) held in the first holding circuit (3 _-1 ), and a selected select carry output signal holds (ECO _2), the count data read-write signal _{(R / W 1 ~R / W} n) select the carry output signal corresponding to the second holding circuit for outputting a (ECO ₂₎ (5 _-2) A timer counter comprising: 4. The semiconductor integrated circuit according to claim 1, wherein one of the carry output signals (CO _{1 to} CO _n ) held in said first holding circuit (3 _-1 ) is selected and output. A second carry section (4 _-3 ) for carrying the count value from the second counter section (4) by another selector (5 _-1 ) and the selected select carry output signal (ECO ₂ ). ) And a selected carry output signal (ECO ₂ ) that holds the selected select carry output signal (ECO ₂ ) and outputs a select carry output signal (ECO ₂ ) corresponding to the count data read / write signal (R / W _{1 to} R / W _n ). 2
A timer counter including a holding circuit ( _5-2 ). 5. The semiconductor integrated circuit according to claim 1, wherein the carry output signals (CO _{1 to} CO _n ) from the counters (2 _-1 to 2 _n ) and a second counter section (CO). AN that performs logical AND with carry output signals (C _{1 to} C _n ) from 4)
A timer counter comprising a D circuit (23).