JP2806849B2 - Memory address controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a memory address control device for controlling an address of a semiconductor memory device (memory), and more particularly to a memory address control device for controlling a row address and a column address.

[0002]

2. Description of the Related Art Conventionally, such a memory address control device accesses a memory by using a row address counter or a column address counter for designating an address for the memory and switching the address with an address control signal.

FIG. 6 is a block diagram of a memory address control device for explaining an example of the prior art. As shown in FIG. 6, the memory address control device includes a row address counter 1 that counts a first clock to generate a row address, and a column address counter 2a that counts a second clock to generate a column address. A switching circuit 5a for switching the outputs of these counters 1 and 2a by a row / column switching signal; a row address strobe (RAS inversion) signal; a column address strobe (CAS inversion) signal; and a write enable (WE). Inverted)
And a memory 3 accessed by a signal and the output of the switching circuit 5. The row / column switching signal, the RAS inverted signal, the CAS inverted signal, and the WE inverted signal are sent from a CPU (not shown) at different timings.

In the operation of the address control device, read / write control of the memory 3 is performed by a WE inversion signal. That is, the WE inversion signal is “low (L)”.
Indicates a write operation, and “high (H)” indicates a read operation. Note that, in these read / write operations, the operations relating to the address control are the same, so that the following description will be made without distinguishing between read / write.

First, the address setting method for reading / writing data from / to the memory 3 is as follows. A switching circuit 5a outputs a signal of the row address counter 1 to the memory 3, and then switches the switching circuit 5a to switch the column. The signal of the address counter 2a is output to the memory 3.

In this way, a certain address is selected and data can be read / written. However, if the subsequent access is the same row address, the row address is not set and only the column address is set. Thus, reading / writing can be performed subsequently. This operation is an operation mode called page mode,
Since there is no need to set a row address again, there is an advantage that reading / writing can be performed on a number of addresses in a short time.
In particular, this is an indispensable operation mode for a system that requires high-speed operation such as digital signal processing.

FIG. 7 is a circuit diagram of the column address counter in FIG. As shown in FIG. 7, this column address counter has a 4-bit configuration of 16 bits as an example.
Hex counter. The circuit configuration is such that the second clock C
Flip-flops F1 to F for inputting K to a clock terminal
4 and an inverter I1 for combining outputs of these flip-flops F1 to F3, NAND gates NA1 and N1.
A2 and inverters I2 to I4 for inverting these outputs.
And these inverter outputs and inverters I1,
AND gates A1 to A6 and NOR gates NR1 to NR1 which take combinational logic such as outputs of NAND gates NA1 and NA2 and positive and inverted outputs of flip-flops F2 to F4.
NR3, and outputs data Q0 to Q3 as 4-bit column addresses from the flip-flops F1 to F4. Note that the signal RN is a flip-flop F
Reset signal for 1 to F4, "Low (L)"
All the Q outputs of F1 to F4 become (L) at the input.

In the circuit operation, the second clock CK is input to the clock terminals of the flip-flops F1 to F4, so that the signal of the data terminal (D) of each flip-flop is
The signal is output to the output terminal (Q) simultaneously with the rise of the clock, and an inverted signal of the Q signal is output to the inverted output terminal (QB). Further, in a state other than the time when the clock rises, the Q output and the Q inverted output signal retain the previous state.

In such a column address counter, flip-flops F1 to F
4 are all reset to 0, that is, set to "0" in decimal, and then the flip-flop F1 changes to "1" at the rising edge of the clock CK, that is, F1, F2, F3.
F4 becomes (1, 0, 0, 0) and "1" in decimal
become. Thereafter, the clocks are counted sequentially, and F1 and F
2, F3, and F4 count up to (1, 1, 1, 1), that is, up to "15" in decimal, and "
Return to 0 ″.

FIG. 8 is a timing chart of various signals in FIG. As shown in FIG. 8, first, the value of the row address counter is counted at the rising edge of the RAS inverted signal, and the value of the column address counter is counted at the rising edge of the CAS inverted signal. That is, the first clock has R
It is common to use the CAS inverted signal for the AS inverted signal and the second clock. Next, the switching circuit 5a is switched to the row address counter 1 by the row / column switching signal,
When the RAS inverted signal falls, the row address is set in the memory 3. Then, the switching circuit 5a is switched to the column address counter 2a side, and the CAS inverted signal falls, whereby the column address is set in the memory 3. Data is read / written from / to the memory address set by the row address and the column address. Next, the column address counter 2a
Counts the clock CK of
At the falling edge of the CAS inversion signal, a column address is set in the memory 3. Thereafter, this operation is repeated, and 1
Reading / writing of data at one row address is completed.

Next, the count value of the row address counter 1 is advanced by one by the first clock, and the same operation is repeated.

As described above, the row address and the column address are switched and output to the memory 3, and this address signal changes from "0" to "1" or from "1" to "1".
When the bit changes to 0 ", the operating current flows instantaneously, and the more bits that change, the more the operating current increases. The current flowing at this moment causes the power supply system to fluctuate and propagate as noise. Some of these noises propagate through power supplies and GND lines, while others propagate directly by radiation.If this noise propagates to analog circuits operating at very small voltages and currents, the analog circuits may malfunction. For example, if noise propagates to the analog input signal of the AD converter, the analog input signal including the noise is converted into a digital signal. Or enter.

[0013]

The above-described conventional memory address control device is adapted to a high-speed system such as digital signal processing by using a page mode. However, since the output signal to the memory is a digital signal, there is a drawback that noise generated when the address signal changes adversely affects the analog signal processing system.

For example, in an image signal processing system or the like, there is an obstacle that noise such as vertical lines and white dots appears on the screen, resulting in an unsightly image.

In order to reduce such troubles, a column address is changed to a binary code (F4, F3, F3, F3, F4, F3,
Gray code (F4, F3, F) instead of F2, F1
2, F1).

When this gray code is used, only one bit changes, so that the occurrence of noise due to a change in column address is reduced. For example, "7" in decimal
Changes to “8”, in a normal binary code, all bits change [(0, 1, 1, 1) →
(1, 0, 0, 0)], whereas in the Gray code, only the F4 bit changes [(0, 1, 0, 0) → (1,
1,0,0)].

However, also in this case, it is not possible to eliminate noise generated when switching between the row address and the column address.

An object of the present invention is to provide a memory address control device which reduces noise generated when switching between a row address and a column address and prevents malfunction of an analog signal processing system which is easily affected by noise. .

[0019]

A memory address control device according to the present invention counts a first clock and outputs a row address, and loads a counter value of the row address counter to generate a second address. It comprises a column address counter that starts counting from the same counter value when counting clocks, and a memory that is accessed using the counter value of the column address counter.

The column address counter in the memory address control device is provided with an initial value setting gate for inputting an initial value setting signal and row address data and setting an address to the memory.

Further, the row address counter and the column address counter in the memory address control device of the present invention are provided in a write address control section and a read address control section, respectively, and are switched by a write / read switching signal to access the memory. It is configured to

[0022]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a memory address control device for explaining an embodiment of the present invention. As shown in FIG. 1, in the present embodiment, in a system including a memory, the row address counter 1 and the column address counter 2 are set to the same initial value to reduce noise generated at the time of address switching. By eliminating the / column switching, the occurrence of noise is eliminated. The device configuration includes a row address counter 1 that counts a first clock to generate a row address, loads a row address from the row address counter 1, and sets an initial value setting signal LOAD.
And a column address counter 2 that counts the second clock from the same counter value as the row address to create a column address, a RAS inversion signal, a CAS inversion signal, a WE inversion signal, and the column address counter 2
And the memory 3 accessed using the output of the memory 3 as an address input. The RAS inverted signal, the CAS inverted signal, and the WE inverted signal are sent from a CPU (not shown) at different timings as in the above-described conventional example.

FIG. 2 is a circuit diagram of the column address counter in FIG. As shown in FIG. 2, for example, this column address counter also has a 4-bit configuration of 16 bits.
Take a hex counter as an example. The circuit configuration includes an inverter INV that generates an inverted signal of the initial value setting signal LOAD.
1, an initial value setting signal LOAD, an initial value setting unit 4 for inputting a row address or the like as a data input to set an initial value as a column address, and an output of the initial value setting unit 4 to a data terminal D. , A flip-flop F1 that inputs a second clock to a clock terminal CK, a reset signal RN to a reset terminal RN, outputs a positive-phase output to a Q terminal, and outputs a negative-phase output to a QB terminal as data outputs (Q0 to Q3). To F4 and an inverter I1 and a NAND gate N for combining the outputs of these flip-flops F1 to F3.
A1, NA2 and an inverter I for inverting these outputs
2 to I4 and the inverter output and inverter I
1, AND gates A1 to A6 and NOR gates NR1 to NR3 which take combinational logic such as outputs of NAND gates NA1 and NA2 and outputs of flip-flops F2 to F4.
And Portions other than the initial value setting section 4 are the same as those in the circuit of FIG. 7 described above.

The initial value setting unit 4 in the present embodiment
AND gates A7 and A8 which take the logic of the positive and negative phase outputs of the initial value setting signal LOAD by the inverter INV1, the row address data D0 from the row address counter 1 and the QB output of the flip-flop F1, and the inverter I
The positive and negative phase outputs of the initial value setting signal LOAD by NV1 and the row address data D from the row address counter 1
AND gates A9 and A10 which take the logic of the output of NOR gate NR1 and AND gates A11-A1
4 and these AND gates A7, A8; A9, A10;
A11, A12; are formed by OR gates 0R1 to OR4 to which respective outputs of A13, A14 are input, and output data Q0 to Q3 as 4-bit column addresses from flip-flops F1 to F4. Note that the reset signal RN is input to the flip-flops F1 to F4 as “low (L)”, and all Q outputs of F1 to F4 become (L).

The "column (L)" input of the initial value setting signal LOAD causes the column address counter 2 to perform a normal counting operation. That is, the operation is the same as that of the conventional counter of FIG. Data input D0 at this time
~ D3 has no effect on the count.

When the LOAD signal is set to a "high (H)" input, the data inputs D0 to D3 are loaded into the flip-flops F1 to F4 in synchronization with the clock, and are initialized to the values of D0 to D3. .

Thereafter, when the LOAD signal is returned to "low (L)" and a clock is input as in the conventional case, counting starts from the initial counter value.

In short, the initial value setting unit 4 including the AND gates A7 to A14, the OR gates OR1 to OR4, and the inverter INV1 performs the initial setting for setting the data D0 to D3 as the row address as the initial value of the column address counter 2. Configures a value setting gate.

FIG. 3 is a timing chart of various signals in FIG. As shown in FIG. 3, this corresponds to the LOA described above.
This is an example in which a RAS inverted signal is used as the D signal and a CAS inverted signal is used as the second clock of the column address counter 2. That is, the RAS inversion signal is input as a LOAD signal, and when the RAS inversion signal is “high (H)”, the data input of the column address counter 2 is the row address of the row address counter 1 and the second
At the same time as the rise of the CAS inverted signal, which is the clock, the same counter value as that of the row address is initialized in the column address counter 2.

Next, the row address initialized in the memory 3 is set at the falling edge of the RAS inversion signal. At this time, the LOAD signal, which is the same as the RAS inversion signal, also returns to “low (L)”, and the column address counter 2 generates a column address by the same operation as the conventional example. In short, when the LOAD signal of the column address counter 2 is “low (L)”, the circuit becomes the same as that of FIG. 7 without the initial setting unit of FIG.
The column address is counted by the inversion signal, and the column address is sequentially set in the memory 3.

When one row address has been set, RA
The S-inversion signal is raised to advance the counter value of the row address counter 1, and the column address counter 2 prepares for the LOAD of the next row address. Thereafter, the above operation is repeated.

FIG. 4 is a map diagram of the memory in FIG. As shown in FIG. 4, the memory control mode uses the same page mode as the operation of FIG. 7, but the row address of the address signal and the first column address start from the same value n. Next, the row address n is selected at the falling edge of the RAS inverted signal, and the column address n is selected at the falling edge of the CAS inverted signal. As a result, the selected memory cell of the memory 3 is represented by the hatched portion at the center of the memory map.

The next operation is performed in the same manner as in the prior art in the next CA.
At the fall of the S inversion signal, the column address n +
1 is selected. When the same operation as described above is sequentially repeated and the last address of the memory map is accessed,
Returning to address 0, access is made to column address n-1.

FIG. 5 is a block diagram of a memory address control device for explaining a modification of the device shown in FIG. As shown in FIG. 5, this device divides the configuration of the memory address control device shown in FIG. 1 into a write side and a read side, and has a write address having a row address counter 1 and a column address counter 2 respectively. Control unit 6
And read address control unit 7, and these control units 6,
7 is provided with a switching circuit 5 for switching the output and a memory 3. The row address counter 1 counts a first write clock or a first read clock to generate a row address, and the column address counter 2 generates a second address.
The write address or the second read clock is counted to generate a column address. The output of each column address counter 2 is input to a switching circuit 5 controlled by a write / read switching signal, and the switched signal is supplied to an address input of the memory 3.
This memory address control device requires a switching circuit 5 for switching between writing and reading, but does not require row / column switching.

In such a memory address control device,
Row address counter 1 of write address controller 6
Counts the first write clock from an initial value (usually 0), and returns to the initial value when counting to the final address or a certain set address. The output of the row address counter 1 that counts this clock is input to the column address counter 2, so that the column address counter 2 is set to the same counter value. The column address counter 2 counts the second write clock from the count value, and counts up to the last address or a certain set address.
It returns to the 0 address and starts counting again.

On the other hand, the row address counter 1 and the column address counter 2 in the read address control unit 7 count the first read clock and the second read clock, respectively. This is the same as the counter 1 and the column address counter 2.

Further, the column address counter 2 of the write address control unit 6 and the read address control unit 7
Are output to the memory 3 after being supplied to the switching circuit 5 and switched by the write / read switching signal.
In short, the switching circuit 5 outputs a signal from the column address counter 2 of the write address control unit 6 to the memory 3 when performing a write operation on the memory 3 and conversely, performs a read address control when performing a read operation. A signal from the column address counter 2 of the unit 7 is output to the memory 3.

As described above, according to the present embodiment, in a system including a memory, in order to reduce noise generated at the time of address switching, the first clock is counted from the address signal for accessing the memory and the row is counted. A row address counter that outputs an address, a column address counter that loads a counter value of the row address counter and starts counting from the same counter value when counting the second clock, and a counter value of the column address counter. By having the memory to be accessed, switching between the column address and the row address in the memory can be eliminated, so that noise generated at the time of switching can be suppressed, and the influence on the analog processing system is eliminated. be able to.

Further, according to the present embodiment, as described above, the hold time of the row address and the setup time of the column address can be increased, so that the design becomes easy and the high-speed operation can be performed. it can.

[0040]

As described above, the memory address control device of the present invention counts the first clock and outputs a row address, and loads the counter value of the row address counter, By having a column address counter which starts counting from the same counter value when counting two clocks, and a memory accessed by the counter value of the column address counter, a row address signal and a first column address signal are provided. Can be started from the same value, and the switching of the row / column address in the memory can be eliminated, so that the noise generated at the time of the conventional switching can be suppressed to zero, and the analog signal processing system which is easily affected by the noise can be suppressed. This has the effect that malfunction of the device can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram of a memory address control device for describing an embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of a column address counter in FIG. 1;

FIG. 3 is a timing chart of various signals in FIG. 1;

FIG. 4 is a map diagram of a memory in FIG. 1;

FIG. 5 is a block diagram of a memory address control device for explaining a modification of the device shown in FIG. 1;

FIG. 6 is a block diagram of a memory address control device for explaining an example of the related art.

FIG. 7 is a circuit configuration diagram of a column address counter in FIG. 6;

FIG. 8 is a timing chart of various signals in FIG. 6;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Row address counter 2 Column address counter 3 Memory 4 Initial value setting part 5 Switching circuit 6 Write address control part 7 Read address control part

Claims (3)

(57) [Claims] 1. A row address counter that counts a first clock and outputs a row address, loads a counter value of the row address counter, and starts counting from the same counter value when counting a second clock. A memory address control device, comprising: a column address counter for performing the operation; and a memory accessed by a counter value of the column address counter. 2. The memory address control device according to claim 1, wherein said column address counter includes an initial value setting gate for inputting an initial value setting signal and row address data to set an address to said memory. 3. The memory address control according to claim 1, wherein the row address counter and the column address counter are provided in a write address control unit and a read address control unit, respectively, and are switched by a write / read switching signal to access the memory. apparatus.