KR100263636B1 - Device and method for fast-controlling dynamic random access memory - Google Patents

Abstract

PURPOSE: A control apparatus for a high speed dynamic RAM and method thereof are provided to receive a data clock and a refresh signal from outside to generate an address, DRAM control signal and an internal refresh signal to accelerate the data access and to set corresponding timing by using an access state signal from outside. CONSTITUTION: The control apparatus for a high speed dynamic RAM includes a DRAM control signal generator(100) and a data input/output controller(200). The DRAM control signal generator receives the data clock from outside and generates the address control signal. The data input/output controller receives an input/output order signal, a data clock and data to be stored from outside, receives a CAS(column address strobe) signal from outside from the DRAM control signal generator, stores the data in the DRAM by way of respective data path, receives the data stored in the DRAM by way of the respective data path and outputs the received data to a data port. The DRAM control signal generator further includes a CAS signal generator and an RAS(row address strobe) signal generator. I.

Description

Device and method for fast dynamic ram control {{Device and method for fast-controlling dynamic random access memory}

The present invention relates to a high speed DRAM control device and method (Device and Method for Fast-Controlling Dynamic Random Access Memory), and receives a data clock and a refresh signal from the outside without using a separate register for setting the operation, address, By generating a DRAM control signal and an internal refresh signal, high-speed data access is possible, the corresponding timing is automatically set using an external access state signal, and a storage medium required by controlling input / output for each successive data is selected. It is an object of the present invention to provide a high speed DRAM control apparatus and method that can be reduced.

At present, the global trend of informatization has emphasized the importance of information in all fields. Therefore, in the 21st century, it is essential to establish a database so that a large amount of information of various fields may be first obtained and used when needed. In particular, in order to store such a large amount of information and use the data at high speed, the technology of the memory device is radically improved.

Currently, memory devices used as information storage media include magnetic tapes, optical disks, digital video disks (DVDs), compact disks (CDs), and random access (RAM). access memory (RAM) and read only memory (ROM). Among these, RAMs such as DRAM (Dynamic RAM) and SRAM (Static RAM), which are classified according to data storage methods, are commonly used for data requiring high-speed data processing. Especially, data storage is possible because of high density data storage. And DRAM is the most used as a medium for reading.

In general, DRAM is controlled by an external processor. That is, it is possible to set a memory address indicating a certain location of the memory to store data and to set a corresponding address even when reading desired information. All of these functions are controlled through the DRAM interface from an external processor. do.

In order to understand the operation of the conventional DRAM interface control device, the following describes a US patent (US5530944) to control the DRAM interface through an external processor.

As shown in FIG. 1, a conventional DRAM interface controller receives an address of a DRAM from an external processor and outputs the address to a DRAM, and accesses a control enable signal (bank enable) and a fast state and an arbitrary input / output state. An address decoder 10 that outputs a signal (page hit) and a processor status signal from an external processor to generate a data input / output command signal for reading and storing in a DRAM, and to control a clock of data to be read or stored. The bus cycle control unit 20 which detects a bus cycle and outputs a bus cycle start signal, and sets an operation of the DRAM interface control device through an external processor, and sets an operation setting ridge that transmits the state of the interface device to the processor. The control unit 30 and the control enable signal and the access from the address decoding unit 10 A state signal is received and a bus cycle start signal is received from the bus cycle controller 20, and a low address strobe (RAS) signal and a CAS (address control signal) using a value set in the operation setting register unit 30 are received. A DRAM controller 40 which outputs a column address strobe) signal to the DRAM, and outputs a DRAM status signal indicating a data read and storage state of the DRAM to the bus cycle controller 20, and data read from the data or DRAM to be stored in the actual DRAM. It is composed of a data storage unit 50 for storing data.

In the conventional DRAM interface control device configured as described above, the DRAM is controlled by adjusting a characteristic of a signal for controlling the DRAM interface through a program of a processor. First, a processor located outside the DRAM interface control device provides an external address to the address decoder 10 by a program. The address decoder 10 receiving the input outputs an address to the DRAM through an internal processing process, and outputs a control enable signal for enabling the DRAM controller 30 and an access state signal for a high-speed input / output state. . On the other hand, the bus cycle control unit 20 receiving the status signal of the external processor detects the bus cycle of the processor and transfers the bus cycle start signal synchronized to the DRAM control unit 40 to use as a bus cycle, the DRAM The controller 40 receives a ready state for reading or storing the DRAM and outputs the read state to the external processor. At this time, the status signal of the external processor includes the characteristics of the signals for address control of the DRAM, including the width of the RAS pulse, the conversion time of the RAS pulse, the delay time of the CAS in the RAS, the width of the CAS pulse, the CAS pulse Since the conversion time is included, the DRAM controller 40 outputs a signal for address control using the same.

However, such a conventional DRAM control device has a problem that the circuit for the actual implementation is complicated because it is necessary to adjust the bus cycle of the DRAM by sensing the bus cycle of the external processor, and to incorporate a register for setting the operation. In addition, since the DRAM address is received from an external processor and supplied to the DRAM through a complicated process, the address must be supplied at a high speed from the processor for high-speed data access, and the timing of the DRAM is manipulated through a program of an external processor. Since accessing the system requires access, it is complicated to select an access method, and a program for allocating processor addresses and system control is required, which adds to the complexity of the program of an external processor.

Accordingly, an object of the present invention is to solve such a problem, without receiving a separate register for the operation setting, and receives the data clock and refresh signal from the outside address, DRAM control signal, and internal refresh signal A high-speed DRAM control apparatus capable of high-speed data access by automatically generating a signal, automatically setting a corresponding timing using an external access state signal, and reducing storage media required by controlling input / output for each successive data; and In providing a method.

1 is a block diagram of a DRAM control apparatus according to the prior art;

2 is an application example of a high-speed DRAM control apparatus according to the present invention,

3 is a structural diagram of a high speed DRAM control apparatus according to the present invention;

4 is a structural diagram of a DRAM control signal generator shown in FIG. 3;

5 is a detailed block diagram of a CAS signal generator shown in FIG. 4;

6 is a block diagram illustrating a data input / output controller shown in FIG. 3;

7 is a detailed block diagram of a data input clock generator shown in FIG. 6;

FIG. 8 is a detailed block diagram of the data input controller shown in FIG. 6;

FIG. 9 is a detailed block diagram of the data output controller shown in FIG. 6;

10 is an operation timing diagram of a high speed DRAM control apparatus according to the present invention.

<Description of the code | symbol about the principal part of drawing>

100: DRAM control signal generator 110: CAS signal generator

111: first CAS signal generator 112: second CAS signal generator

113: n-th CAS signal generator 120: RAS signal generator

200: data input / output controller 210: data input clock generator

211: first clock signal generator 212: second clock signal generator

213: third clock signal generator 214: fourth clock signal generator

220: data input control unit 230: data output control unit

231: first read buffer unit 232: second read buffer unit

233: third read buffer unit 234: fourth read buffer unit

The high speed DRAM control apparatus and method according to the present invention for achieving the above object is controlled by a method of setting an external processor, by receiving a data clock from the outside and generating an address and a DRAM control signal synchronized thereto. High-speed data access is possible, and instead of detecting the bus cycle of the external processor, the external refresh signal is input to generate the internal refresh signal, so it is easily linked with the external bus cycle, and the data is simply accessed by receiving the access status signal from the outside. By selecting only, the corresponding timing can be set automatically. In addition, it does not use a separate register for setting an operation, and reduces the storage medium required by controlling input and output for each successive data, thereby providing high-speed data access in a memory control field requiring data storage and reading. It can be implemented as a single chip that satisfies user needs and performs a simple function.

The high-speed DRAM control apparatus according to the present invention, as can be seen in the application example shown in Figure 2, receives a data clock and input data from the outside (column) address control signal (CAS1 ~ CASn) and row address control signal ( RAS) outputs to DRAM, stores external data in parallel (RDATA1 to RDATAn) in DRAM, and reads data stored in DRAM through the same path, and is simply connected between an external processor and DRAM (2). Can be used.

Hereinafter, a high-speed DRAM control apparatus for transmitting data in parallel through four paths will be described as an example.

The high-speed DRAM control apparatus according to the present invention is a DRAM control signal generator 100 for receiving the data clock from the outside as shown in Figure 3 to generate the above address control signals (CAS1 to CAS4 and RAS), and from the outside Data input / output command signals RD / WR, a data clock, and data to be stored are received, and column address control signals CAS1 to CAS4 are received from the DRAM control signal generator 100 through data paths RDATA1 to RDATA4. The data input / output controller 200 is configured to store data in parallel with the DRAM, and receive the data stored in the DRAM in parallel through the data paths RDATA1 to RDATA4 and output the data to the data port.

Hereinafter, the operation of the high speed DRAM control apparatus according to the present invention configured as described above will be described in detail with reference to FIGS. 4 to 10.

As shown in FIG. 4, the DRAM control signal generator 100 receives a data clock from an external source and generates a CAS signal generator 110 generating the column address signals CAS1 to CAS4, and the data clock. It is composed of a RAS signal generator 120 for receiving a row address signal (RAS).

The CAS signal generator 110 receives the data clock from the outside and generates a first CAS signal generator 111 that generates two signals divided by two while the '0' level and the '1' level cross each other. And four CAS signals (CAS1), which are divided into two while receiving '0' level and '1' level from each other by receiving two signals of two divided types of data clocks from the first CAS signal generator 111; And a second CAS signal generator 112 for generating ˜CAS4).

개의 신호를 입력받아 상기 제 1 CAS 신호 발생부(111)에 입력되는 데이터 클럭의

분주된

개의 신호를 발생시키는 제 n CAS 신호 발생부(113)가 포함된다.As shown in FIG. 5, in the case of the CAS signal generator of the high-speed DRAM control apparatus which transmits data in parallel through n paths, the first CAS signal generator 111 and the second CAS signal generator 112. From the n−1 th dispenser in the same manner as

Data signals inputted to the first CAS signal generator 111

Busy

An nth CAS signal generator 113 for generating four signals is included.

The first CAS signal generator 111 receives a first data divider 111-1 for receiving a data clock from an external source and divides the data clock into two divided clocks of the data clock from the first divider 111-1. It is composed of a NOT gate (NOT1) that receives logic and performs logical negation.

The second CAS signal generator 112 receives a data clock divided by two from the first divider 111-1 of the first CAS signal generator 111 and divides the data clock into two again to divide the first CAS signal CAS1. 2-1 divider 112-1, which generates the 2-1 divider, and a data clock divided by 2-1 from the 2-1 divider 112-1, and perform a logic negation operation to perform a third CAS signal CAS3. 2-2 minutes to generate a second CAS signal (CAS2) by receiving a signal from the NOT gate (NOT2) for outputting the signal) and the NOT gate (NOT1) of the first CAS signal generator 111; A period 112-2 and a NOT gate NOT3 for receiving a signal from the second-2 divider 112-2 and performing a logic negation operation to output a third CAS signal CAS4.

Hereinafter, the operation of the DRAM control signal generator 100 of the present invention configured as described above will be described in detail with reference to FIGS. 4 to 5 and 10.

The CAS signal generation unit 110 generates four CAS signals CAS1 to CAS4 having a period four times longer than the period of the data clock input from the outside. First, the first CAS signal generator 111 divides a data clock by two through the first divider 111-1 to generate a signal having a period twice as long as that of the data clock and a logic negation operation of the signal. The received signal is applied to the second CAS signal generator 112. The second CAS signal generator 112 receives the two divided signals of the data clock and the inverted signals thereof from the first divider 111 to perform the same functions of the first divider 111, respectively. The CAS signals CAS1 to CAS4 are generated four times longer than the period of the data clock.

In the four CAS signals generated as described above, as shown in FIG. 10, CAS1 becomes the '1' level first, CAS2 becomes the '1' level sequentially after one period of the data clock, and the next one cycle. Later, CAS3 is at '1' level, and after one cycle, CAS4 is at '1' level. Each CAS signal is continuously generated at four times the data clock period while maintaining the '1' level for two periods of the data clock and '0' for the next two periods.

The RAS signal generator 120 generates a RAS signal for controlling a row address using a data clock as in the conventional RAS signal generator.

As illustrated in FIG. 6, the data input / output controller 200 receives a data clock from an external source, receives a CAS signal from the DRAM control signal generator 100, and receives four data input clocks corresponding to each control signal. A data clock generator 210 for generating (CLOCK1 to CLOCK4), data to be stored in the DRAM and data input / output command signals RD / WR are received from the outside, and a data input clock is received from the data clock generator 210. A data input controller 220 for receiving data and outputting data in parallel to the DRAM; and a data input / output command signal RD / WR from the outside; receiving data in parallel from the DRAM; and receiving the data clock generator 210. And a data output controller 230 for receiving a data input clock from the data output clock and outputting the data to the output port.

As illustrated in FIG. 7, the data input clock generator 210 uses a NOT gate NOT4 that receives a data clock from the outside and performs a logic negation operation, and uses the output of the NOT gate NOT4 as a clock. And a first clock signal generator 211 for outputting a first clock signal CLOCK1 using the CAS1 signal applied from the second-1 divider 112-1 as input data, and the first clock. A second clock signal that uses the same clock as the signal generator 211 and outputs a second clock signal CLOCK2 using the CAS2 signal applied from the second-2 divider 112-2 as input data. The third clock signal CLOCK3 using the generator 212 and the same clock as the first clock signal generator 211 and using the CAS3 signal applied from the NOT gate NOT2 of FIG. 5 as input data. A third clock signal generator 213 for outputting the first clock signal generator; The fourth clock signal generator 214 outputs the fourth clock signal CLOCK4 by using the same clock as the generator 211 and using the CAS4 signal applied from the NOT gate NOT3 of FIG. 5 as input data. It is composed.

Here, the first clock signal generator 211, the second clock signal generator 212, the third clock signal generator 213, and the fourth clock signal generator 214 may each be a D-flip flop. configuration using flip-flop).

The data input controller 220 uses a first clock signal input from the first clock signal generator 211 as a clock to receive data to be stored in the DRAM from the outside and latch the data. A first storage buffer unit 222 which uses data input from the first latch unit 221 as an input, receives an input / output command signal from the outside, and uses the signal as an enable signal to output data to the DRAM; A second latch unit 223 for receiving data to be stored in the DRAM from the outside by using the second clock signal input from the second clock signal generator 212 as a clock, and latching the data; A second storage buffer unit 224 for outputting data to the DRAM using data input from 223 as an input and an input / output command signal from an external device as an enable signal; The third latch unit 225 receives data to be stored in the DRAM from the outside by using the third clock signal input from the clock signal generator 213 as a clock, and latches the data from the third latch unit 225. A third storage buffer unit 226 for outputting data to the DRAM using input data as an input and using an input / output command signal from an external device as an enable signal and input from the fourth clock signal generator 214 The fourth latch unit 227 receives the data to be stored in the DRAM from the outside using the fourth clock signal as a clock, and uses the data input from the fourth latch unit 227 as an input. And a fourth storage buffer unit 228 for outputting data to the DRAM by using the input / output command signal as an enable signal.

Here, the first latch portion 221, the second latch portion 223, the third latch portion 225, and the fourth latch portion 227 are each configured using a delay flip-flop. .

The first storage buffer unit 222, the second storage buffer unit 224, the third storage buffer unit 226, and the fourth storage buffer unit 228 each use a tri-state buffer. To configure.

The data output controller 230 may output an input / output command signal input from the outside, a first clock signal and a second clock signal input from the first clock signal generator 211 and the second clock signal generator 212. A first read buffer using an AND gate AND1 for performing an AND operation and one data RDATA1 input in parallel from a DRAM as an input, and using an output of the AND gate AND1 as an enable signal. Performing an AND operation on the unit 231, an external input / output command signal, and a second clock signal and a third clock signal input from the second clock signal generator 212 and the third clock signal generator 213. The second read buffer unit 232 using the AND gate AND2 to be executed and one data RDATA2 input in parallel from the DRAM as inputs, and using the output of the AND gate AND2 as an enable signal. External input / output command signal An AND gate AND3 for performing an AND operation on the third clock signal and the fourth clock signal input from the third clock signal generator 213 and the fourth clock signal generator 214, and a parallel from DRAM. A third read buffer unit 233 for using one data RDATA3 inputted as an input and using the output of the AND gate AND3 as an enable signal, and an external input / output command signal and the first input signal. An AND gate AND4 for performing an AND operation on the fourth clock signal generator 214 and the fourth clock signal and the first clock signal input from the first clock signal generator 211 and the DRAM in parallel. And a fourth read buffer unit 234 for outputting one data RDATA4 as an input and using the output of the AND gate AND4 as an enable signal.

The first read buffer 231, the second read buffer 232, the third read buffer 233, and the fourth read buffer 234 each use a tri-state buffer. To configure.

Hereinafter, the operation of the data input / output controller 200 of the high speed DRAM interface control apparatus according to the present invention will be described in detail with reference to FIGS. 7 to 10.

The data input clock generator 210 generates a clock to latch the CAS signal at the falling-edge by inverting the data clock input from the outside from the NOT gate NOT4 of FIG. 7. The reason for latching at the falling point is that the CAS signal generated by the CAS signal generator 110 changes at the rising-edge of the data clock, so it is preferable to latch the input value when it is in a stable state. Because. By using this clock, the CAS signal generated by the CAS signal generator 110 is latched by the clock signal generators 211 to 214 constituted by D-flip flops. As shown in Fig. 10, the clock signal generated because it is latched at the falling point of the data clock is lagging by half the period of the data clock than the CAS signal as the input.

The data input controller 220 applies data to be stored to the DRAM by using a clock generated from the data input clock generator 210. That is, since the clocks generated by the data input clock generator 210 sequentially generate rising points at one cycle interval of the data clock, data input from the outside is adjusted from the first latch unit 221 to the clock. The fourth latch unit 221 is sequentially latched in order. When the input / output command signal is '0' (storage state), the three-phase buffers of the storage buffer units 222, 224, 226, and 228 are enabled and transmitted to the DRAM through each path, while the input / output command signal is In the case of '1' (read state), the three-phase buffer constituting the storage buffer unit is in a high-impedance state and data cannot be transferred to the DRAM.

The data output controller 230 outputs data read from the DRAM through an output port through a logical operation of a clock generated from the data input clock generator 210 and an input / output command signal. As shown in FIG. 10, the logical product of the two clocks maintains a '1' level for one period of the data clock, and the period is four times the data clock. The logical product of CLOCK1 and CLOCK2 takes precedence, and the logical product of CLOCK2 and CLOCK3, the logical product of CLOCK3 and CLOCK4, and the logical product of CLOCK4 and CLOCK1 are kept at '1' level in one period of the data clock. do. Accordingly, when the input / output command signal is '1' (read state), the outputs of the AND gates are sequentially generated by the logical product of the clock signal, and the three-phase buffer forming the read buffer unit is also generated by this signal. It is enabled sequentially so that data read from four paths from the DRAM can be sequentially output to the output port. On the other hand, when the input / output command signal is '0' (stored state), the read buffer parts are all in a high-impedance state and data is not transmitted to the output port.

Hereinafter, a high speed DRAM control method according to the present invention will be described.

In the high-speed DRAM control method according to the present invention, a DRAM control signal generation step of receiving a data clock from an external source and generating the address control signal, a data input / output command signal, a data clock and data to be stored from the external source, and the DRAM control Data input / output that receives CAS signal from signal generation step, stores data in DRAM through data paths RDATA1 to RDATA4, and receives data stored in DRAM in parallel through data paths RDATA1 to RDATA4 and outputs them to the output port. It consists of a control phase.

Hereinafter, the operation of the high speed DRAM control method according to the present invention configured as described above will be described in detail.

The DRAM control signal generation step includes a CAS signal generation step of receiving a data clock from an external source and generating a CAS signal, and a RAS signal generation step of receiving the data clock and generating RAS.

The CAS signal generating step includes a first CAS signal generating step of receiving a data clock from an external source and generating two signals divided by two at a data clock while '0' and '1' levels are alternated, and generating the first CAS signal. A second CAS signal generating step of generating two CAS signals CAS1 to CAS4 by receiving two signals inverted in two divided forms of a data clock from the step and performing the same process as the first CAS signal generating step for each of them. It consists of.

Hereinafter, the operation of the DRAM control signal generator 100 of the present invention configured as described above will be described in detail with reference to FIG. 10.

In the first CAS signal generation step of the CAS signal generation step, the second CAS signal generation step is performed by dividing a data clock by two and dividing a signal having a period two times longer than a period of the data clock and a signal that is logically negated and inverted of the signal. To apply. In the second CAS signal generating step, the CAS1 and CAS3 are generated through the same process as the first CAS signal generating step by receiving the two divided signals of the data clock, and receiving the inverted signal to the same as the first CAS signal generating step. The process generates CAS2 and CAS4. The four CAS signals generated as described above are CAS1, CAS3, and CAS4 periodically outputted sequentially in a state where the CAS1 signal is the fastest first, followed by a period of data clock, as shown in FIG. 10.

In the RAS signal generation step, as in the conventional RAS signal generation step, a RAS signal for controlling a row address is generated using a data clock.

The data input / output control step includes a data clock generation step of receiving a data clock from an external source, a CAS signal from the DRAM control signal generation step, and generating four data input clocks CLOCK1 to CLOCK4 corresponding to each control signal; A data input control step of receiving data to be stored in the DRAM and a data input / output command signal from the outside, receiving a data input clock from the data clock generation step, and outputting data to the DRAM; And a data output control step of receiving data in parallel from the DRAM, receiving a data input clock from the data clock generation step, and outputting data to the output port.

The data input clock generation step may include a first clock signal generation step of outputting a first clock signal CLOCK1 using the CAS1 signal applied from the CAS signal generation step, and a CAS2 applied from the CAS signal generation step; A second clock signal generation step of outputting a second clock signal CLOCK2 using the signal as input data; and a third clock signal CLOCK3 outputting using the CAS3 signal applied from the CAS signal generation step as input data; A third clock signal generation step, a fourth clock signal generation step of outputting a fourth clock signal CLOCK4 using the CAS4 signal applied from the CAS signal generation step, and a data clock from an external source; Performing a logic negation operation to generate the first clock signal generation step, the second clock signal generation step, the third clock signal generation step, and And a clock inversion step of providing a clock of the fourth clock signal generation step.

The data input control step receives an input / output command signal from an external source and uses it as an enable signal, receives and stores data to be stored in a DRAM using CLOCK1 input from the first clock signal generation step as a clock, and latches the data. A first storage step of outputting the data to the DRAM, the input / output command signal as an enable signal, and receiving and latching data to be stored in the DRAM using the second clock signal CLOCK2 as a clock. A second storage step of outputting to DRAM, an input signal using the input / output command signal as an enable signal, and receiving and latching data to be stored in the DRAM by using the third clock signal CLOCK3 as a clock; A third storage step of outputting the signal; and using the input / output command signal as an enable signal, the fourth clock signal CLO And a fourth storage step of receiving and latching data to be stored in the DRAM using CK4) as a clock and outputting the latched data to the DRAM.

The data output control step uses one data (RDATA1) input from the DRAM to an output port by using an input / output command signal and a signal obtained by performing a logical multiplication of CAS1 and CAS2 generated in the clock signal generation step as an enable signal. Outputs one data (RDATA2) input from the DRAM by using the first read step to be applied, the input / output command signal, and the signal obtained by performing a logical multiplication of CAS2 and CAS3 generated in the clock signal generation step as an enable signal. One data (RDATA3) input from the DRAM using a second read step applied to the port, an input / output command signal, and a signal obtained by performing a logical multiplication of CAS3 and CAS4 generated in the clock signal generation step as an enable signal. Logic of CAS4 and CAS1 generated in the third read step of applying a signal to the output port, the input / output command signal and the clock signal generation step Consists of a piece of data (RDATA4) using the signal to perform an operation to the enable signal input from the DRAM to read the fourth step to be applied to the output port.

Hereinafter, the operation of the data input / output control step of the high speed DRAM control apparatus according to the present invention will be described in detail with reference to FIG. 10.

In the data input clock generation step, an externally input data clock is inverted to generate a clock to latch the CAS signal at a falling-edge. In the clock signal generation step, the CAS signal generation step is performed using this clock. Latch the CAS signal generated by. As shown in Fig. 10, the clock signal generated because it is latched at the falling point of the data clock is lagging by half the period of the data clock than the input CAS signal.

In the data input control step, data to be stored is applied to the DRAM by using a clock generated from the data input clock generation step. That is, since clocks generated in the data input clock generation step are sequentially raised at one cycle interval of the data clock, externally input data is sequentially latched in accordance with this clock. In this case, when the input / output command signal is '0' (storage state), each storage step is enabled so that data is transferred to the DRAM through each path, while the input / output command signal is '1' (read state). In the storing step, data is not transferred to the DRAM by breaking the connection between each latch step and the DRAM.

In the data output control step, data read from the DRAM is output through an output port through a logical operation of a clock generated from the data input clock generation step and an input / output command signal. As shown in FIG. 10, the logical product of the two clocks maintains a '1' level for one period of the data clock, and the period is four times the data clock. The logical product of CLOCK1 and CLOCK2 takes precedence, and the '1' level is alternately maintained in one cycle interval of the data clock in the order of the logical product of CLOCK2 and CLOCK3, the logical product of CLOCK3 and CLOCK4, and the logical product of CLOCK4 and CLOCK1. Done. Accordingly, when the input / output command signal is '1' (read state), the output of each logical AND step is sequentially generated by the logical AND of the clock signal, and each read step is sequentially performed by this signal. Enabled to sequentially output data read from four paths from the DRAM to the output port. On the other hand, when the input / output command signal is '0' (stored state), each read step is disabled and data is not transmitted to the output port.

According to the high-speed DRAM control apparatus and method according to the present invention described above, by accessing the data clock from the outside and generating an address and a DRAM control signal synchronized thereto, high-speed data access is possible, and detecting a bus cycle of an external processor. Instead, by receiving an external refresh signal and generating an internal refresh signal, it is easily linked with an external bus cycle, and by receiving an access status signal from the outside, simply selecting a data access method to automatically set a corresponding timing. In addition, it does not use a separate register for setting an operation, and reduces the storage medium required by controlling input and output for each successive data, thereby providing high-speed data access in a memory control field requiring data storage and reading. It can be implemented as a single chip that meets the user's needs and performs a simple function, thereby securing the reliability and price competitiveness of the control device.

Claims (22)

In an apparatus for controlling DRAM using an external processor: A DRAM control signal generator which receives a data clock from an external source and generates the address control signal; Input and output command signals, data clocks and data to be stored from the outside, and receives a CAS (Column Address Strobe) signal from the DRAM control signal generator to store the data in the DRAM through each data path, and to store the data stored in the DRAM A high speed DRAM control device comprising a data input and output control unit 200 for inputting through each data path and outputting to the data port. The method of claim 1, wherein the DRAM control signal generation unit A CAS signal generator for receiving a data clock from an external source and transmitting a CAS signal; And a RAS signal generation unit configured to receive the data clock and generate a RAS signal. The method of claim 2, wherein the CAS signal generation unit A first CAS signal generator which receives a data clock from an external source and generates a two-divided signal of the data clock while crossing the '0' level and the '1' level; A second CAS signal generator for receiving two divided signals of the data clock from the first CAS signal generator and generating a CAS signal re-divided by crossing the '0' level and the '1' level, respectively. High speed DRAM control device characterized in that. The method of claim 3, wherein the first CAS signal generating unit A first divider which receives a data clock from the outside and divides the data clock by two; And a first NOT gate configured to receive a two divided signal of a data clock from the first divider and perform a logic negation operation. The method of claim 3, wherein the second CAS signal generating unit A 2-1 divider which receives a data clock divided by two from the first divider of the first CAS signal generator and divides the data clock into two again to generate a first CAS signal; A NOT gate configured to receive a data clock divided by the 2-1 divider and perform a logic negation operation to output a third CAS signal; A second-2 divider which receives a signal from the first NOT gate of the first CAS signal generator and divides the signal into two to generate a second CAS signal; And a third NOT gate configured to receive a signal from the second divider and perform a logic negation operation to output a third CAS signal. The CAS signal generator of claim 2, wherein the CAS signal generator of the high-speed DRAM controller transmits data in parallel through n paths. A first CAS signal generator configured to receive a data clock from an external source and generate a two-divided signal of the data clock while crossing the '0' level and the '1' level; And And a second divider and a NOT gate having the same structure as that of the first CAS signal generator, and are connected in series to the nth CAS signal generator including n modules. The method of claim 6, wherein the n-th CAS signal generating unit Generating a CAS signal of CAS1 and CAS (n / 2 + 1) in the first module; Generating a CAS signal of CAS2 and CAS (n / 2 + 2) in a second module; A high speed DRAM control apparatus characterized by repeating the same method as above to generate CAS signals of CAS (n / 2) and CAS (n) in the last module. The method of claim 1, wherein the data input and output control unit A data clock generator which receives a data clock from an external source, receives a CAS signal from the DRAM control signal generator, and generates a data input clock corresponding to each control signal; A data input controller which receives data to be stored in the DRAM and a data input / output command signal from an external source, receives a data input clock from the data clock generator, and outputs data in parallel to the DRAM; A high speed DRAM comprising: a data output control unit configured to receive a data input / output command signal from an external source, receive data in parallel from a DRAM, receive a data input clock from the data clock generator, and output data to an output port; controller. The method of claim 8, wherein the data input clock generator A fourth NOT gate configured to receive a data clock from an external source and perform a logic negation operation; A first clock signal generator for outputting a first clock signal using the output of the fourth NOT gate as a clock and using the CAS1 signal applied from the 2-1 divider as input data; A second clock signal generator using the same clock as the first clock signal generator and outputting a second clock signal using the CAS2 signal applied from the second-2 divider as input data; A third clock signal generator using the same clock as the first clock signal generator and outputting a third clock signal using the CAS3 signal applied from the second NOT gate as input data; And a fourth clock signal generator for outputting a fourth clock signal by using the same clock as the first clock signal generator and using the CAS4 signal applied from the third NOT gate as input data. DRAM control unit. 10. The apparatus of claim 9, wherein the first clock signal generator, the second clock signal generator, the third clock signal generator, and the fourth clock signal generator are each configured as a D flip-flop. A high speed DRAM control device, characterized in that. The method of claim 8, wherein the data input control unit A first latch unit which receives data to be stored in DRAM from outside by using the first clock signal as a clock and latches the data; A first storage buffer unit which receives an input / output command signal input from the outside and uses the signal as an enable signal to receive data from the first latch unit and output data to the DRAM; A second latch unit which receives data to be stored in a DRAM from an external source and latches the data by using the second clock signal as a clock; A second storage buffer unit which receives an input / output command signal input from the outside and uses the signal as an enable signal to receive data from the second latch unit and output data to the DRAM; A third latch unit which receives data to be stored in DRAM from outside by using the third clock signal as a clock and latches the data; A third storage buffer unit which receives an input / output command signal input from the outside and uses the signal as an enable signal to receive data from the third latch unit and output data to the DRAM; A fourth latch unit which receives data to be stored in the DRAM from outside by using the fourth clock signal as a clock and latches the data; And a fourth storage buffer unit configured to receive an input / output command signal input from the outside and use the signal as an enable signal to receive data from the fourth latch unit and output data to the DRAM. 12. The apparatus of claim 11, wherein the first latch portion, the second latch portion, the third latch portion, and the fourth latch portion are each configured using a D-flip flop. The method of claim 11, wherein the first storage buffer unit, the second storage buffer unit, the third storage buffer unit and the fourth storage buffer unit is configured using a three-phase buffer (Tri-state buffer), respectively High speed DRAM control device. The method of claim 8, wherein the data output control unit A first AND gate configured to perform an AND operation on an input / output command signal input from an external device, the first clock signal, and the second clock signal; A first read buffer unit using first data input from a DRAM as an input and using an output of the first AND gate as an enable signal; A second AND gate configured to perform an AND operation on an input / output command signal input from an external device, the second clock signal, and the third clock signal; A second read buffer unit using second data input from a DRAM as an input and using an output of the second AND gate as an enable signal; A third AND gate configured to perform an AND operation on an input / output command signal input from an external device, the third clock signal, and the fourth clock signal; A third read buffer unit using third data input from a DRAM as an input and using an output of the third AND gate as an enable signal; A fourth AND gate configured to perform an AND operation on an input / output command signal input from an external device, the fourth clock signal, and the first clock signal; And a fourth read buffer unit using fourth data input from the DRAM as an input and using the output of the fourth AND gate as an enable signal. The method of claim 14, wherein the first read buffer unit, the second read buffer unit, the third read buffer unit and the fourth read buffer unit are configured using a tri-state buffer, respectively. High speed DRAM control device. In a method of controlling DRAM using an external processor: A DRAM control signal generating step of receiving a data clock from an external source and generating the address control signal; Data input / output command signal, data clock and data to be stored are received from the outside, CAS signal is received from the DRAM control signal generation step, data is stored in the DRAM through the data path, and data stored in the DRAM is received through the data path. A high speed DRAM control method comprising a data input and output control step output to an output port. The method of claim 16, wherein the DRAM control signal generation step A CAS signal generation step of receiving a data clock from an external source and generating a CAS signal; And a RAS signal generation step of generating the RAS by receiving the data clock. 18. The method of claim 17, wherein the CAS signal generating step A first CAS signal generation step of receiving a data clock from an external source and generating two signals divided by two of the data clock while '0' and '1' levels are alternated; Generating CAS signals CAS1 to CAS4 by receiving two signals inverted in two divided forms of the data clock from the first CAS signal generating step and performing the same process as the first CAS signal generating step for each of them. And a second CAS signal generating step. The method of claim 16, wherein the data input and output control step A data clock generation step of receiving a data clock from an external source, receiving a CAS signal from the DRAM control signal generation step, and generating four data input clocks corresponding to each control signal; A data input control step of receiving data to be stored in the DRAM and data input / output command signals from the outside, receiving a data input clock from the data clock generation step, and outputting data to the DRAM; A high speed data output control step of receiving a data input / output command signal from an external device, receiving data in parallel from a DRAM, receiving a data input clock from the data clock generation step, and outputting data to an output port DRAM control method. 20. The method of claim 19, wherein generating the data input clock A first clock signal generation step of outputting a first clock signal using the CAS1 signal applied from the CAS signal generation step as input data; A second clock signal generation step of outputting a second clock signal using the CAS2 signal applied from the CAS signal generation step as input data; A third clock signal generation step of outputting a third clock signal using the CAS3 signal applied from the CAS signal generation step as input data; A fourth clock signal generation step of outputting a fourth clock signal using the CAS4 signal applied from the CAS signal generation step as input data; And a clock inversion step of receiving a data clock from an external source and performing a logic negation operation to provide a clock signal to the clock signal generation steps. 20. The method of claim 19, wherein the data input control step is Receives input and output command signals from the outside and uses them as enable signals, receives and stores data to be stored in the DRAM by using the first clock signal input from the first clock signal generation step as a clock, and latches the latched data to the DRAM. A first storing step of outputting; A second storing step of using the input / output command signal as an enable signal, receiving and latching data to be stored in the DRAM by using the second clock signal as a clock, and outputting the latched data to the DRAM; A third storing step of using the input / output command signal as an enable signal, receiving and latching data to be stored in the DRAM using the third clock signal as a clock, and outputting the latched data to the DRAM; And a fourth storing step of using the input / output command signal as an enable signal, receiving and latching data to be stored in the DRAM using the fourth clock signal as a clock, and outputting the latched data to the DRAM. High speed DRAM control method. 20. The method of claim 19, wherein the data output control step is A first read step of applying first data input from the DRAM to an output port using an input / output command signal and a signal obtained by performing a logical multiplication of CAS1 and CAS2 generated in the clock signal generating step as an enable signal; A second read step of applying second data input from the DRAM to an output port using an input / output command signal and a signal obtained by performing an AND operation on the CAS2 and CAS3 generated in the clock signal generation step as an enable signal; A third read step of applying third data input from the DRAM to an output port using an input / output command signal and a signal obtained by performing a logical multiplication of CAS3 and CAS4 generated in the clock signal generating step as an enable signal; And a fourth read step of applying the fourth data input from the DRAM to the output port by using the input / output command signal and the signal obtained by performing the AND operation on the CAS4 and CAS1 generated in the clock signal generation step as the enable signal. A high speed DRAM control method, characterized in that.

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