JPH0243645A - Storage device - Google Patents

Abstract

PURPOSE:To quicken a writing speed and to improve the processing speed of a system by simultaneously accessing plural addresses designated by the low order bit of an address. CONSTITUTION:A high order bit 1 of the address is designated in the access time of a storing circuit 3, and the contents of the plural addresses designated by the low order bit 9 are simultaneously accessed. Further, data are successively read to a latch circuit 2 in a selecting circuit 5 with a clock quicker than the access of the storing circuit 3. Consequently, the data of continuous addresses can be simultaneously written to the storing circuit. Thus, the data can be stored at a high speed without depending on the access time of the storing circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a storage device, and particularly to a storage device in which sequential addresses are frequently written.

[Conventional technology]

Conventionally, in this type of storage device, an address is specified by an address pointer or a next address set in a storage area, and data of the storage contents is inputted at a timing that matches the access timing, and data is written one by one.

[Problem to be solved by the invention]

In the conventional storage device described above, the system using this storage device prepares and supplies an address and data to be stored each time a write is performed, so it is not possible to increase the writing speed, and it is difficult to improve the processing speed of the system. The disadvantage is that it is difficult to

[Means to solve the problem]

The storage device of the present invention has a memory circuit that is re-addressed by the upper bit G of the address, an arbitrary number of lower bits of the address, and a designated clock of at least two different clocks. a counter that counts up, a selection circuit that selects and latches data to be input to the storage circuit based on the output of this counter, and a latch that latches the data latched in the selection circuit as data to be written to the storage circuit. It is configured by having a circuit.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a more detailed block diagram of the selection circuit of FIG. 1. In FIGS. 1 and 2, the latch circuit 2 latches the upper bit 1 of the address in synchronization with the clock C1, and accesses the address of the storage circuit 3 specified by the upper bit 1. The counter 6 is set with the numerical value of the lower bit 9 of the address from the higher-order device of this storage device, and the clock C1 or clock C1 specified by the clock change circuit 10.
The count is increased from the set value according to the clock C2 which is multiple times faster than the clock C2. The selection circuit 5 includes a plurality of latch circuits 41, 42, .
52, .
2...4N, and outputs an enable signal from the enable signal generation circuits 51, 52...5N. Further, the selection circuit output signal outputted from the selection circuit 5 is latched by the latch circuit 4 in synchronization with the rise of the reverse phase clock C1 of the clock C1. Also, clock C
All the enable signals are also latched by the latch circuit 4 in synchronization with the rising edge of 1. Furthermore, the enable reset signal 13 is sent to the enable signal generation circuit 51 .in synchronization with the next rising edge of the clock C1. . . 5N to reset all enable signals, and similarly, the latch circuit 4 adds an enable signal to the output signal of the selection circuit and the enable signal read in synchronization with the rising edge of the clock C1. input the data into the memory circuit 3.

FIG. 3 is a timing chart of FIGS. 1 and 2. The clock C1 is a clock dependent on the access time of the memory circuit 3, and the memory circuit 3 is synchronized with the rise of the clock C1. Clock C2 is clock C1
The clock has a shorter period, and the counter 6 counts in synchronization with the clock C1 or C2. The clock change signal is sent from the clock change circuit 10 to the counter 6.

When this signal is low level, the counter 6 outputs the clock C.
2 and controls the selection circuit 5 to input data 11 at high speed. When the clock change signal is at a high level, the counter 6 inhibits input of data 11 in synchronization with the clock C1. At the next timing of clock C1, address lower bit 9 is initialized,
Start importing data 11. Enable signal generation circuits 51 and 52 added to the latch circuit of the selection circuit 5
...5N outputs an enable signal in synchronization with the rising edge of the clock C2, and resets the enable signal by the enable reset signal 13 inputted at the rising edge of the clock C1.

FIG. 4 is an example diagram of data transfer and storage in FIGS. 1 and 2. In FIG. 4, first, input data 11 is input at the rising edge of clock C2.
21'', ``A9'', ``8E'', and ``CF'' are read into the latch circuits 41, 42...44 in the selection circuit 5 in this order. At the same time as this reading, an enable signal is added. is output to the latch circuit 4 at the rising timing of the clock C1.

It is shown that the data read into the latch circuit 4 is written into the memory circuit 3 receiving the address upper bit "2'° at the timing of the rise of the clock C1."

〔Effect of the invention〕

As explained above, the present invention specifies the upper bits of an address within the access time of the memory circuit, and simultaneously accesses the contents of a plurality of addresses specified by the lower bits. Data can be sequentially read into the latch circuit in the selection circuit, and data at consecutive addresses can be simultaneously written to the storage circuit, so data can be stored at high speed without being dependent on the access time of the storage circuit. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a detailed block diagram of the selection circuit shown in FIG. 3, a timing diagram of main points in FIG. 1, and FIG. 4 is an example diagram of data transfer and storage in FIGS. 1 and 2. 1... Upper bit of address, 2, 4, 41°42~
4N... Latch circuit, 3... Memory circuit, 5... Selection circuit, 6... Counter, 9... Lower bit of address, 10... Clock change circuit, 11... Data, 1.2... Counter output signal, 13... Enable reset signal.

Claims (1)

[Claims] a memory circuit that is readdressed by the upper bits of the address; a counter that sets an arbitrary number of lower bits of the address and counts up using a designated clock of at least two different clocks;
It is characterized by having a selection circuit that selects and latches data to be input to the storage circuit based on the output of the counter, and a latch circuit that latches the data latched by the selection circuit and uses the data to be written into the storage circuit. storage device.