JPS61230515A - Data variable delay device - Google Patents

Abstract

PURPOSE:To decrease number of components and to increase the maximum delay amount by providing a random access memory, a random access memory address control circuit and a random access memory control circuit. CONSTITUTION:A random access memory address signal having a set delay quantity as a period is generated by the random access memory address control circuit (address counter) 5, and the delay quantity set by an input data series signal according to a random access memory address signal and a random address memory control signal is kept by a random access memory control circuit 29, the 1st random access memory 12 and the 2nd random access memory 13 and a delay output data series signal 16 delayed by the set delay quantity is outputted. Thus, the number of components is decreased and the maximum delay quantity is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data variable delay device that delays an input data sequence signal by an externally set delay amount.

[Conventional technology]

FIG. 5 is a configuration example showing a conventional variable data delay device. In the figure, 1 is a reference clock signal, 21 is an n-bit parallel latch circuit (n is an integer), and 2 is a circuit synchronized with the reference clock signal 1. a pit input data series signal inputted by
22 is a 1 clock delay data signal, 23 is a 2 clock delay data signal, 24 is a 3 clock delay data signal, 25
26 is a clock delayed data signal, 27 is a delay amount setting data signal, 28 is a selector, and 16 is a delayed output data series signal.

Next, the operation will be explained. The n-bit parallel latch circuit 21 at the first stage latches at the timing of the n-pit input data series signal 2t - the reference clock signal 1, and outputs a one-clock delayed data signal 22.

The n-bit parallel latch circuit 21 at the next stage latches at the timing of the 1-clock delayed data signal 23t - the reference clock signal 1, and outputs the 2-clock delayed data signal 23.

Similarly, the n-bit parallel latch circuits 21 from the third stage to the second stage output the clock delayed data signal 26t from the 3 clock delayed data signal 24. Next, the selector 28 selects a clock delay data signal 2 from the n-bit input data series signal 2 and the 1 clock delay data signal 22.
6, the delay data signal corresponding to the delay amount setting data signal 27 is selected, and the delayed output data series signal 16 of the set delay amount is output.

[Problems to be Solved by the Invention] Since the conventional data variable delay device is configured as described above, in order to obtain a delayed data signal with a large amount of delay, the hardware size becomes enormous, However, as the scale of hardware increases, element delays increase, making it difficult to operate in synchronization with a reference clock signal, and there is a limit to the maximum amount of delay.

This invention was made in order to solve the above-mentioned problems, and the purpose is to obtain a data variable delay device that can increase the maximum delay amount without increasing the scale of the nodeware. shall be.

[Means for solving problems]

The data variable delay device according to the first invention of this application includes first and second random access memories for storing input data sequence signals, and first and second random access memories that store input data sequence signals, and first and second random access memories that store input data sequence signals. A random access memory address control circuit that generates write and read address signals for the second random access memory, and writes for the first and second random access memories.

A random access memory control circuit that generates a signal for controlling reading is provided.

The variable data delay device according to the second invention of this application includes a random access memory that stores an input data sequence signal, and generates write and read address signals for the random access memory in accordance with a set delay amount. This invention includes a random access memory address control circuit and a random access memory control circuit that generates a signal for controlling writing and reading of the random access memory, thereby reducing the number of random access memories used compared to the first invention.

[Effect]

The data variable delay device in the first invention of this application is:
A random access memory address signal having a period equal to the set delay amount is generated by the random access memory address control circuit, and the first . Write and read control signals for the second random access memory are generated, and the first. The second random access memory holds the input data sequence signal by a set delay amount according to the random access memory address signal and the random address memory control signal, and outputs a delayed output data sequence signal delayed by the set delay amount.

The data variable delay device in the second invention of this application is
Similar to the first invention, the random access memory address control circuit generates a random access memory address signal having a period equal to the set delay amount, and the random access memory control circuit generates random access memory write and read control signals. The input data sequence signal is held by the set delay amount according to the random access memory address signal and the random access memory control signal, and a delayed output data sequence signal delayed by the set delay amount is output.

〔Example〕

An embodiment of the first invention will be described below with reference to the drawings. In Figure 1, 1 is a reference clock signal, 2 is an n-bit human data series signal (n is an integer) that is input in synchronization with reference clock signal 1, and 3 is a delay that delays the n-bit human data series signal 2. 4 is a random access method address signal (hereinafter referred to as a RAM address signal); 5 is a delay amount setting data signal 3t-human power As a signal, an address counter (random access memory address control circuit) that outputs a RAM address signal 4t in synchronization with the reference clock signal 1, a carry signal of the 6Fi address counter 5, and 7 a random access memory select using the carry signal 6 as an input signal. signal (hereinafter referred to as R
It is called an AM select signal. ) T-type flip-flop that outputs 8, 8 is a RAM select signal that selects write random access memory and read random access memory, 9 creates a write enable signal using the RAM select signal 8 and reference clock signal t' as input signals. 10 is a first random access memory (hereinafter referred to as a first RA) which will be described later.
It is called M. ) 12, 11 is a second random access memory (to be described later).
Hereinafter, it will be referred to as a second RAM. ) 13 is the second write enable signal, 12 is the first RAM that stores the n-bit human data series signal 2 for the number of clocks determined by the delay amount setting data signal 3, 13 is the same as the first RAM 12 A second RAM with functions, 14 is the first RAM 12
15 is the first output data signal output from the second R
A second output data signal output from AM13, 16 a delayed output data series signal, 17 a RAM select signal 8
Accordingly, a selector 29 for selecting the delayed output data series signal 16 from the first output data signal 14 and the second output data signal 15 is composed of the write enable signal generator 9, the T-type flip-flop 7, and the selector 17. A random access memory control circuit formed.

FIG. 2 shows a 4-bit up counter as the address counter 5 in FIG.
This is a timing chart when a RAM t- of n pits x 16 words is used as I3, and delay amount setting data 3 t-r2J is used.

Next, the operation will be explained with reference to the timing chart shown in FIG. The address counter 5 counts up at the rising edge of the reference clock signal 1, and outputs the counted up value as the RAM address signal 4. When the value of the RAM address signal 4 is counted up to 15, the address counter 5 outputs a carry signal 6, and the carry signal 6 causes the value of the delay amount setting data signal 3 to be "2" at the next rising edge of the reference clock signal. ” and outputs “2” as the value of RAM address signal 4. By repeating the above operation, the address counter 5 generates the RAM address signal 4 in synchronization with the reference clock signal 1...2, 3, 4, 5, 6, . ......, 1
5, 2, 3. Output at the cycle of... Incidentally, the carry signal 6 is also input to a T-type flip-flop 7, and the T-type flip-flop 7 outputs a RAM select signal 8 whose high and low levels are inverted at the fall of the carry signal 6. The RAM select signal 8 is the first
This signal indicates whether the RAM 12 and the second RAMI 3 are in the data signal writing period or the data signal reading period. In the timing chart of FIG. 2, when the RAM select signal 8 is high, the first RAM 12
is the write period, the second RAM M13 is the read period, and on the other hand, when the RAM select signal signal port is -, the first RAM M12
is the read period, and the second RAM 13 is the write period. Writing data signals to the first RAM 12 and the second RAMI 3 is directly performed by the first write enable signal 10 and the second write enable signal 11 output from the write enable signal generator 9. controlled. The input data series signal 2 is written to the first RAM 12 and the second RAM 13 while the first write enable signal 10 and the second write enable signal 11 are low, and conversely, the input data series signal 2 is written to the first RAM 12 and the second RAM 13 while the first write enable signal 10 and the second write enable signal 11 are low. While the enable signal 10 and the second write enable signal 11 are high, the first RAM
I2, read from the second RAM 13. As shown in the timing chart of FIG. 2, the write enable signal generator 9 generates a signal that goes low in 10 cycles of the reference clock signal only when the RAM select signal 8 is high, that is, when the first RAMI 2 is in the write period. The write enable signal 10f of 1 and the second 2 which become low in the period of the reference clock signal 1 only when the RAM select signal 8 is low, that is, when the second RAM 13 is in the write period.
6 first RAM 12 that outputs an enable signal 11;
Then, while the first write enable signal 10 is low, the input data signal is written to the address indicated by the RAM address signal 4, and while the RAM select signal 8 is low, the input data signal is written from the address indicated by the RAM address signal 4. The first output data signal 14 is read out. In the second RAM 13, while the second 2-item enable signal 11 is low,
The input data signal is written to the address indicated by the RAM address signal 4, and while the RAM select signal 8 is high, the R
The second output data signal 15 is read from the address indicated by the AM address signal 4. The selector 17 uses the RAM select signal a1 to select the data signal read out during the read period from the first output data signal 14 and the second output data signal 15, and outputs the continuous output data series signal 1.
Output as 6. As mentioned above, the first RAM 12,
In the second RAM 13, each RAM address signal 4
2.3, 4. . . . , 15 Since writing and reading are performed alternately with a period of 14 addresses, the input n-pit input data series signal 2 is delayed by 14 reference clocks and becomes the delayed output data series signal 16. is output as

In the above embodiment, the number of pits of the RAM address signal 4 is determined arbitrarily by connecting up counters in multiple stages as the address counter 5, and the number of words corresponding to the number of addresses is set as the first RAM 12 and the second RAM 13. By using RAMt- with RAMt-, it is possible to construct a data variable delay device with an arbitrary maximum delay amount. Further, a down counter may be used as the address counter 5.

Next, an embodiment of the second invention will be described with reference to the drawings. In FIG. 3, the same or equivalent parts as in FIG. 1 are designated by the same reference numerals. Reference numeral 18 denotes a random access memory (hereinafter referred to as
It is called RAM. λ19 is a write enable signal, 20
is a write enable signal generator (random access memory control circuit) which receives the reference clock signal 1 as an input signal and outputs a write enable signal 19.

Figure 4 shows a 4-bit up counter as address counter 5 in Figure 3, and n bits as RAM1 B)
Using the word RAMt-, the delay amount setting data signal 3 is
2" is a timing chart.

Next, the operation will be explained in accordance with the timing chart of FIG. 4. Write enable signal generator 2
0 uses the reference clock signal 1 as an input signal and outputs a write enable signal 19 shown in the timing chart of FIG. The operation of the address counter 5 is similar to that in the first embodiment of the invention, . . . , 14, 15, 2.
, 3.4. ......, 15, 2. The RAM address signal 4t- is output as shown below. The RAM 18 outputs the delayed output data signal 16 during the period in which the write enable signal 19 is high in the first half of one reference clock 1;
Write n-pit input data signal 2yk in the second half low period ・RAM address signal 4 within 1 reference clock signal 1
Since is constant, reading and writing are performed on data at the same address. As mentioned above, RAM1
B, RAM address signal 4 2.3, 4 . ......, the same reference clock signal 1 with a period of 14 addresses of 15
Since the reading and writing of data is repeated, the input n-bit human data series signal 2 is output as a delayed output data series signal 16 delayed by 14 reference clocks. Note that in the above embodiment, the write enable signal If the falling timing of signal 19 is always delayed from the falling timing of reference clock signal 1, it becomes possible to latch at the falling edge of delayed output data series signal 16t - reference clock signal 1, and it is possible to easily obtain an effective delayed output. It is possible to configure a data variable delay device in which only the data sequence signal 16 is output. In addition, by arbitrarily determining the number of pits of the RAM address signal 4 by connecting up counters in multiple stages as the address counter 5, and using a RAM having the number of words corresponding to the number of addresses as the RAM 18, it is possible to achieve an arbitrary maximum delay amount. A data variable delay device can be configured. Further, a down counter may be used as the address counter 5.

In this way, according to the data variable delay device of the second invention,
The structure can be simpler than the device of the first invention, and the number of elements can be reduced.

〔Effect of the invention〕

As described above, according to the present invention, a data variable delay device that outputs a delayed output data sequence signal using an input data sequence signal, a delay amount setting data signal, and a reference clock signal as input signals can be used as a random access memory, a random access memory, and a random access memory. Since it is configured using an address control circuit and a random access memory control circuit, the number of elements used is reduced, making it possible to increase the maximum delay amount, and making it possible to
Furthermore, when integrated into an LSI, it is possible to obtain an LSI that does not require any input/output signals other than the above-mentioned signals. Further, according to the second invention, the configuration of the device can be further simplified and the number of used elements can be reduced.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a data variable delay device according to an embodiment of the first invention, Fig. 2 is a timing chart of the signals in Fig. 1, and Fig. 3 is an embodiment of the second invention. FIG. 4 is a diagram showing a timing chart of the signals in FIG. 3, and FIG. 5 is a diagram showing a conventional variable data delay device. In the figure, 1 is a reference clock signal, 2 is an input data series signal, 3 is a delay amount setting data signal, 4 is a random access memory address signal, 5 is an address counter (random access memory address control circuit), and T is a T-type flip-flop. 9 is a write enable signal generator, 10° and 11 are 1st. a second two-item enable signal, 12 a first random access memory, 13 a second random access memory, 14, 15 a first . A second data output signal, 16 a delayed output data sequence signal, 18 a random access memory, 19 a write enable signal, and 20 a write enable signal generator (random access memory control circuit). In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (2)

[Claims] (1) a first random access memory and a second random access memory each having a capacity capable of holding a data sequence signal input based on a system reference clock signal for a period corresponding to a predetermined amount of delay; The first and second random accesses are performed using a delay amount setting data signal as an input signal for setting a delay amount for delaying an input data series signal based on a reference clock signal of the system so that the delay amount becomes a period. A random access memory address control circuit that generates an address signal for the memory, and the first and second random access memories based on the reference clock signal of the system, are used on the write side or on the read side, with the delay amount as a period. The system includes a random access memory control circuit that generates a random access memory selection signal and a random access memory write enable signal used to alternately switch between the system's reference clock signal and the delay amount setting data. 1. A variable data delay device, which outputs an input data series signal after delaying it by a predetermined amount of delay based on a system reference clock signal. (2) A random access memory with a capacity capable of holding a data sequence signal inputted based on a system reference clock signal for a period corresponding to a predetermined amount of delay, and an input data sequence signal inputted based on a system reference clock signal. a random access memory address control circuit that receives a delay amount setting data signal as an input signal for setting a delay amount for delaying a signal and generates an address signal for the random access memory so that the delay amount becomes a period; and a system reference. and a random access memory control circuit that generates a write enable signal for controlling writing and reading of the random access memory to be performed alternately in time division during one period of the clock signal, and a system reference clock. A data variable delay device characterized in that the input data series signal is delayed by a predetermined delay amount and outputted based on the reference clock signal of the system from the signal and the delay amount setting data signal.