JPH06275072A - Semiconductor storage - Google Patents

Abstract

PURPOSE:To facilitate the timing setting between control signals. CONSTITUTION:This device is provided with a timing generation circuit 1 constituted of a frequency conversion circuit 2 converting the frequency of an external signal to a high frequency or a low frequency and an output control circuit 3 controlling the output of an internal signal by the output signal of the frequency conversion circuit 2. Thus, since the frequency of the external signal is changed in the inside, and a required delay time is obtained by using the magnitude of the frequency, the control signals of respective circuits are controlled synchronizing with the external signal, and the deviation in the timing between control signals of respective circuits occurring due to the changes in power source voltage and a temperature are prevented, and the timing setting between respective control signals are facilitated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a timing generation circuit.

[0002]

2. Description of the Related Art Semiconductor integrated circuits such as DRAMs include not only combinational logic circuits but also analog circuits such as amplifiers. Therefore, when operating a plurality of circuits, each circuit is unique. It is necessary to control the timing, and various delay circuits are used to set the timing.

Further, as shown in FIG. 11, a synchronous DRAM, which is one of the memories capable of inputting / outputting data at high speed in synchronization with the system clock in response to the recent increase in speed of microprocessors, is also available. , The internal circuits other than the I / O system are each controlled by a timing signal in which a timing peculiar to each circuit is set by using an inverter chain.

FIG. 12 shows operation waveforms of a conventional semiconductor memory device. In FIG. 12, (a) is an external input clock signal CLK, (b) is a word line enable signal, (c) is a sense amplifier enable signal, (d) is a column address selection signal, and (e) is a data output buffer. The output data of is shown. In the conventional semiconductor memory device, as shown in FIGS. 11 and 12, various timings of signals for controlling circuits other than the I / O system are asynchronously determined by using a delay circuit such as an inverter.

[0005]

However, in the conventional semiconductor memory device, since the timing of the control signal of each circuit other than the I / O system is set by using a delay circuit such as an inverter, the power supply voltage, Due to the difference in the delay time between the control signals of each circuit due to the temperature change, it is difficult to determine the timing of starting each circuit, and attempts have been made to suppress the variation in this timing. (JP-A-63-327715).

The present invention solves the above-described problems, and the timing signal for determining the operation timing of various different internal circuits is not affected by the fluctuation of the power supply voltage or the temperature of the operation of each circuit. It is an object of the present invention to provide a semiconductor memory device that can be easily set and adjusted.

[0007]

A semiconductor memory device of the present invention is a frequency conversion circuit having a high frequency conversion circuit for converting the frequency of an external signal into a high frequency and a low frequency conversion circuit for converting the frequency of an external signal into a low frequency. A circuit, an output control circuit that generates a control signal in synchronization with the output of this frequency conversion circuit, a data storage unit that reads or writes data in parallel according to the control signal, and the read data of this data storage unit that is synchronized with an external signal. And a serial output unit for sequentially outputting data, and a serial input unit for sequentially writing external data in a data storage unit in synchronization with an external signal.

[0008]

According to the semiconductor memory device of the present invention, a clock having several kinds of frequencies is newly created inside, and the delay time is adjusted by utilizing the cycle of this clock.
It is possible to obtain a desired delay time without using a delay circuit that uses the charging / discharging time, which makes it possible to control control signals with various timings in synchronization with external signals, and to control temperature and power supply voltage. It is possible to eliminate the variation in the timing of the control signal depending on the. Especially when it is used for DRAM, its effect is great.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a conceptual diagram of one embodiment of the semiconductor memory device of the present invention. In FIG. 1, 1 is a timing generation circuit, 2 is a frequency conversion circuit, 3 is an output control circuit,
4 is a row address buffer, 5 is a row decoder, 6 is a word line driver, 7 is a column address buffer, 8
Is a column decoder, 9 is a memory cell array, 10 is a sense amplifier, 11 is a read amplifier, 12 is a main amplifier,
13 is a write amplifier, 14a and 14b are shift registers, 15 is a data output buffer, 16 is a data input buffer, 22 is a data storage unit, 23 is a data serial output unit, and 24 is a data serial input unit. is doing.

FIG. 2 shows an operation waveform diagram of one embodiment of the semiconductor memory device of the present invention. 2A is a clock signal CLK from the outside, FIGS. 2B to 2D are output signals of the high frequency conversion circuit 2a in the frequency conversion circuit 2, and FIG.
Is a clock signal after internally doubling the frequency of a clock signal CLK from the outside, (c) is quadrupled, (d) is quadrupled, and (e) is the second clock signal of (b). Internal control signal synchronized with falling edge of pulse, (f) is (c)
Internal control signal synchronized with the trailing edge of the fourth pulse of (d), (g) an internal control signal synchronized with the trailing edge of the 16th pulse of (d), and (h) of the data in the data output buffer 15. The output is shown respectively.

The read operation of the semiconductor memory device of this embodiment will be described with reference to FIGS. 1 and 2. First,
The row address is fetched from the row address buffer 4, the word line is selected through the row decoder 5 and the word line driver 6, and the data in the memory cell 9 is called up by the sense amplifier 10 and amplified. Next to this,
A column address is fetched from the column address buffer 7 and some of the sense amplifiers 10 operating through the column decoder 8 are selected.

In this embodiment, an external clock signal CLK as shown in FIG. 2 (a) is input to the frequency conversion circuit 2 of FIG. 1 and then this frequency conversion is performed as shown in FIG. 2 (b). The output signal shown in FIG. 2E, which is synchronized with the second pulse of the output signal of the circuit 2, is used as the control signal 17 for word line selection. Further, the output signal shown in (f) of FIG. 2 synchronized with the fourth pulse of the output signal of the frequency conversion circuit 2 shown in (c) of FIG. 2 is used as the operation control signal 18 of the sense amplifier 10. And (d) of FIG.
The output signal shown in (g) of FIG. 2 synchronized with the 16th pulse of the output signal of the frequency conversion circuit 2 shown in FIG. 2 is used as the control signal 19 for selecting the column address.

In the read operation, the data is called from the selected sense amplifier 10 to the read amplifier 11, the main amplifier 12, and the shift register 14a and transferred to the data output buffer 15. Among them, the operation control signal 20 of the read amplifier 11 and the main amplifier 12 is the output signal of the frequency conversion circuit 2 having the same period as the control signal for selecting the column address, and also controls the shift register 14a and the data output buffer 15. Uses a clock signal CLK from the outside.

In the write operation, the data taken in from the data input buffer 16 is taken out and written into the memory cell 9 from the selected sense amplifier 10 through the shift register 14b, the write amplifier 13 and the read amplifier 11. The control signal of each circuit in the write operation is the same as that in the read operation, and the data input buffer 16 and the shift register 14b are the clock signals CLK from the outside.
The operation control signal 20 is used for the write amplifier 13 and the read amplifier 11.

Thus, for example, by synchronizing the control signals of the respective circuits with the respective falling edges of the clock signals after frequency conversion, desired timing can be set between the respective control signals. Next, the configuration of the timing generation circuit 1 shown in FIG. 1 will be described. The timing generation circuit 1 includes a frequency conversion circuit 2 that newly generates a clock having a frequency higher or lower than this clock from a clock signal input from the outside, and each clock newly generated by this frequency conversion and having a different frequency. The output control circuit 3 determines the output timing between signals for controlling each circuit.

The operation of the timing generating circuit 1 will be described in detail below. FIG. 3 shows an operation waveform diagram of the input / output signals when the clock signal CLK from the outside is input to the frequency conversion circuit 2 as shown in FIG. FIG. 4 shows a specific example of the high frequency conversion circuit 2a of the frequency conversion circuit 2 of FIG. First, frequency conversion of the clock signal CLK from the outside is performed, and the clock signal CLK having a certain frequency (cycle T) as shown in FIG. 3A is input to the high frequency conversion circuit 2a as shown in FIG. By doing so, a clock signal having twice the frequency is created as shown in FIG. By passing the output signal of the high frequency conversion circuit 2a of FIG. 4 having twice the frequency of the clock signal CLK from the outside through the high frequency conversion circuit 2a shown in FIG. 4 again, as shown in FIG. External clock signal CLK
3 (d) by passing a clock signal having a frequency four times that of the external clock signal and a signal having a frequency four times the frequency of the external clock signal CLK to the high frequency conversion circuit 2a shown in FIG. External clock signal CL
It is possible to create a clock signal having a frequency of eight times K. In addition, when the clock signal CLK is input to the frequency divider that is the low frequency conversion circuit 2b, when the clock signal CLK is input to the frequency dividers shown in FIGS.
1/2 times the external clock signal CLK, 1
A clock signal having a low frequency such as / 4 times can be created.

Next, a delay time is set for the frequency-converted clock signal, and for example, the clock after frequency conversion by the frequency conversion circuit 2 has a delay time required by the frequency divider. Selected pulse number. In FIG. 5, as an example, a pulse number of 2 is selected in (a), a pulse number of 4 is selected in (b), and a pulse number of 8 is selected in (c) with respect to the clock signal of FIG. 3B. The waveform in the case is shown.

Next, as the setting of the delay time, the timing control of the output of the control signal of each circuit is carried out by using the clock signal 21 for which a certain pulse number is selected. For example, as an embodiment, a latch as shown in FIG. By inputting a control signal of a certain circuit in advance to the input terminal A of the output control circuit 3 configured by the circuit 3a and inputting the clock signal 21 having the delay time set to the input terminal B, the control signal of the circuit is changed. Determine the timing of output C.

FIG. 7 shows an operation waveform diagram of input / output signals when the latch circuit 3a of FIG. 6 is used as an embodiment of the output control circuit 3. For example, a case where a signal (a) having a cycle of 8T is input to the input terminal A and a clock signal 21 in which the timing of the pulse number 4 is selected by the clock of FIG. The rising edge of the output C is delayed by the period of the pulse of the input clock of the input terminal B, and the falling edge of the output signal is synchronized with the rising edge of the input signal from the outside.

FIG. 8 shows a circuit 3b which is a combination of two latch circuits 3a shown in FIG. 6 as another embodiment of the output control circuit 3. FIG. 9 shows the latch circuit 3a of FIG. 8 as an example.
6 is an operation waveform diagram in the case where is used as the output control circuit 3. For example, a clock having a low frequency is input to the input terminal D of FIG. 8 and a clock signal 21 having a delay time is input to the input terminals E and F. Here, as an example, the input terminal D
Is the period T of the clock signal CLK as shown in FIG.
The clock signal of which the frequency is reduced by the frequency conversion circuit 2 has a period of 8T, and the clock signal whose timing is the pulse number 2 of FIG. 3B is selected at the input terminal E as shown in FIG. 9B. 21 is input to the input terminal F, and the clock signal 2 whose timing is the pulse number 8 in FIG. 3D is selected as the delay time as shown in FIG. 9C.
When 1 is input, the rising edges of the output signals G and H are the clock signal 21 as shown in FIGS.
Will be output with the delay time set by.

Further, a latch circuit 3 as shown in FIG.
When c is used as the output control circuit 3, the pulse widths of the output signals I and J can be arbitrarily changed by the input signals K and L. Thus, in the timing generation circuit 1 of FIG. 2, the output signals 17, 1 of the output control circuit 3 are
Delay times of 8, 19, and 20 are set in synchronization with the clock signal CLK through the output signal 21 of the frequency conversion circuit 2.

As described above, in the above semiconductor memory device,
By using the frequency-converted clock signals 17, 18, 19, 20 as control signals of the circuit which has been controlled asynchronously with the external clock signal CLK, the clock signal CLK is controlled in synchronization with the clock signal CLK. The synchronization with the conventional circuit can be realized, and the timing setting between the control signals of each circuit becomes easy.

[0023]

According to the semiconductor memory device of the present invention, a frequency conversion circuit for converting the frequency of an external signal into a high frequency and a low frequency, and an output control for controlling the output of the internal signal by the output signal of the frequency conversion circuit. By providing a timing generation circuit composed of a circuit, it becomes possible to synchronize the control signal of each circuit with an external signal, and to control the control signal of each circuit without using a delay circuit that uses the time for charging / discharging the electric charge. The output timing can be set, and various timing settings without temperature dependency or power supply voltage dependency can be set.

[Brief description of drawings]

FIG. 1 is a conceptual diagram of an embodiment of a semiconductor memory device of the present invention.

FIG. 2 is an operation waveform diagram of the semiconductor memory device of FIG.

3A is an input waveform diagram of the external clock in FIG. 1, FIG. 3B is an output waveform diagram when the input waveform in FIG. 4A is passed through the high frequency conversion circuit 2a in FIG. 4, and FIG. Output waveform diagram when the output waveform of (b) is passed through the high frequency conversion circuit 2a of FIG. 4, (d) is an output waveform diagram when the output waveform of (c) is passed through the high frequency conversion circuit 2a of FIG. 1E is an output waveform diagram when the input waveform of FIG. 1A is passed through the low frequency conversion circuit 2b of FIG. 1. FIG. 6F is the output waveform diagram of FIG. It is an output waveform diagram at the time of passing.

4 is a circuit diagram of a specific example of a high frequency conversion circuit 2a of the frequency conversion circuit 2 in FIG.

5A is an output waveform diagram of the high frequency conversion circuit 2a when the pulse number 2 is selected in the waveform of FIG. 3B,
3B is an output waveform diagram when pulse number 4 is selected in the waveform of FIG. 3B, and FIG. 3C is an output waveform diagram when pulse number 8 is selected in the waveform of FIG. 3B. is there.

FIG. 6 is a circuit diagram of a specific example of the output control circuit 3 in FIG.

7A is a waveform diagram of an input signal to an input terminal A of the circuit of FIG. 6, FIG. 7B is a waveform diagram of an input signal of an input terminal B of the circuit of FIG. 6, and FIG. It is an output signal waveform diagram from the output terminal C of a circuit.

FIG. 8 is a circuit diagram of a specific example of the output control circuit 3 in FIG.

9A is a waveform diagram of an input signal to an input terminal D of the circuit of FIG. 8, FIG. 9B is a waveform diagram of an input signal to an input terminal E of the circuit of FIG. 8, and FIG. 9C is a circuit of FIG. Is a waveform diagram of an input signal to the input terminal F of FIG. 7, (d) is a waveform diagram of an output signal from the output terminal G of the circuit in FIG. 8, and (e) is a waveform diagram of an output signal from the output terminal H of the circuit in FIG. .

10 is a circuit diagram of a specific example of the output control circuit 3 in FIG.

FIG. 11 is a conceptual diagram of a conventional semiconductor memory device.

FIG. 12 is an operation waveform diagram of a conventional semiconductor memory device.

[Explanation of symbols]

 1 timing generation circuit 2 frequency conversion circuit 3 output control circuit 4 row address buffer 5 row decoder 6 word line driver 7 column address buffer 8 column decoder 9 memory cell array 10 sense amplifier 11 read amplifier 12 main amplifier 13 write amplifier 14 shift register 15 data Output buffer 16 Data input buffer 22 Data storage unit 23 Data serial output unit 24 Data serial input unit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Riichi Suzuki 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (2)

[Claims] 1. A frequency conversion circuit having a high frequency conversion circuit for converting the frequency of an external signal into a high frequency and a low frequency conversion circuit for converting the frequency of the external signal into a low frequency, and synchronizing with the output of this frequency conversion circuit. An output control circuit that generates a control signal, a data storage unit that reads or writes data in parallel according to the control signal, and a serial output unit that sequentially outputs the read data of the data storage unit in synchronization with the external signal, A semiconductor memory device comprising: a serial input unit that sequentially writes data from the outside into the data storage unit in synchronization with the external signal. 2. A high frequency conversion circuit outputs a first logical product and a logical sum which receive a first signal and a signal obtained by delaying the first signal, and an output of the first logical product. A first inverter that receives the input, a second logical product that receives the output of the first inverter and the output of the logical sum, and a second logical product that receives the output of the second logical product. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device comprises an inverter.