JPH01286056A - Interleave memory access device - Google Patents

Abstract

PURPOSE:To output data from a bank with delaying for a prescribed time and to make them fit for a pipe line control by executing the access of the address to the bank while evenly and symmetrically shifting it. CONSTITUTION:A memory access device possesses a decoder 9 to decide two low-order bits a1 and a0 of the address in order to obtain control signals E0 to E3 to hold and control the address for respective banks 1, 3, 5 and 7 of a memory, and latches 11, 13, 15 and 17 provided according to the respective banks in order to hold the address of the respective banks 1, 3, 5 and 7 according to a control signal from the decoder 9. The decoder 9 outputs the control signal by the two low-order bits a1 and a0 of the address. The address is supplied to latches 11 to 17 through an address bus 19 to the latches 11 to 17, and the data are outputted from the banks 1, 3, 5 and 7 through a data bus 21 to the latches 11 to 17.

Description

[Detailed Description of the Invention] I [Object of the Invention] (Field of Industrial Application) The present invention relates to an interleaved memory access system for accessing data such as microinstructions stored in a storage device having a plurality of banks. In particular, the present invention relates to an interleaved memory access device that accesses storage τ in a manner compatible with pipeline control.

(Prior Art) In recent years, an interleaved memory access method has been known as a method for shortening the access time in microprogram control in which microinstructions are accessed and executed from a control storage device that stores data such as microinstructions. ing. In this method, a control storage device is divided into a plurality of banks, a plurality of microinstructions are obtained in advance by reading them in parallel, and the microinstructions are selected based on the execution results.

FIG. 2 shows a schematic configuration diagram of a conventional memory access system using the interleaving method, and FIG. 1 shows a time chart of the conventional memory access processing in the device shown in FIG.

As shown in FIG. 2, in this conventional example, the memory 10
1 is divided into 4 banks (0, 1, 2, 3),
Addresses are sent to each memory 101 through an address bus 103.
The data from the memory 101 is supplied to the data bus 10 by a control signal from the output timing control section 105.
7. Addresses Ao, A+, A2, and A3 corresponding to the four banks are supplied to the memory 101 through the address bus 103 as shown in FIG. 1a. Here, when the first given address Ao is 4 bits, the upper two pits of the address Ao are common to the four banks, and the lower two bits specify the bank. and,
Other address A1. A2 and A3 each consist of two bits specifying a bank. Therefore, the actual access time given to each bank is non-uniform, as shown in FIG. 1b, and differs between the first address Ao and the following three addresses A*, A2, and A3.

Also, there is a time interval T between the first address AO and the next address A4 for bank 0.

was there. Therefore, data supplied from the memory 101 through the data bus 107 becomes as shown in FIG. 1C.

(Problem to be Solved by the Invention) In other words, since the length of each address is different and the access time given to each bank is uneven, the data bus 10
There are times when data is supplied through 7 and times when it is not, especially data Do.

Dl, D2, D3 and data D4, Ds, De
, Dl, there is a problem in that a loss time Ta occurs between the two.

The biggest problem is that the address Ao for bank 4
~Since the lengths of ~A3 are different and the output times of data from the memory 101 are uneven, when an attempt is made to operate a device that accesses these data by pipeline control, a disturbance occurs in the pipeline. However, if pipeline control is attempted, the disadvantage is that the control becomes extremely complex.

[Structure of the Invention] (Means for Solving the 12 Problems) A memory access device according to the present invention has been made in order to solve the problems of the above-mentioned prior art. It is equipped with a means for continuously supplying a plurality of addresses so as to have an access time, and a plurality of pieces of information corresponding to the above-mentioned addresses are successively output from the above-mentioned bank with a certain delay time with respect to the corresponding addresses. Features (Function) characterized in that: By providing the address supply means, the address access to the bank is performed while shifting uniformly and symmetrically. As a result, data is successively outputted from the bank with a delay corresponding to the number of books common to each bank with respect to the supplied address.

(Example) Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 5 shows a schematic configuration diagram of a memory access device embodying the present invention.

The first embodiment of this memory access device uses the lower two bits al and aQ of addresses Ao to A7 to obtain control signals Eo to E3 that control address retention for each bank 1.3 and 5.7 of the memory. A decoder 9 for decoding, and latches 11, 13.15 provided corresponding to each bank to hold the address Ao=Ay of each bank 1 to 7 according to the control signal Eo=E3 from the decoder 9.
゜17.

The decoder 9 inputs the lower two bits a1 and ao of the address.
According to the table shown in FIG. 4, the control signal Eo =
It is designed to output E3.

Further, the addresses Ao-Ay are supplied to the latches 11 to 17 via the address bus 19, and data is output from the memory bank via the data bus 21.

Next, the operation of access processing in the memory access device will be described with reference to FIGS. 3a to 3d.

First, addresses Ao-A7 of equal length are supplied to the latches 11-17 via the address bus 19, as shown in FIG. 3a. The lower two bits aloao of the address Ao=A7 are supplied to the decoder 9,
The decoder 9 receives control signals Eo~ according to the table shown in FIG.
The control signals Eo to E3 are supplied to the latches 11 to 17 as latch enable signals.

The waveform of the control signal Eo=E3 is as shown in FIG. 3b. That is, here, the lower two bits al and aQ of address AO are (0, 0), the lower two bits al and a of address A1 are (0°1), and address A2
The lower two bits aI of.

aO is (1, 0), and the lower two bits al and aQ of address A3 are (1, 1). When the address Ao is supplied to the latches 11 to 17 via the address bus 19, the decoder 9 supplies the latch 11 with an enable signal EO.

Therefore, address Ao is accessed to bank 1 via latch 11. Next, address A1 is latch 11
~17, the latch 13 is supplied from the decoder 9
A hay enable signal E1 is provided. Therefore, address A1 is supplied to bank 3 via latch 13.

When the address A2 is supplied to the latches 11 to 17, the decoder 9 supplies the latch 15 hay enable signal E2. Therefore, via the latch 15, the address A2
is supplied to bank 5. Then, when the address A3 is supplied to the latches 11 to 17, the latch 17 hay enable signal E3 is supplied. Therefore, address A3 is supplied to bank 7 via latch 17.

Then, when the address A4 is supplied to the latches 11 to 17, the decoder 9 again supplies the latch 11 hay enable signal Eo. Therefore, via the latch 11,
Address A4 is provided to bank 1. address A5~
The access operation of A7 is similar to the access operation of addresses A+ to A3 described above, so the explanation will be omitted.

Therefore, accesses of addresses Ao to A3 to banks 1 to 7 are performed while shifting uniformly and symmetrically as shown in FIG. 3C. That is, address Ao
=A3 is supplied to each bank 1 to 7 in parallel and with the same access time. And the third C
As a result of symmetrical access as shown in the figure, the data Do is transferred via the data bus 21 as shown in FIG.
~D7 is supplied. That is, data Do=Dy is
The supplied address Ao = A+ is delayed by the number of books common to banks 1 to 7, and is output uniformly and continuously, and the data Do is output as in the prior art.
No loss time occurs between =D3 and data D4 to D7.

Also, address Ao” for the above four banks 1 to 7
- Since the length of A7 is the same and the data from the memory is output with a certain delay time corresponding to the above address Ao=As, this memory access device is very compatible with vibe line control. can be adapted. In other words, since the relationship between the address and data of each bank is symmetrical, it can be said that vibration line control can be performed easily and at high speed.

Next, a second embodiment of the memory access device according to the present invention will be described with reference to FIGS. 6 and 7.

The second embodiment uses a dynamic random access memory as the memory, and the latch circuits 11 to 17 in the first embodiment are omitted.

As shown in FIG. 6, this memory access device has a RAS signal and a CAS signal for holding addresses;
A control waveform that supplies an output enable signal OE for outputting data to the data bus 29 and a WE double signal for writing modified data etc. from the data bus 29 as control signals to the DRAMs 21 to 27 divided into four banks. It has a generation section 31 and an address multiplexer 33 which supplies a multiplexed address signal (ma) to each bank.

Next, with reference to FIG. 7, the operation of the embodiment shown in FIG. 6 will be described.

In other words, dynamic random access memory has R
There is a function that can hold addresses in the memory element by AS (row address strobe) and CAS (column address strobe) signals, and thereby the function of the circuit of the first embodiment shown in Fig. 5 can be achieved with even fewer parts. I can do it.

The DRAM is given a signal multiplied by ma by multiplexing the address signal, which is held in the DRAM at the rising edge of the RAS and CAS signals. -〇E times signal output enable signal, for example, by -〇EO1, the data bus 29
The data indicated by (OR) above is output. In the second embodiment, a modify write operation is performed after the access mode, and the contents of data indicated by (OW) following (OR) are written into the memory of bank O by the -WEO signal. This second embodiment is an example corresponding to a storage device that holds images.

Also in this second embodiment, banks 21 to 27
Because they operate symmetrically, the output video data comes out continuously and smoothly.

FIG. 8 shows in more detail the control waveform generator 31 and address multiplexer 33 of the second embodiment of the memory access device described above.

Next, referring to FIG. 9, the data bus 29 shown in FIG.
A circuit connected to the DRAM for immediately modifying and writing data read from the DRAM will be described.

This combinational circuit is operated by a clock C shown in FIG. 7, and is configured to send data read from the DRAM back to the DRAM at high speed.

[Effects of the Invention] As explained above, according to the present invention, a means is provided for successively supplying a plurality of addresses to a plurality of banks of memory in parallel so as to have the same access time. Since multiple pieces of information corresponding to the above bank are successively output from the above bank with a certain delay time to the corresponding address, accesses to the above bank are uniformly and symmetrically shifted. It is done while As a result, data is successively outputted from the banks with a delay of the number of books common to the banks with respect to the supplied address, thereby making it possible to comply with vibe line control.

[Brief explanation of the drawing]

FIGS. 1A to 1C are operation timing diagrams of a conventional memory access device. FIG. 2 is a schematic configuration diagram of the conventional memory access device whose operation is shown in FIG. 1. 3a to 3d are operation timing diagrams of a memory access device implementing the present invention. FIG. 4 is a diagram showing the relationship between the lower two bits of an address and address latch control signals to each bank of the memory in the embodiment of the present invention. FIG. 5 is a schematic configuration diagram of a memory access device implementing the present invention. FIG. 6 is a schematic configuration diagram of a second embodiment of a memory access device according to the present invention. FIG. 7 is an operation timing diagram of the memory access device shown in FIG. 6. FIG. 8 is a more detailed circuit diagram of the control waveform generator and address multiplexer shown in FIG. 6. FIG. 9 is a combination circuit diagram connected to the data bus shown in FIG. 6. 1.3, 5.7...Memory bank 9...Decoder 11.13.15.17...Latch 19...Address bus 21...Data bus 21.23.25.27...・DRAM31...Control waveform generation section 33...Multiplexer

Claims (8)

[Claims] (1) An interleave memory access device for accessing information stored in a memory consisting of multiple banks in parallel, and multiple addresses are consecutively accessed in each bank of the memory in parallel and with the same access time. interleave memory, characterized in that a plurality of pieces of information corresponding to the address are successively output from the plurality of banks with a certain delay time with respect to the corresponding address. Access device. (2) The interleave memory access device according to claim 1, wherein the certain delay time is a number of books common to each bank. (3) The interleave memory access device according to claim 1, wherein the plurality of addresses have the same address length. (4) The interleaved memory access device according to claim 3, wherein the plurality of addresses are supplied with a delay of an address length of the addresses for each bank. (5) The address supply means decodes the lower two bits of the address in order to obtain a control signal for controlling address retention for each bank, and the address supply means performs decoding for each bank according to the control signal from the decoder. 2. The interleave memory access device according to claim 1, further comprising a latch provided corresponding to each bank to hold the address of the interleave memory access device. (6) The interleaved memory access device according to claim 5, wherein the latch control signal is an enable signal. (7) The interleaved memory access device according to claim 1, wherein the memory is comprised of a DRAM consisting of a plurality of banks. (8) The address supply means receives RAS and CAS signals for holding addresses, an output enable signal OE for outputting data to the data bus, and WE for writing modified data etc. from the data bus. 8. The control waveform generation section that supplies a control signal to the DRAM divided into four bunches as a control signal, and an address multiplexer that supplies a ma signal obtained by multiplexing the address signal to each bank. The interleaved memory access device described in .