JPS61202394A - Memory device - Google Patents

Abstract

PURPOSE:To attain high-speed continuous accesses with a memory device of large capacity by distributing 2-dimensionally the memory chips and giving control to selection of these chips so that the same chip does not receive the continuous accesses in a continuous access mode. CONSTITUTION:Each optional lower bit not higher bit of the row/column addresses is decoded for selection of a memory chip at a high-speed access control part 13. In a continuous access mode the chips are selected one by one. In this case, the limit of the holding time can be ignored for the control signal since the continuous accesses is avoided with the same chip. Then the control signal which are delayed in response to the highest timing with which the row-column address can be fetched are allocated orderly in both row and column directions for each memory chip. Thus the cycle time can be minimized.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a memory device suitable for high-speed processing of large amounts of data, such as image data mounted on an artificial satellite or acquired by a remote sensor. .

(Prior Art) Conventionally, this type of memory has been known as dynamic random access memory (hereinafter referred to as DRAM), which is lower in price and has a higher degree of integration than static random access memory (hereinafter referred to as 5-RAM). -RAM) was used.

FIG. 3 is an example of a conventional memory device.

In the figure, (11 is a memory section constituted by a D-RAM in which memory chips are arranged two-dimensionally in the row and column directions, (2) is data written to the memory section (1), (3)
is read data from memory section (1).

(4) is an address generator, (51, 16+ is an address generator (4) that divides a single address into upper bits and lower bits, and generates a row address corresponding to the upper bit and a column corresponding to the lower bit. (7) is a control signal generation unit that generates a memory control signal necessary when accessing the memory section (1); (8
1, (91, +l [I is a control signal generated from the control signal generating section, and is referred to as a 1-row address strobe signal (hereinafter referred to as RAS).
1 column address strobe signal (hereinafter referred to as CAS signal)
signal) and write enable signal (hereinafter referred to as W signal), (II) is the row address (5) and column address (
Send a control signal to any memory chip to which the address specified by the 1st row address (5) and column address (6) is assigned by decoding the upper arbitrary bits of 1st row address (5) and 1st row address (5) and A control unit controls the address of the lower bits of the column address (6) excluding upper arbitrary bits to be appropriately selected in one row and column and sent to the memory section. H is the selected row address or column address.

A conventional memory device is configured as described above.

For example, when performing continuous access, the address is incremented by 1 in the address generator (4), and at that time, the chip is selected using the high-order arbitrary bits, so access to a certain - column is performed within the same chip. Continuous, so the overall speed of the memory device is 5-R.
It is limited by the cycle time of D-RAM, which is slower than that of AM.

FIG. 4 shows a time chart of the RAS signal, CAS signal, address, and data when continuous access is performed in a conventional memory device. From this, it can be seen that the cycle time is four reference clocks.

[Problem that the invention seeks to solve]

In conventional memory devices such as those mentioned above, the cycle time of D-RAM is slow, so even if it has a large capacity, it cannot be used.For example, when processing a large amount of image data obtained by remote sensing in real time, There was a problem that the speed was insufficient.

This invention has been made to solve this problem, and improves the conventional memory address allocation method even when using RAM, which is slow in large-capacity memory devices.
The purpose is to enable high-speed continuous access by minimizing cycle time.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of the present invention,
(1) to (6) are exactly the same as the above conventional device, and (71 to aG correspond to each part in the above conventional device. (71 is the υ memory control signal as described above) In this case, it is a control signal generation section that generates several types of memory control signals that are delayed by a predetermined time so that the cycle time is minimized during continuous access, (8), +91 , 1(
I is a RAS signal, a CAS signal, and a W signal which are memory control signals outputted from the control signal generating section (7).

αj is a row address (5) and a column address so that each memory chip can be accessed in sequence without continuing to access the same chip by simply incrementing the memory address by 1 during continuous access. Decoding the lower arbitrary bits of (6) and thereby sending a control signal to any memory chip to which the specified address is assigned, and row address (5) and column address (
6) Set the address of the upper bits excluding the lower arbitrary bits to 1.
A high-speed access control section controls the row/column to be appropriately selected and sent to the memory section (I4 is the selected row address or column address).

In the memory device configured as described above, in order to select a memory chip, the high-speed access control unit (2) decodes the lower arbitrary bits, rather than the upper arbitrary bits, of each of the 9 row and column addresses. For example, if m memory chips are arranged in the row direction and n in the column direction, then 1
By decoding the lower log and m bit signals of the column address, it can be determined which row and which column of the memory chip should be accessed. In the case of continuous access, the selection results in one chip at a time. Also, in this case, since the same chip is not accessed continuously, the control signal hold time constraint can be ignored and 9 row/column addresses can be captured.The control signal is delayed according to the fastest timing for each memory chip.

The cycle time can be minimized by sequentially allocating both the row and column directions.

FIG. 2 shows an example of a time chart showing the relationship between several types of memory control signals, which are delayed by a predetermined period of time, and addresses and data so that several chips can be controlled independently at the same time. Although the RAS signal and the CAS signal are shown as memory control signals, the W signal is also delayed in the same way as the RAS signal and the CAS signal. The addresses RO and CO are a set of the row address and column address to be accessed first, and the same applies hereafter, and the data DO means the data accessed by RO and COK, and the same applies below. In this case 1
The fastest timing at which row/column addresses can be taken in is the standard clocked clock.

, it is possible to delay the clock one clock at a time. When the hold times of the RAS and CAS signals are taken into account, the periods of the RAS and CAS signals are determined, so it can be determined how many types of control signals should be prepared in relation to the period and the delay time. At the timing shown in this figure, signals of four types are generated. In this case, it can be seen that the cycle time is one reference clock. As can be seen by comparing the cycle time for continuous access in the conventional memory device shown in Figure 4, which was four reference clocks, the memory Access cycle time is reduced.

〔Effect of the invention〕

As explained above, the present invention arranges memory chips two-dimensionally in a row direction and a column direction in a large capacity memory device V, so that the chips are By controlling the selection and further preparing several kinds of control signals, a memory chain capable of large capacity and high-speed continuous access can be realized using highly integrated and low-cost RAM. Therefore, it is effective for processing two-dimensional data such as a large amount of image data acquired by remote sensors mounted on nine artificial satellites. .

[Brief explanation of drawings]

FIG. 1 is a block diagram of a memory device showing an embodiment of the present invention, FIG. 2 is a time chart of memory control signals (RAS, CAS signals), addresses and data, and FIG. The figure is a block diagram of a conventional memory device, and FIG. 4 is a memory control signal (
2 is a time chart of RAS, CAS signals), addresses, and data. In the figure, (1) is the memory section, (2) is the write data, (3) is the read data, (4) is the address generator, (5) is the row address from the address generator, and (6) is the column from the address generator. address,(
7) is a control signal generation unit, (8) is a row address enable signal IRAs signal), (91 is a column address enable signal (CAS signal), aI is a write enable signal (W signal 1, all is a control unit, az is a row The address of the lower bits of the address excluding the upper arbitrary bits, or the address of the lower bits of the column address excluding the upper arbitrary bits. This is the address of the bit address or the upper bit of the column address excluding the arbitrary bit f.The same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] A memory section consisting of a dynamic random access memory in which memory chips are arranged two-dimensionally in the row and column directions, an address generator that can independently control the row and column addresses, and a number delayed by a predetermined time. When the memory section is successively accessed by inputting a control signal generation section that generates a control signal of the type, the address generator, and the output of the control signal generation section, the control signal can be accessed by simply increasing the memory address by one. A memory device comprising: a high-speed access control section that functions to apply signals to a plurality of chips in a memory section in a predetermined order.