JPH0528031A - Data processor - Google Patents

Abstract

PURPOSE:To obtain the data processor capable of production at a low cost by providing a control means performing plural access operations for a storage means according to one access operation by means of an access means. CONSTITUTION:A storage means 1 is composed of a dynamic RAM with a 4-bit data bus, and an access means 2 is composed of a CPU or the like with a 8-bit data bus. A control means 3 is composed of an access control circuit 3a performing the access control specifying data reading and writing and the chip select to the storage means 1, an address control circuit 3b outputting the address signal from the access means 2 after converted into an address signal for storage means 1, and a data control circuit 3c performing the data transmission control between the storage means 1 and the access means 2. Thus, it can be written in the storage device 1 of a 4-bit data bus through two access operations by the control means 3 according to one access operation by the access means 2 with the 8-bit data bus.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device.

[0002]

2. Description of the Related Art Conventionally, for example, in the case of a data processing device which performs data processing using an 8-bit microcomputer as an access means, 8-bit SRA having the same number of bits as the microcomputer as a data storage means.
It is common to use M (static RAM).
As described above, the SRAM having the same number of bits as the access means is used to read and write data by one access operation.

[0003]

The SRAM used in the above conventional device is more expensive than other storage means of the same capacity. For example, the price is about three times that of a DRAM (dynamic RAM) having the same capacity. Therefore,
Therefore, the cost of the device must be increased.

An object of the present invention is to provide a data processing device which can be manufactured at low cost.

[0005]

SUMMARY OF THE INVENTION The present invention has a storage means for storing data, which has a data bus having an n-bit width, and N
(Where N> n) a data bus having a bit width, and access means for accessing the storage means, and a plurality of access operations for the storage means in response to one access operation by the access means. By providing a control means for reading and / or writing data to and from the storage means,
The above problems are solved.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, reference numeral 1 is a storage means for storing data, and in this example, a D having a 4-bit data bus.
RAM. Reference numeral 2 is an access means including a CPU for controlling reading and writing of data from the storage means 1 and having an 8-bit data bus. 3a is a chip select for the storage means 1, data read / write designation, RAS (row address strobe) / CA
An access control circuit for performing access control such as S (column address strobe) designation and the like, 3b is access means 2
The address control circuit 3c for converting the address signal from the storage unit 1 into the address signal for the storage unit 1 and outputting the converted signal is a data control circuit for controlling the data transmission between the storage unit 1 and the access unit 2. 3 are configured.

Data read and write operations will be described below with reference to the timing chart of FIG.

First, when reading data from the storage means 1, a 16-bit address signal is sent from the access means 2 to the address bus A as shown in FIG. Also,
In the control bus B, as shown in FIG. 2B, the chip select signal is set to "0", thereby making the storage means 1 accessible. Further, as shown in FIG. 2C, the read / write designation signal is set to "1", and thereby the data read is designated.

The address signal is the address control circuit 3b.
2e, the row address signal and the column address signal are distributed as shown by e in FIG. Further, the RAS signal is output to the control bus B as shown by f in FIG. 2 and the CAS signal as shown by g in FIG. A row address and a column address are designated by the signal. Further, in the control bus B, the write signal becomes "1", as shown by h in FIG.

In response to the data read access from the access means 2 as described above, the 4-bit upper data H of the first designated address is transferred to the address bus C from the storage means 1 as shown by i in FIG. Sent out. This data H is latched in the data control circuit 3c as indicated by j in FIG. Subsequently, as indicated by i in FIG. 2, 4-bit lower-order data L of the address designated for the second time by the address control circuit 3b is transmitted to the address bus C. The access means 2 first receives the upper 4-bit data H, then the lower 4-bit data L, and receives both as 8-bit data, as shown in FIG.

As described above, the 4-bit storage means 1
The data is read from and is received by the 8-bit access unit 2.

Next, when writing data to the storage means 1, a 16-bit address signal is sent from the access means 2 to the address bus A, as indicated by a'in FIG. Further, in the control bus B, the chip select signal is set to "0", as shown by b'in FIG. 2, whereby the storage means 1 is made accessible. Further, as indicated by c'in FIG. 2, the read / write designation signal is set to "0" for a predetermined period, and data writing is designated during this period. The above-mentioned address signal is controlled by the address control circuit 3b so that
As shown by ', the row address signal and the column address signal are distributed, and the addressing of the storage means 1 is performed twice. A RAS signal as indicated by f ′ in FIG. 2 and a CAS signal as indicated by g ′ in FIG. 2 are output to the control bus B, and the distributed row address signal and the row address signal according to the generation timing of the RAS and CAS signals. A row address and a column address are designated by the column address signal. 8-bit data is sent to the data bus C from the access means 2 as shown by d'in FIG. In response to the 8-bit data, the data control circuit 3c first sends the upper 4-bit data to the storage means 1 as shown by i'in FIG. After that, the lower 4-bit data L is sent to the storage means 1. The data sent from the data control circuit 3c is written in the control bus B to the respective designated addresses of the storage means 1 when the write signal becomes "0", as indicated by h'in FIG.

As described above, in response to one access operation by the access means 2 having an 8-bit data bus, four access operations are performed by the control means 3 twice.
Data is written to the storage means 1 having a bit data bus.

Although the data bus of the access means 2 is 8 bits and the data bus of the storage means 1 is 4 bits in the above embodiment, for example, the data bus of the access means 2 is 16 bits and the data bus of the storage means 1 is 16 bits. The number of bits may be set arbitrarily, such as 8 bits for the data bus.

In the above embodiment, the memory means 1 is accessed by the two access operations by the control means 3 in response to the one access operation by the access means 2.
The number of accesses by the control means 3 may be set to an appropriate number of times according to the relationship between the number of bits of the data bus of the access means 2 and the storage means 1.

Further, in the above embodiment, the storage means 1
Although a DRAM is used as the above, the present invention is not limited to this, and for example, an EP
A ROM, an EEPROM, a read-only PROM, or the like may be used.

[0018]

According to the present invention, an inexpensive storage means such as a DRAM having a bit number smaller than that of the access means can be used, so that the cost of the device can be reduced accordingly. it can.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart for explaining a data read / write operation.

[Explanation of symbols]

 1 Storage Means 2 Access Means 3 Control Means

Claims (1)

Claim: What is claimed is: 1. A storage device having an n-bit width data bus for storing data, and a data bus having an N (where N> n) bit width. Access means for accessing the storage means and a plurality of access operations for the storage means in response to one access operation by the access means, thereby reading and / or reading data from the storage means.
Alternatively, a data processing device comprising: a control unit for performing writing.