JPH0556598B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a memory control method, and particularly to a memory control method.
The present invention relates to a memory access method that can read or write memory data without inserting a wait cycle into a CPU cycle.

[Conventional technology]

Recently, memory has been integrated on a large scale, with tens to hundreds of kilobits being integrated into a single chip. Address multiplexing techniques are used in large scale integrated memories, especially dynamic RAM, to reduce the number of pins. This is a technology that superimposes two pieces of address information on one internal address point in a time-division manner. Two timing signals, a row address selection signal (RAS) and a column address selection signal (CAS), are input from the outside. This technology latches the address signal for the row selection decoder at RAS timing, latches the address signal for the column selection decoder at CAS timing, and reads or writes any one bit on an array cell.

Conventionally, when a CPU accesses this type of RAM using a high-speed clock, for example, as shown in Figure 2, in one bus cycle with T ₁ , T ₂ , T ₃ , and T ₄ as machine cycles, a wait cycle is generated.
Memory could not be accessed without inserting one or more T〓 into a bus cycle.

In other words, with the conventional method, when reading memory, a memory request (MRQ) from the CPU is
A signal is output at the rising edge of the next machine cycle T ₂ after the signal was output, and at the falling edge of T ₂ , the address switching signal (RCG) is raised to convert the address on the address line from a row address to a column address, and the next The signal is activated to logic 0 at the rising edge of _T3 . Since the data is actually output from the memory after a certain period of time after this signal is output, the CPU cannot read the data with no wait, so as shown in the time chart in Figure 2, cycle
Insert T〓 between T ₃ and T ₄ and wait more than 1 wait, CPU
I had to wait. At this time,
If you send the signal a little earlier, it will be possible to read the memory, but if you try to write write data that was determined in the middle of T ₃ at the falling edge of the signal during memory write, the data will remain undetermined. There was a drawback that writing was required, which caused problems in operation, but in the end, in order to be able to read and write the memory,
The CAS signal was generated at the rising edge of _T3 , and one or more waits had to be inserted into the CPU cycle. Otherwise, in order to access memory without waiting using the conventional method, the frequency of the CPU clock had to be lowered.

[Problem that the invention seeks to solve]

Therefore, even if even one wait is inserted into a CPU cycle, there is a problem in that in computers and the like where memory access is the majority, making the CPU wait is extremely inefficient.

The present invention eliminates these conventional drawbacks and
RAS signal at the beginning regardless of memory request
We provide a highly efficient memory access method that does not insert wait cycles T into bus cycles by taking advantage of the fact that memory access is not performed unless a signal is output even if it is output during _one T cycle. The purpose is to

[Means for solving problems]

According to the present invention, means for generating a row address signal independently of a memory access request signal in synchronization with the first machine cycle of a CPU cycle;
When accessing memory, the memory access request signal output from the CPU is used as a trigger to generate a column address designation signal for memory read when reading memory, and a column address designation signal for memory read that is delayed by a certain period of time when writing memory. Means for generating a column addressing signal for memory write, inputting the row addressing signal and column addressing signal, and accessing by the row address and column address input corresponding to each of the designated signals. The present invention provides a memory access method comprising a memory.

[Operation] In the present invention, the first machine cycle T ₁
Address load enable () output in
Using the signal as a trigger, the signal is given to the DRAM regardless of the memory request, and the memory request signal from the CPU is used as the trigger to read the memory.
A CAS signal and a memory write signal generated by delaying the CAS signal are provided to the DRAM.

〔Example〕

Next, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1a follows the memory access method of the present invention.
FIG. 1b is a block diagram of a DRAM control circuit.
shows the timing chart of each part.

The CLK signal in Figure 1b is the basic clock of the system, and one bus cycle consists of four machine cycles: T ₁ , T ₂ , T ₃ , and T ₄ , and the ALE signal is
Address load enable signal, CPU
This is an enable signal for latching the address information output to the address line in the _T1 cycle into the address latch circuit. Therefore, this
The ALE signal goes low in the first machine cycle of every bus cycle, as shown in Figure 1b.

When a signal is input to the signal generator 10 that generates a signal indicating row addressing, the signal 101 is set to a low level from the rising edge of the signal, regardless of whether the cycle is a memory access cycle or not. Output. At this time, the address is latched in the address latch circuit, so the address connected to its output is enabled, so when the signal is output, the DRAM in Figure 1a
On the address line AD input to the control circuit, the first
The row address becomes valid as shown in Figure b. Since this signal 101 is input to the delay circuit 11, the RCG signal shown in FIG.
It is applied to the address switching circuit 12.
Therefore, the address on AD was a row address at the falling edge of the signal, but
From the rising edge of the RCG signal, it switches to the column address. Therefore, the address switching circuit 12
The DRAM 13 inputs the output as the address and inputs the signal to the row designation terminal R.
From the fall of the RAS signal, it means that the row address has already been given, and the row address is latched inside the chip. but,
DRAM output DT to which CAS signal is not given
No output signal is output yet.

The output of this address switching signal RCG is
It is also input to the pulse width control circuit 14 which is fed back to the RAS signal generation circuit 10.
At this time, after a certain period of time, usually after the signal is output at the rising edge of _T1 and until the rising edge of _T3 , the signal is automatically cleared and becomes high level. However, in direct memory access (DMA) mode, external I/O
If the WAIT request signal WAIT from WAIT is input to the WAIT control circuit 15, clearing of the signal by the pulse width control circuit 14 is also temporarily delayed.

In this way, in the present invention, the signal is automatically output using the signal as a trigger regardless of the memory request, but the signal indicating column address designation is generated in consideration of the wait request from external I/0 in DMA. A memory request signal (MRQ) is input to the circuit 16 during a memory access cycle in which the CPU accesses the DRAM, and then is output from the signal generating circuit 16. When reading the memory when the MR signal is at a high level, the selection circuit 17 selects the memory read signal R.
That is, the signal generated by the signal generation circuit 16
The CAS signal 160 is output as is and applied to the column designation terminal C of the DRAM. On the other hand, during memory write when the MW signal is at a high level, the memory write signal W is the signal 1.
60 delayed by a certain period of time in the delay circuit 18.
The CAS signal selection circuit 17 selects, forms, and outputs the signal. Therefore, as shown in Figure 1b, the next machine cycle (T ₂ ) when the MRQ signal goes high
At the rise of , ・R falls, and a little later, ・W falls.

At the time of memory read, when ・R falls, the active low level is output via the selection circuit 17.
It is applied to the column designation terminal C of the DRAM 13.
At this time, since the column address has already been given to the address terminal A of the DRAM 13 by the address switching circuit 12, in the DRAM 13, one of the row contents latched to the internal output by the row address is transferred to the column address. It is selected accordingly. And data output DT of DRAM13
The contents of the address specified by the address consisting of the total bits of the row address and column address are output. That is, as shown in Figure 1b, a delay time ΔR is required from when the R signal falls until the data (VALID DATA) becomes valid at the data output DT.
The fall time of the CAS/R signal is the rise of _T2 cycles, and even if there is a delay time,
The data output from DRAM 13 is valid at least at the end of the _T3 cycle. Therefore, at the falling edge of T ₃ cycles, the CPU
The read data, which is the output of the DRAM 13, can be latched into the data input register of , and the waiting cycle of 〓 as in the conventional case is not necessary.

On the other hand, at the time of memory write, when W falls, the input DT of DRAM13 is
Since the input data from the CPU is valid, the data on the input DT can be controlled to be written at the falling edge of W, as shown in FIG. 1b. In this case, of course, the T〓 wait cycle is not necessary.

Furthermore, if the external I/0 wait request signal WAIT in DMA is input to the wait control circuit 15 at the time of memory read or memory write, the signal generation circuit 16 generates a signal at the time of DMAI/0 write, that is, memory read. It is sufficient to output the signal as it is, and at the time of DMAI/0 read, that is, memory write, the signal generation circuit 16 may temporarily wait before outputting the signal.

As described above, the present invention outputs a signal as a trigger regardless of whether a memory request (MRQ) is input,
DMA automatically clears wait requests from external I/0, generates CAS signals only after a memory request is issued, and separates CAS signals for memory writes and memory reads. The delay element 11 is used to generate a switching signal for the row/column address, and the delay element 18 is used to generate a signal for memory write.
It is characterized by generating CAS/W signals, T ₁ , T ₂ ,
In a bus cycle without T〓 consisting of T ₃ and T ₄
Enabled read/write operations for DRAM13. And overall, the timing is CPU
It is also unique in that it is asynchronous with the clock and uses delay elements to create timing.

〔Effect of the invention〕

The present invention eliminates CPU wait cycles by outputting signals in synchronization with the first machine cycle regardless of memory requests and activating the signals when memory is requested. This has the effect of allowing high-speed read and write operations and eliminating the need for a circuit that inserts a wait cycle for memory access into the CPU cycle.

[Brief explanation of the drawing]

FIG. 1a shows a memory access control circuit of the present invention;
FIG. 1b is a timing chart showing the timing of each part of an embodiment of the memory access control circuit of the present invention, and FIG. 2 is a timing chart of a conventional memory access control circuit. 10...Signal generation section, 11, 18...Delay circuit, 12...Address switching circuit, 13...
...DRAM, 14...Pulse width control circuit, 1
5...WAIT control circuit, 16...signal generation circuit, 17...selection circuit.

Claims (1)

[Claims] 1 A means for generating a row address signal independently of a memory access request signal in synchronization with the first machine cycle of a CPU cycle, and a means for generating a row address signal independently of a memory access request signal at the time of memory access, using the memory access request signal output from the CPU as a trigger at the time of memory read. Column addressing signal for memory read,
At the time of memory write, means for generating a column address designation signal for memory write delayed by a certain period of time from the column address designation signal for memory read; A memory access method comprising a memory accessed by correspondingly input row addresses and column addresses.