JPH03286234A - Memory control device - Google Patents

Memory control device

Info

Publication number
JPH03286234A
JPH03286234A JP8651090A JP8651090A JPH03286234A JP H03286234 A JPH03286234 A JP H03286234A JP 8651090 A JP8651090 A JP 8651090A JP 8651090 A JP8651090 A JP 8651090A JP H03286234 A JPH03286234 A JP H03286234A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
access
control
device
turned
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8651090A
Inventor
Riichi Suzuki
Original Assignee
Matsushita Electric Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing
    • Y02D10/10Reducing energy consumption at the single machine level, e.g. processors, personal computers, peripherals or power supply
    • Y02D10/13Access, addressing or allocation within memory systems or architectures, e.g. to reduce power consumption or heat production or to increase battery life

Abstract

PURPOSE: To realize high-speed access, and simultaneously, to reduce power consumption by accessing a storage device divided into plural blocks in parallel.
CONSTITUTION: When a bank A is read-accessed, RASA in a memory access control signal is turned into a 'Low' level by an access timing control device 100, and one page in a DRAM group 101 to 116 to constitute the bank A is selected. When the access timing control circuit 100 to access each word in the selected page controls the control signals CASA00-3, CASA10-3, CASA20-3, CASA30-3 of an address group, these are turned into 'Low' level at a time, and word data different from each other are read at a time by the DRAM group 101 to 116. At that time, if a central processing unit designated previously an instruction fetch cycle, a latch select signal 23 from the device 100 is turned into 'High' level, and if it designated previously a data fetch cycle, the signal 23 is turned into 'Low' level.
COPYRIGHT: (C)1991,JPO&Japio
JP8651090A 1990-03-30 1990-03-30 Memory control device Pending JPH03286234A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8651090A JPH03286234A (en) 1990-03-30 1990-03-30 Memory control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8651090A JPH03286234A (en) 1990-03-30 1990-03-30 Memory control device

Publications (1)

Publication Number Publication Date
JPH03286234A true true JPH03286234A (en) 1991-12-17

Family

ID=13888979

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8651090A Pending JPH03286234A (en) 1990-03-30 1990-03-30 Memory control device

Country Status (1)

Country Link
JP (1) JPH03286234A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8868829B2 (en) 2006-07-31 2014-10-21 Google Inc. Memory circuit system and method
US8949519B2 (en) 2005-06-24 2015-02-03 Google Inc. Simulating a memory circuit
US8972673B2 (en) 2006-07-31 2015-03-03 Google Inc. Power management of memory circuits by virtual memory simulation
US8977806B1 (en) 2006-10-05 2015-03-10 Google Inc. Hybrid memory module
US9047976B2 (en) 2006-07-31 2015-06-02 Google Inc. Combined signal delay and power saving for use with a plurality of memory circuits
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US9542353B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US8949519B2 (en) 2005-06-24 2015-02-03 Google Inc. Simulating a memory circuit
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US9542352B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
US9727458B2 (en) 2006-02-09 2017-08-08 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
US9542353B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US8868829B2 (en) 2006-07-31 2014-10-21 Google Inc. Memory circuit system and method
US8972673B2 (en) 2006-07-31 2015-03-03 Google Inc. Power management of memory circuits by virtual memory simulation
US9047976B2 (en) 2006-07-31 2015-06-02 Google Inc. Combined signal delay and power saving for use with a plurality of memory circuits
US8977806B1 (en) 2006-10-05 2015-03-10 Google Inc. Hybrid memory module

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