JPH03286234A - Memory control device - Google Patents

Abstract

PURPOSE:To realize high-speed access, and simultaneously, to reduce power consumption by accessing a storage device divided into plural blocks in parallel. CONSTITUTION:When a bank A is read-accessed, RASA in a memory access control signal is turned into a 'Low' level by an access timing control device 100, and one page in a DRAM group 101 to 116 to constitute the bank A is selected. When the access timing control circuit 100 to access each word in the selected page controls the control signals CASA00-3, CASA10-3, CASA20-3, CASA30-3 of an address group, these are turned into 'Low' level at a time, and word data different from each other are read at a time by the DRAM group 101 to 116. At that time, if a central processing unit designated previously an instruction fetch cycle, a latch select signal 23 from the device 100 is turned into 'High' level, and if it designated previously a data fetch cycle, the signal 23 is turned into 'Low' level.

Description

[Detailed Description of the Invention] Industrial Field of Application This invention C relates to a memory control device that divides a storage device into a plurality of blocks and accesses them in parallel to speed up access to the storage device. This relates to a memory control device that reduces power consumption.Conventional technologyFor example, Japanese Patent Application Laid-Open No. 1-222
FIG. 4 shows the countries in which this conventional memory control device is constructed, and FIG. 5 shows a time chart of the conventional memory access processing in the device shown in FIG. 4.

As shown in FIG. 4, 200 inputs an address signal from the central controller and a control signal from the central controller.
201 to 208 are access timing control devices that output multiplexed address signals, memory access control signals, data transmission direction control signals, and wait control signals to the central control device. inputting the multiplexed address signal and the memory access control signal from the access timing control device 200 to input and output data;
Each of them is a group of dynamic random access memories (hereinafter referred to as DRAMs) with a length of 8 bits, and has a page mode access method.Also, 201 to 204 are in bank O, and 205 to 208 are in bank 1.
201, 202, 205, 206 constitute an even word address group, 203, 204, 207, 208 constitute an odd word address group & 209 inputs a data transmission direction control signal from the access timing control device 200 L DRAM 201~ 208 and the data bus from the central control unit.

In the conventional memory control device configured as described above (
If bank 0 is accessed, RASO goes to "Low'" level as shown in Figure 5 (b), and from then on, the power that causes access to outside the currently valid page is The force that causes the RAS pulse timeout specified by the DRAM specifications\or bank 0
"LOW" until memory refresh is performed in
Level is maintained and access to each word (5th
As shown in figure (C) and figure 5 (d), CAS
This is done by controlling OE and CASO○, and even word address groups 201 and 20 within the currently valid page.
2 and odd word address groups 203 and 204, CAS precharging is interleaved and high-speed access is achieved. Similarly, as shown in Figure 5 (e), RASI goes to "Low" level, and after that, the power that causes access outside the currently valid page is specified by the DRAM specifications. The LOW level is maintained until the memory in bank 1 is refreshed.

Access to each word (see (f) in Figure 5 and
As shown in (g) of the figure, this is done by controlling CASIF, CASlo, and within the currently valid page,
When accesses are performed alternately between the even word address group 205, 206 and the odd word address group 207, 208, CAS precharging is interleaved and high-speed access is achieved. In Figure 5 (
b) and as shown in FIG. 5(e), RASO and
Even if RASI precharging is interleaved and high-speed access is achieved, the problem that the invention attempts to solve is that, however, in the above configuration, the DRAM selected by the selection signal (RASOlRASI) of each bank.
i;L Force that causes access outside the currently valid page＼ RAS specified in the DRAM specifications
The pulse timeout occurs because the memory in the selected bank remains activated until the memory is refreshed. 1. In view of these points, the present invention aims to provide a memory control device that speeds up access to a storage device by accessing a storage device divided into a plurality of blocks in parallel, and reduces power consumption. do.

Means for Solving the Problems The present invention provides a storage device consisting of a plurality of blocks, an access timing for inputting an address signal to each block of the storage device, and an access timing for inputting an access signal to each block of the storage device in parallel. The present invention is also applicable to a memory control device comprising a control device and a latch for holding data selected by the address signal translation and access signal and output from the storage device. The access timing control unit simultaneously reads from the storage device the address that was specified and the word of the address that precedes that address and holds it in the latch. The access timing controller also negates the access signal that activates the storage device while the previous word is sequentially output to the data bus to reduce power consumption. When accessing the address areas alternately, the word of the address preceding the address designated by the central controller in each address area is simultaneously read in advance and held in each set of latches. , the frequency of direct access to the storage device is reduced, and the access signal that activates the storage device is negated during that time, thereby further reducing power consumption. Embodiment FIG. 1 shows a memory in an embodiment of the present invention. Fig. 2 shows a block diagram of the control device; Table C shows a time chart of memory read access processing in the memory control device shown in Fig. 1; Fig. 3 shows a block diagram of the memory control device shown in Fig. 1; A time chart of write access processing is shown. In Fig. 1, 1 is an address signal from the central control unit, 2 is a control signal from the central control unit, and 3 is a multiplexed address signal q4 to q14 is a memory access control signal. 15 to 22 are latch output control signals 23
is a latch selection signal 24 is a data transmission direction control signal
25 is a weight control signal to the central controller.10
0 inputs address signal 1 from the central control device and control signal 2 from the central control device; address signal 3 input to the storage device; memory access control signals 4 to 14;
This is an access timing control device that outputs latch output control signals 15 to 22, a latch selection signal 23, a data transmission direction control signal 24, and a wait control signal 25 to the central control device. 101-132ζ Friend: 8-bit long DRA that inputs address signal 3 and memory access control signals 4-14 and performs data input/output.
Group M may have a page mode access method.
, 101 to 116 constitute bank A, and 117 to 132 constitute bank B. In addition, 101 to 104, 1
17 to 120 are the O-th word address group, 105 to 1
08, 121 to 124 are the first word address group, 1
09 to 112 and 125 to 128 constitute the second word address group, and 113 to 116 and 129 to 132 constitute the third word address group. Also, 8 RASA of the memory access control signals 4 to 14 is the RAS of bank A. confidence
RASB is Bank B's RA S 4M momme CASAOO
~3 is CA11u of the O-th word address group of bank A
CASAIO~3 is the CAS 4W spider of the first word address group of bank A CASA20~3 is the CAS signal-IL of the second word address group of bank A CASA30
~3 is the CAS signal uc of the third word address group of bank A
AsBOo~3 is C of the Oth word address group of bank B
AS signal u CASBIO~3 is the CAS signal u of the first word address group of bank B CAS820~3 is the CAS signal of the second word address group of bank B CASB30
~3 is the CAS signal of the third word address group of bank B,
WE is a memory write enable signal.

90-93 (latch selection signal 23, memory write enable signal 14, memory access control signal 5-8
, 10-13 and latch enable signal 29~
It is also possible to use a three-man NAND that outputs 32 94 to 97 ζ. Three-man power inputs the latch selection signal 23, memory write enable signal 14, and latch output control signals 15 to 22, and outputs the latch output enable signals 33 to 48. N
In the AND mode, 133 to 196 are latches that input the latch enable signals 29 to 32, latch output enable signals 33 to 48, and the output data of the storage device, and hold the data output by the storage device. It is also an instruction latch that holds instruction information stored in a storage device.
165 to 196 are data latches that hold data information stored in the storage device, and 197 is a DRAM that inputs the data transmission direction control signal 24.
This is a switch that connects the data bus from the central control unit to the output data path of the latch during read access to the L DRAM, and connects the data bus from the central control unit to the input data path to the DRAM during write access to the L DRAM.

The operation of the memory control device of this embodiment configured as described above will be explained below. When a read access is made to bank A, jlG
2(b) As shown in the figure, the access timing control device 100 sets RASA to the "LOW" level and selects one page from the DRAM group 101 to 116 forming bank A. Access to each word within the selected page is
The access timing control device 100 is CASAOO~3
, CASA 10-3, CASA20-3, CASA3
Control 0 to 3 L\ 2nd (C) Block 2nd (
d) as shown in Figures 2(e) and 2(f),
CASAOO~3, CASA 10~3, CASA20
~3. Simultaneously set CASA30~3 to "Low level" and hydrate the word at the address specified by the address signal l. Four words of data that differ from each other only in the LS82 bit of the word address are transferred to DRAM groups 101~116.
If the central controller specifies the instruction fetch cycle in the control signal 2 from the central controller, the latch selection signal 23 will be set to "High".
If the central control unit specifies a data fetch cycle in the control signal 2 from the central control unit, the latch selection signal 23 is set to the “Low” level.

As a result, during the instruction fetch cycle, 3-man NA
Output 29 of ND90 is asserted and 3-person NAND9
1 is negated, and the DRAM group 101-1
4 words read simultaneously from 16 are instruction latch 1
33 to 148, and during a data fetch cycle (output 30 of the three-way NAND91 is asserted, output 29 of the three-way NAND90 is negated, and the four words simultaneously read from the DRAM11 to 116 are held in the data latch). Even if the latch output control signals 15 to 18 are held at 1.65 to 180, the second (g
) is 2nd (h) @ 2nd (1) figure and 2nd
(j) Output as shown in the figure As a result, during the instruction fetch cycle (outputs 33 to 3 of the 3-man NAND94)
6 is interleaved and asserted, and only the words at the address specified by the central controller are interleaved and output to the data bus. Similarly, during the data fetch cycle, 3-person NAN
The outputs 41 to 44 of D95 are interleaved and asserted to the data bus from the Oth word to the third word held in the data latches 165 to 180.Only the word at the address specified by the central controller is interleaved and sent to the data bus. Output. In subsequent read access,
When the bits other than the LS82 bit of address signal 1 differ from the contents of the address used in the previous read access, four words are simultaneously read from the k DRAM group. 11RAsA, CASAOO~3, CASA 10~3 if the address content is the same as the one made
, CASA20-3, and CASA30-3 are negated.

A read access to bank B is similar to a read access to bank A.

Immediately, as shown in FIG. 2(k), the access timing control device 100 sets RASB to 'Low' level and selects one page among the DRAMWs 17 to 132 constituting bank B. Access to each word is performed by the access timing control device 100 using CASBOO~3, CASB10~3, CASB20.
~3, Control CASB30~3 L\ 2nd
(1) @ 2nd (m) is 2nd (n) and 2nd
(0) As shown in the figure, CASBOO~3, CASBIO
~3, CASB20~3, CASB30~3 at the same time”
4 words of data are simultaneously read from the DRAM groups 117 to 132 as "Low" level. If the central control unit specifies the data fetch cycle in the control signal 2 from the central control unit, the latch selection signal 23 is set to the “Low” level.
The result of this level and melon is i during the instruction fetch cycle.
t Output 31 of the 3-power NAND92 is asserted.
The output 32 of the three-man NAND93 is negated, and the DR
The four words read simultaneously from the AM groups 117 to 132 are held in the instruction latches 149 to 164, and during the data fetch cycle, the output 32 of the 3-man NAND 93 is asserted, and the output 31 of the 3-man NAND 92 is asserted.
are negated and the four words simultaneously read from the DRAM groups 117 to 132 are stored in the data latches 181 to 19.
Even if held at 6, latch output control signals 19 to 22
(2nd (p) In 2nd (q) @ output as shown in Figures 2(r) and 2(s). As a result, during the instruction fetch cycle, (37~ 40 is interleaved and asserted to the 0th word to the 3rd word held in the instruction latches 149 to 164. Similarly, only the word at the address specified by the central controller is interleaved and output to the data bus. During a data fetch cycle, outputs 45 to 48 of the three-way NAND 97 are interleaved and asserted to the address specified by the central controller from the Oth word to the third word held in the data latches 181 to 196. In the subsequent read access, if the bits other than the LS82 bit of address signal 1 differ from the contents of the address used in the previous read access, "x" DRAM group 41 RA S B, CA SB
00-3, CASB 10-3, CASB20-3,
And, if write access to bank A is performed even though CASB30 to CASB3 are negated (Table address signal 1
Even if a write operation is performed only to the address specified by When one page is selected, the access timing control device 100 controls access to each word within the selected page.
ASAOO~3, CASA10~3, CASA20~3
, control CASA30~3 to perform 1, L 3rd (c)
In 3rd(d)El 3rd(e) and 3rd(f)
As shown in the figure, CASAOO~3, CASAIO~3,
To CASA20-3, CASA30-3 DRA corresponding to the address and data length specified by the central controller
When writing the data on the data bus to the DRAM with only the CAS signal of M set to low level, a write access to bank B is performed (a write operation is performed only to the address specified by address signal 1). As shown in FIG. 3(k), the access timing control device 100 sets the RASB to 'Lo'.
DRAM group 117 constituting bank B.
Select one page from ~132. Access to each word in the selected page is performed by the access timing control device 100 using CASBOO~3, CASBIO~3, CA
Perform this by controlling SB20-3 and CASB30-3.
3 (1) El 3 (m) El As shown in Figure 3 (n) and Figure 3 (o), CASBOO ~ 3, C
ASB10~3, CASB2o~3, CASB30~3
Only the DRAM CAS signal corresponding to the address and data length specified by the central control unit is set to "Low".
According to this embodiment, the data on the data bus is written to the DRAM as a level 4; LDRAM DRAM group 1
By simultaneously holding four words of consecutive addresses, including the word of the address designated by the European central control unit, in the lead latch, when read accessing the word of the address specified by the European central control unit,
Words included in the four words read simultaneously can be read to the data bus by simply enabling the output of the latch without directly accessing the DRAM. By using two sets of 4-word latches for instruction-like data, the number of accesses to DRAM can be reduced even when instruction fetches and data fetches to the storage device are executed alternately. Since this MDRAM is in a standby state, it is possible to reduce power consumption compared to conventional examples, and at the same time, by interleaving the words held in latches and reading them to the data bus, high-speed access is also possible. There is.

In particular, in this embodiment, the word length is 32 bits, but the word lengths are 4 bits, 8 bits,
It may be 16 bits or 64 bits, and there is no restriction on the number of bits.In addition, in this embodiment, the power using two sets of latches for reading data (object 1 of the information to be latched, instruction and It can be used not only for data but also for other information.
It may also be used as a latch for writing, and there are no restrictions on the number of latches.Ly There are no restrictions on the number of banks and ffs that make up the DRAM group, or the number of words that are simultaneously read from the DRAM group and held in the latches. Furthermore, storage devices consisting of multiple blocks are not limited to DRAM, but also static random access memory (SRAM).
According to the present invention, when a read access is made to a storage device consisting of a plurality of blocks, the word of the address specified by the central control unit is included (as described in the detailed description of the invention). By simultaneously reading the word and holding it in the latch, and by interleaving only the output of the latch with the memory device inactive when reading the preceding word and performing the read, high-speed access to the memory device is achieved.
It is possible to reduce power consumption, and when reading words in different address areas alternately, L
By providing multiple latches, the frequency of direct access to the storage device is reduced, and during that time the storage device is kept inactive, and only the outputs of the latches are interleaved for reading, thereby further reducing power consumption. When the present invention is applied to a storage device in which read access to consecutive addresses is frequently used, the practical effects will be significant.

[Brief explanation of the drawing]

FIG. 1 shows the configuration of a memory control device according to an embodiment of the present invention. FIG. 2 is a time chart showing the operation during read access to a storage device according to the same embodiment. FIG. FIG. 4 is a time chart showing the operation during write access, and FIG. 5 is a time chart showing the operation of the conventional memory control device. 90-97...3 manual NAND. 100... Access timing control devices 101 to 13
2... DRAM gourd 133-196... Latch.

Claims (4)

[Claims] (1) A storage device consisting of a plurality of blocks, an access timing control device that outputs an address signal to each block of the storage device and an access signal to each block of the storage device in parallel, and an access timing control device that outputs an access signal to each block of the storage device, and and a latch that holds data selected by the access signal and output from the storage device. (2) When reading from a storage device, an access signal simultaneously accesses a plurality of blocks of the storage device, a latch simultaneously holds multiple pieces of data that the storage device simultaneously outputs as a result of the simultaneous access, and the latch Among the data, the data specified by the address signal is output to the data bus, and when writing to the storage device, the access signal accesses a specific storage device specified by the address signal among the storage devices. The memory control device according to claim 1, characterized in that: (3) The memory control device according to claim 2, wherein the latch is comprised of a plurality of sets of latches. (4) The memory control device according to claim 3, wherein a plurality of sets of latches hold data stored in different address areas of the storage device, respectively for each address area.