JPH10326491A - Memory unit, sram cell, and data transfer method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To rapidly process massive data, by providing an SRAM, DRAMs and two external IO ports, providing two IO ports connected to the external ports and the IO port bidirectionally transferring the data between with the DRAM in the SRAM and executing read-out and write-in for the DRAM parallel to the read-out and write-in from the outside with the SRAM. SOLUTION: The dram consists of four 4 M bits memory banks respectively constituted of 512 rows × 32 columns × 256 bits. The SRAM consists of 4 K bits constituted of 16 lines ×16 word × 16 bits to transfer the 16 bits data between with the IO data pins 18, 20 of the external ports A, B through two SRAM ports corresponding to respective data pins. Two SRAM ports can access independently and simultaneously even any location in the SRAM 16. They can transfer simultaneously and parallel a 256 bits data block in between with the DRAMs 12 through a global input/output bus.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION This application relates to memory devices, and more particularly to dynamic random access memory (DR).
AM) and a static random access memory (SRAM) having cells with three input / output (IO) ports
And a multi-port random access memory (M
PRAM).

[0002]

2. Description of the Related Art To develop a computer graphics system, a high-speed memory capable of storing a large amount of data such as 3D graphics data is required.
One such memory is a cached memory for storing the most commonly accessed data developed to improve DRAM main memory performance by utilizing faster SRAM cache memory. There is. For example, US Pat. No. 5,566,31
No. 8 discloses an enhanced DRAM that integrates an SRAM cache memory with a DRAM on a single chip. A sense amplifier and a column write select register are coupled between the SRAM cache and the DRAM memory array. The column decoder, in conjunction with the SRAM cache,
Provides access to the desired column of RAM. A row decoder, in conjunction with a DRAM memory array, allows access to a particular row of the DRAM. Input / output control and data latches receive data from the SRAM and provide data output via data input / output lines. The current row of data accessed from the DRAM memory array is SRA
It is held in the M cache memory. If a cache "miss" is detected, the entire cache memory
From the RAM memory array, it is refilled via a bus from the DRAM to the cache memory.

To improve the speed and performance of RAMs, dual-port RAMs have been developed that allow two separate I / O ports to access a memory array. However, dual port RAM
Data input and output cannot be effectively controlled. This is because ports cannot be exchanged.
For example, data traffic cannot be redistributed between ports if one of the ports is overloaded and the other is underloaded.

[0004] It is therefore desirable to provide a multiport RAM chip with interchangeable ports.

Further, a dual-port RAM can provide only one of write and read access to a memory array to an external device such as a graphics controller at a time. For example, while one port is being used to write data to the memory array, the other port cannot read data from the memory array.

It is desired to provide a multiport RAM capable of simultaneously performing read access and write access from different ports.

The speed of reading and writing data in a RAM is limited by the switching delay between the moment the RAM is activated and the moment valid data appears on the input or output. For example, a DRAM read operation can be triggered by switching row address strobe / RAS and column address strobe / CAS to a low level. For example, the delay in reading data is / RA
Determined by the latency of RAS, which corresponds to the delay between the moment the S signal transitions low and the moment valid data appears at the output.

After the operation of the DRAM is started, the SRAM
DRAM and S to continue the write or read operation of
It is desirable to provide parallel operation with RAM. This could increase the bandwidth of data transfer in RAM by eliminating RAM switching delays caused by RAS latency.

An SRAM is an external IO port and a DRAM
In order to be able to support access from
It would be desirable to provide an SRAM cell having an external IO port of RAM and a number of IO ports coupled to DRAM.

[0010]

DISCLOSURE OF THE INVENTION Accordingly, one advantage of the present invention is that:
An object is to provide a multi-port memory chip having interchangeable input / output ports.

Another advantage of the present invention is that it provides a multiport RAM that allows read and write accesses from different ports to occur simultaneously.

A further advantage of the present invention is that it allows the operation of a DRAM and the operation of an SRAM to be performed in parallel.
It is to provide a multi-port RAM.

Another advantage of the present invention is to provide a multi-port RAM having an SRAM comprised of cells having an external IO port of the MPRAM and a number of IO ports coupled to the DRAM.

[0014] The above and other advantages of the present invention are at least somewhat achieved by providing a memory device having first and second external input / output ports disposed on a single chip. The first memory may be configured to store data. A second memory having a smaller storage capacity than the first memory is coupled to the input / output ports for storing data to be output from those ports and receiving data input from the ports. Second
Are coupled to first and second external input / output ports, respectively, to enable them to write data to and read data from storage cells. And a third port coupled to the first memory and having a third port for allowing it to write data to and read data from the storage cell. . For example, the second memory may include a triple port SR arranged on a plurality of lines.
AM storage cells may be included.

According to a first aspect of the present invention, each of the first, second and third ports includes an input data line for receiving data to be written into the storage cell, and a read from the storage cell. Output data line for transferring data to be stored, a write control line for controlling data input to the storage cell, and a read control line for controlling data output from the storage cell. .

According to a further aspect of the present invention, the storage cell may have a latch circuit for latching data in response to an input data line. The first, second, and third input pass gates are activated by a signal in a corresponding write control line so that data is passed to the latch circuit via the input data line of the corresponding port. The first, second, and third output pass gates are activated by a signal in a corresponding read control line so that data is transferred from the latch circuit via the corresponding output data line.

According to another aspect of the present invention, two or more read control signals can be simultaneously supplied to the output pass gate to provide multiple read accesses to the storage cells simultaneously.

According to a further aspect of the present invention, the third port can support a data transfer between the first memory and the storage cell performed in parallel with the access to the storage cell from the external input / output port. .

According to another aspect of the present invention, the first port can support data writing to the storage cell in parallel with data reading from the storage cell performed through the second port.

According to the method of the present invention, the SRAM and the DR
To transfer data in a multi-port RAM with an AM, the following steps are performed. That is: S
Writing a data element into the RAM storage cell via one of the first and second data ports; and transferring the data element from the SRAM storage cell to the DRAM via the third data port. Reading.

Further, the following steps may be performed to modify the data in the SRAM storage cell. Reading data from the SRAM storage cell via the first data port, modifying the data, and writing the modified data into the SRAM storage cell via the second data port. And

These and other objects and advantages of the present invention will be readily apparent to those skilled in the art from the following detailed description. The detailed description shows and describes only preferred embodiments of the invention and is merely illustrative of the best mode contemplated for implementing the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and descriptions presented herein are to be considered as illustrative and not limiting.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention is applicable to the general field of memory devices, but one of the best modes for carrying out the present invention is shown in FIG.
Of the multiport RAM (MPRAM) 10 shown in FIG. MPRAM10 arranged on a single chip
Includes a DRAM 12, which is divided into four individually addressable memory banks, each of 4 megabits. Each bank includes a memory array composed of 512 rows × 32 columns × 256 bits. As will be described in more detail below, a single 256-bit global input / output (IO) bus 14 is shared by all four banks of DRAM 12 and connects DRAM 12 to SRAM 16.

The 4 kilobit SRAM 16 can be configured as 16 lines × 16 words × 16 bits. DRA
Each 256-bit transfer between M12 and SRAM 16 replaces or updates one of the 16 lines in SRAM 16.

The MPRAM 10 has two identical and independent 16-bit IO ports A and B.
Each of ports A and B provides read and write access to each cell of SRAM 16. IO
Data pins 18 and 20 are connected to ports A and B, respectively, to provide 16-bit data DQA and DQB.
Provides input and output.

The SRAM control signals SCA and SCB for ports A and B are
2 and the port B control circuit 24 to supply data via the SRAM for data read or write, burst end, etc.
Specifies the operation of Write enable commands / WEA and / WEB for ports A and B are provided via port control circuits 22 and 24, respectively, to decode the SRAM write operation. In addition, port control circuits 22 and 24 can also receive special function commands SFA and SFB, respectively, to enable the write per bit operation mode and to terminate the burst.

The clock generator 26 supplied with the master clock signal CLK provides an internal clock for the operation of the MPRAM. All MPRAM input signals are referenced to the rising edge of master clock CLK. The master clock enable signal CKE is supplied to the clock generator 26.
To enable internal clock generation. The chip select signals / SD and / SS are respectively DRA
The chip selection function is provided to the M12 and the SRAM 16.

The port control circuits 22 and 24 and the clock generator 26 are coupled to an SRAM control circuit 28 that controls write and read access to the SRAM 16. The data transfer path between each of IO data pins 18 and 20 and SRAM 16 for data writing or data reading is configured as a two-stage pipeline.

For writing data to SRAM 16, write commands WA and WB for ports A and B, respectively, may be issued by SRAM control circuit 28 on a first clock cycle. The data to be written is provided on the second clock cycle. SRAM
The 16 addressed lines and words are supplied to port control circuits 22 and 24, respectively, at port A
Address signals ADA and A for A and B
Determined by DB. For example, the addressed line may be defined by the upper four bits of address signals ADA and ADB, and the 16-bit word to be addressed may be determined by the lower four bits of address signals ADA and ADB.

In order to read data from the SRAM 16,
Read commands RA and RB may be issued by SRAM control circuit 28 during a first clock cycle. Data is accessed on the rising edge of the second clock and is valid on the third clock cycle.
As with the write operation, the addressed lines and words of SRAM 16 are determined by the address signals ADA and ADB for ports A and B, respectively.
For example, the line to be addressed has an address signal AD
A 16-bit word defined and addressed by the upper four bits of A and ADB is the address signal ADA.
And the lower 4 bits of ADB.

As described in more detail below, port A
And B are independent and can provide simultaneous reading and writing of data to any location in SRAM 16. However, the user is prevented from writing to the same SRAM cell from both ports at the same time. IO buffers 30 and 32 are coupled to ports A and B, respectively, to buffer data during read and write operations.

Write per bit mask registers 34 and 3 connected to IO buffers 30 and 32, respectively.
6 is used to perform a masked write operation from ports A and B. The SRAM control circuit has a port A
Write command M masked for
Issue WA and MWB to mask DQA and DQB data read from or written to SRAM 16. Pins 38 and 40 supply 2-bit mask control data DQMA and DQMB to ports A and B, respectively. When any bit of the mask control data DQMA and DQMB is set high, the DQA data and DQB data read or written, respectively, are masked.
For example, the upper bits of mask control data DQMA and DQMB control the upper bytes of DQA and DQB data, respectively. The lower bits of the mask control data DQMA and DQMB may control the lower bytes of the DQA and DQB data, respectively. Load mask register commands LMRA and LMRB are issued by SRAM control circuit 28 for ports A and B, respectively, to write right bit registers 34 and 36.
It is possible to load

The MPRAM 10 has an SRAM 16 and a DRA
And M12 to operate in parallel. DRAM
Control circuit 42 forms a DRAM control command defined by control signals / RAS and / CAS. The 2-bit bank address command BA has four DRAMs.
Select one of the banks. The 11-bit address command ADD includes a DRAM row and column address, DR
The transfer operation of the AM, and of the lines in the SRAM 16, the lines from which data can be transferred to the DRAM 12 or the data to which the DRAM 12
Select a line that can be transferred from For example, AD
The lower 9 bits of the D command select the DRAM row address, the lower 5 bits select the DRAM column address,
Two bits of the D command can be used to define a DRAM transfer operation. The upper 4 bits can select one line out of 16 lines in the SRAM.

The DRAM control circuit 42 forms a DRAM read transfer command DRT, and transfers one block designated by the ADD command out of 32 blocks of data to
The data is transferred to one of the 16 lines in the SRAM 16. DRAM write transfer command DWT is also DRAM
The data is transferred from one line designated by the ADD command out of the 16 lines of the SRAM formed by the control circuit 42 to one block out of 32 blocks in the DRAM 12.

The data transfer register 44 is provided in the DRAM 12
Between the DRAM 12 and the SR 16
Supports data transfer to and from AM16. A 32-bit byte write enable mask register 46 is used to mask DRAM write transfers. This register 46 can be loaded from either port A or port B when a load mask register command LMR is issued. Each bit in the register 46 masks one byte of the 256-bit global IO bus 14. Byte write enable mask register 46 and write per bit mask registers 34 and 36 may be bypassed during writing to DRAM 12 and SRAM 16, respectively.

The MPRAM 10 has a programmable burst mode. This mode allows the user to 1,2,4, for bursts of data written to SRAM 16 from ports A and B, or for bursts of data read from SRAM 16 to ports A and B.
And 8 burst lengths can be selected. Sequential or interleaved bursts may be selected. The set mode register command SMR issued by the DRAM control circuit 42 allows the length and type of the burst to be programmed into the internal mode register. The mode register code (M
RC) may be entered using an ADD command. M
The RC is stored in the mode register until it is overwritten by the next SMR command or until power is no longer applied to the MPRAM 10. SM
The R command may be issued when the DRAM 12 and the SRAM 16 are idle. End burst commands BTA and BTB can be issued by SRAM control circuit 28 to end the burst sequence from or to ports A and B, respectively.

FIG. 2 shows the SRAM 16, DRAM 12, external ports A and B, port A control circuit 22, port B
The interconnection between the control circuit 24 and the DRAM control circuit 42 is schematically illustrated. The SRAM 16 has 25 lines.
It can be composed of 16 lines with 6 storage cells.
The three IO ports A, B, and D are
, And supports data transfer between external ports A and B and DRAM 12. SRAM ports A, B, and D
Have an IO data bus and a control bus.

SRAM ports A and B allow an external memory controller to access SRAM 16 through external ports A and B, respectively. The port A input / output and control circuit 162 and the port B input / output and control circuit 164 are provided for SRAM ports A and B,
Supports data transfer and control and address signals. For example, 16-bit data DQA and DQB
Are transferred between IO data pins 18 and 20 of external ports A and B and SRAM ports A and B, respectively. Read and write SRAM accesses from external ports A and B via SRAM ports A and B are performed by port A control circuit 22 and port B control circuit 24.
Are respectively controlled by control and address signals.

The SRAM port D is connected to the SRAM 16 and the DR
Supports data transfer to and from AM12. For example, S
RAM port D is coupled to global IO bus 14
obtain. The DRAM control circuit 42 reads out data via the port D
And write SRAM access. Global I
Between the SRAM 16 and the DRAM 12 via the O bus 14
Data transfer was filed at the same time as this application,
Incorporated by reference, "Having a shared global bus
Multi-port RAM (“MULTI-PORT RAM HAVING SHARED
 Applicants co-pending, entitled "GLOBAL BUS") "
Application SN Are disclosed in more detail within.

Referring to FIG. 3, each storage cell 160 of SRAM 16 has three ports A, B, and D, each of which has a data IO line and a control line. The data IO lines of ports A, B, and D are
It is coupled to the M10 A, B, and D port data IO buses. The control lines of ports A, B, and D are connected to the control buses of SRAM ports A, B, and D, respectively.

As shown in FIG. 4, each port of SRAM cell 160 has a read / write data path and a read / write address control line. Write address line WY
A, WYB, and WYD provide write address signals for cell ports A, B, and D, respectively. Read address lines RXA, RXB, and RXD
They are used to provide read address signals to cell ports A, B, and D, respectively. Input data line W
LA, WLB and WLD allow data from external ports A and B and DRAM 12 to be written into SRAM cell 160 via cell ports A, B and D. Output data lines RLA, RLB, and RLD are connected through cell ports A, B, and D,
Cell 160 to external ports A and B and DRAM
12 supports reading data.

For example, data to be written into cell 160 from external port A is placed on input data line WLA. A write address signal provided on write address line WYA to address cell 160 is generated by port A control circuit 22 based on the ADA address signal.

In order to read data from external port A, port A control circuit 22 generates a read address signal based on the ADA address signal. A read address signal is provided on read address line RXA to address cell 160. The read data is transferred to external port A via output data line RLA.
Read and write accesses to the cell 160 from the external port B are performed on the output data line RLB, the read address line RXB,
The same operation is performed using input data line WLB and write address line WYB.

DRAM 12 writes data into cell 160 and reads data from cell 160 via input data line WLD and output data line RLD, respectively. In order to perform data reading, cell 160 is addressed via read address line RXD. The read address signal is generated by DRAM control circuit 42 based on the ADD address signal. Cell 160 formed by DRAM control circuit 42 based on the ADD address
Is provided on a write address line WYD.

FIG. 5 shows a triple port S containing a logical 1 value.
An operation of writing a logical 0 value from the external port A into the RAM cell 160 will be described. Thereafter, data received by cell 160 via its port A is read out to DRAM 12 via cell port D. As shown in FIG. 5, a logic 0 from external port A is placed on the WLA data line of SRAM cell 160 on the rising edge of internal clock signal CLK. The WYA line is supplied with a write address signal from port A control circuit 22 to enable port A data to be stored in cell 160.

Thereafter, the DRAM control circuit 42
A read address signal is supplied to the RXD line 0 so that the stored data is read out to the DRAM 12. The logic 0 value is applied to the SRA via the RLD data line of cell 160.
The data is transferred from the M cell 160 to the DRAM 12.

Therefore, external port A and DRAM
12 makes it possible to perform write and read access to the same SRAM cell in parallel.

FIG. 6 shows a triple port SRAM cell 16.
0 shows an example configuration. Cell 160 includes input data lines WLA, WLB and WLD, and inverters I1 and I1.
2, and input pass transistors Q1, Q2, and Q3, respectively, connected between and formed by I3 and a latch circuit for latching data. Inverters I1 and I2 are cross-coupled. Inverter I3 is coupled to the output of inverter I1. Each of inverters I1 to I3 can be provided by a pair of MOS transistors.

Output pass transistors Q4, Q5 and Q6 are provided with a latch circuit and output data lines RLA, RLB,
And RLD, respectively. The gates of the pass transistors Q1, Q2, and Q3 are respectively
Connected to write address lines WYA, WYB and WYD. The gates of pass transistors Q4, Q5, and Q6 are connected to read address lines RXA, RXB, and R, respectively.
Connected to XD. For example, a MOS transistor
Can be used as input and output pass transistors.

When one of external ports A and B or DRAM 12 starts writing data to SRAM cell 160, a corresponding write address signal activates one of input pass transistors Q1-Q3. , The data supplied to one of the input data lines is the latch circuit I1.
To I3. If write access is made simultaneously to a single SRAM cell 160 from two or more ports, invalid data may be provided. Therefore, the MPRAM 10 cannot be written to the same SRAM cell in parallel from both the external ports A and B, or from both the DRAM 12 and one of the external ports.

The read address signal activates one or more output pass transistors Q4 to Q6 to enable data to be sent from the latch circuit to the corresponding output data line. Therefore, triple port SRAM cell 1
60 can support multiple read operations to be performed in parallel.

The SRAM operation is performed on ports A, B, and D
, Only one operation can be performed at a time from any one of
It can support that two operations are performed in parallel. For example, port A can write to cell 160 in parallel with reading from cell 160 to ports A and D.

Therefore, triple port SRAM cell 160 can be connected to DRAM 12 via port D or to DRAM 12 in parallel with MPRAM 10 performing read and write access to SRAM 16 from an external memory controller via ports A and B. DRAM 12 to SRAM
Allows data to be read or written. Therefore, the operations of the DRAM and the SRAM can be performed simultaneously.

External ports A and B are both SRAM
Having access to cell 160, the external memory controller coupled to external ports A and B allows the SRAM memory to wait between read and write cycles without having to wait for the SRAM.
It is possible to modify the data in 16. On all clock cycles, one of the external ports can perform a read operation and the other port can perform a write operation. For example, as shown in FIGS. 7A and 7B, on the first clock cycle, port B
Data element D1 can be read from M cell 160. However, it is assumed that one clock cycle is required for the external memory controller to modify the data element D1. Port A can then write the modified data element D1 into SRAM cell 160. Subsequent data elements D2, D
3 and D4 are similarly modified. Therefore, SR
The bandwidth of the read-modify-write (RMW) cycle for AM16 is significantly improved.

Thus, a memory having an SRAM, a DRAM, and two external IO ports has been described. Each SR
An AM cell has two IO ports coupled to external IO ports and one IO port for transferring data to and from the DRAM. This triple port SRAM cell is coupled to a latch circuit to
O port and three input data lines for writing data supplied from the DRAM and coupled to a latch system to store the stored data to external IO port and DRA.
And M output data lines. Three write address lines and three read address lines are connected to external I
SRAM cells are addressed for data write and read operations performed by O port and DRAM.

While only the preferred embodiment of the invention has been shown and described in this disclosure, the invention is capable of variation and modification within the spirit of the invention as set forth in the appended claims. Should be understood.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the architecture of a multiport RAM chip.

FIG. 2 is a block diagram showing a configuration of an SRAM in the multiport RAM.

FIG. 3 is a diagram showing ports of each SRAM cell.

FIG. 4 is a diagram showing data and address lines of an SRAM cell.

FIG. 5 is a timing chart showing data writing to the SRAM cell and data reading from the SRAM cell.

FIG. 6 is an exemplary circuit diagram of an SRAM cell.

FIGS. 7A and 7B show a read-modify-write cycle in an SRAM.

[Explanation of symbols]

 Reference Signs List 10 Multiport RAM 12 DRAM 14 Global input / output bus 16 SRAM 22 Port A control circuit 24 Port B control circuit 162 Port A input / output and control circuit 164 Port B input / output and control circuit

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor William El Randolph, United States, 27705 North Carolina, Durham, West Club Boulevard, 2318 (72) Inventor Steven Camacho, United States, 27712 North Carola Centennial Drive, Durham, Ina, 5417

Claims (20)

[Claims] 1. A first and a second circuit for providing data input and output on a single chip.
An external input / output port, a first memory for storing data, and a storage capacity smaller than that of the first memory, and coupled to the input / output port to output data from the input / output port. And a second memory for storing data to be received and for receiving data input from the input / output port, wherein the second memory is connected to the first and second external input / output ports, respectively. First and second ports coupled to enable the first and second ports to write data to and read data from the storage cells; And a third port coupled to allow the first memory to write data to and read data from the storage cell. 2. The memory device according to claim 1, wherein the second memory includes a plurality of lines each having a plurality of triple port storage cells. 3. Each of the first, second, and third ports of a storage cell has an input data line for receiving data to be written into the storage cell, and data read from the storage cell. 2. The memory device according to claim 1, further comprising: an output data line for transferring data. 4. Each of the first, second, and third ports of a storage cell has a write control line for controlling data input into the storage cell, and an output from the storage cell. 4. The memory device according to claim 3, further comprising: a read control line for controlling data. 5. The memory device according to claim 4, wherein said storage cell includes a latch circuit for latching data in response to said input data line. 6. The memory cell according to claim 1, wherein data is latched via an input data line of said first, second or third port in response to a write control signal in a corresponding write control line. 6. The system of claim 5, further comprising first, second, and third input passgates for enabling the signals to be sent to the circuit.
A memory device according to claim 1. 7. The storage cell according to claim 1, wherein the first, second and third memory cells are
Respectively, in response to the read control signal of the first, second, and third ports, respectively, for transferring data from the latch circuit via the output data lines of the first, second, and third ports. 7. The memory device according to claim 6, further comprising: 8. The system of claim 1, wherein two or more of the first, second and third read control signals are provided in parallel to the output pass gate to provide multiple read accesses to the storage cells simultaneously. Item 8. The memory device according to item 7. 9. The data transfer between the first memory and the storage cell, wherein the third port supports data transfer performed in parallel with access to the storage cell from the external input / output port. The memory device according to claim 1. 10. The first port supports a data write operation to the storage cell performed in parallel with a data read operation from the storage cell performed through the second port. The memory device according to claim 1. 11. The storage cell is an SRAM cell.
The memory device according to claim 1. 12. An SRAM arranged on a memory chip having first and second external data ports and a DRAM.
The SRAM cell comprises: a latch circuit for latching data; and a first circuit for supporting bidirectional data transfer between the first and second external data ports and the latch circuit. And a second port, and a third port for supporting bidirectional data transfer between the DRAM and the latch circuit.
cell. 13. The first and second ports include first and second input data lines for coupling the latch circuit to the first and second external data ports, respectively, and first and second ports. The SRAM cell of claim 12, comprising two output data lines. 14. The circuit of claim 13, wherein the third port includes first and second input data lines and first and second output data lines for coupling the latch circuit to the DRAM. The SRAM cell as described. 15. The first and second ports for providing write and read access to said SRAM cells to said first and second external data ports. 15. The SRAM cell of claim 14, further comprising a control line and first and second read control lines. 16. The third port further includes a third write control line and a third read control line for providing the DRAM with write and read access to the SRAM cell. The SRAM cell according to claim 15. 17. The semiconductor device according to claim 17, wherein said first, second, and third input data lines are respectively coupled to said latch circuit and connected to said first, second, and third write control lines, respectively. 17. The S of claim 16, further comprising first, second and third input pass transistors having a gate electrode.
RAM cell. 18. A gate coupled between the first, second and third output data lines and the latch circuit, respectively, and connected to the first, second and third read control lines, respectively. The S of claim 17, further comprising first, second, and third output pass transistors having electrodes.
RAM cell. 19. A DRAM coupled to first and second external input / output ports, a DRAM, and first and second data ports coupled to the first and second external input / output ports and the DRAM. S with third data port
A data transfer method in a memory device having a RAM storage cell, the method comprising: writing a data element into the SRAM storage cell via one of the first and second data ports; From the SRAM storage cell to the DRAM via the third data port. 20. reading data from the SRAM storage cell via the first data port; modifying the data; and transmitting the modified data via the second data port. Writing into the SRAM storage cells.