JPH04324187A - Dynamic ram - Google Patents

Abstract

PURPOSE:To provide a dynamic RAM provided with a multi page mode which enables quick access. CONSTITUTION:Data is transferred to one line of a memory cell array 10 spedified by a low address, one bit of data specified by a column address with specified one line data is transferred to the outside and plural page buffers 8 are provided so as to hold the content of data equivalent to one line of the memory cell array 10.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic RAM having a multi-page mode that allows high-speed access.

[0002]The memory used by the processor includes ROM and R.
There is AM. ROM is a read-only memory often called R.
Contrasted with AM. RAM is randomly accessible memory. Among the RAMs, there are static RAMs (hereinafter referred to as "SRAM") that can store data once and retain the data until the power is turned off, and other dynamic RAMs (hereinafter referred to as "DRAMs").

Generally, DRAM has a larger storage capacity than SRAM, but has problems of slow access speed and long cycle time. One of the reasons for the slow access speed is that the address is given twice in order to reduce the number of pins on the chip. Furthermore, the cycle time is long because, in addition to the long access time, reading data from a memory cell destroys the contents of the memory cell, which requires rewriting.

0004

[Prior Art] In order to solve such problems, DR
For AM, nibble mode, static column mode, high speed page mode, etc. have been considered. These modes are for maintaining the contents of a previously accessed page in a buffer within the DRAM chip, thereby allowing subsequent accesses to the same page to be made at high speed without providing a page address. These high-speed access methods require about half the access time compared to normal access methods.

[0005]

However, the conventional high-speed page mode was only effective when one page was accessed continuously. For example, even if the high-speed page mode is started by accessing the instruction code area, the high-speed page mode must be canceled when the data code area of another page is accessed. Generally, instruction codes and data codes are often located on separate pages, so the conventional high-speed page mode has the problem of not being very effective.

In view of these conventional problems, the present invention provides a DRA that has a multi-page mode that enables high-speed access even in a system that separately manages instruction code areas, data code areas, and other stack areas.
The purpose is to provide M.

[0007]

According to the invention, the above objects are achieved by the means set out in the claims.

That is, the invention according to claim 1 provides a data input buffer for buffering data input from the outside, a data output buffer for buffering data output to the outside, and a memory cell array for storing data. an address buffer that buffers an external address signal indicating an address of data stored in the memory cell array; a column decoder that decodes a column address held by the address buffer; and a column decoder that decodes a row address held by the address buffer. Data is transferred between a row decoder and one row of the memory cell array specified by the row address, and data of one bit of data specified by the column address is transferred to and from the external data in one specified row. a plurality of page buffers that perform transfer and hold data contents corresponding to one row of the memory cell array; a page address buffer that buffers external page addresses indicating addresses of the plurality of page buffers; and the memory a sense amplifier input/output gate serving as a gate for data transferred between the cell array and the data input buffer, data output buffer, or page buffer; a row address strobe signal, a column address strobe signal, and a write enable signal from the outside; The dynamic RAM includes a DRAM control circuit that controls the data input buffer, the data output buffer, the address buffer, the column decoder, the row decoder, and the page address buffer according to a page mode signal.

[0009] Furthermore, the invention of claim 2 provides that when data is read from the dynamic RAM of claim 1, if any one of the plurality of page buffers holds specified data, the page buffer is Read the specified data from the buffer, and if none of the page buffers holds the specified data, select page buffer 1, and read one row of the memory cell array that contains the specified data in this page buffer. This is a dynamic RAM control method that transfers the specified data and reads the specified data.

[0010] Furthermore, the invention as claimed in claim 3 provides that, in the case where data is written to the dynamic RAM of claim 1 and the data is updated, specified data is written to the memory cell array and the data is updated; In this dynamic RAM control method, if a page buffer holds data before being updated, the data in the page buffer is also updated.

[0011] Furthermore, the invention according to claim 4 provides that when data is updated by writing data to the dynamic RAM according to claim 1, if no page buffer holds the data before updating, 1. selects a page buffer, writes the contents of the page buffer to the corresponding row of the memory cell array, transfers the row contents of the memory cell array containing the unupdated data to the page buffer, and retains the unupdated data. This is a dynamic RAM control method for updating buffer data.

0012

According to the present invention, one port of a DRAM has a plurality of page buffers, and by controlling the page buffers from the outside, high-speed access can be provided for a wider range of applications than before. FIG. 1 is a diagram showing an example of the configuration of a DRAM according to the present invention. A feature is that a plurality of page buffers 8 are added. In this diagram,
There are four. Each page buffer 8 is one of the DRAMs.
Retain page content. Although one page will be described below as corresponding to one row of the memory cell array 10, this does not necessarily have to be the case. for example,
For a 4 megabit DRAM, one page is 2048 bits. It goes without saying that this page has nothing to do with pages in the virtual storage system.

[0013] By instructions from outside the DRAM, the conventional DRAM
It can be read and written in the same way as RAM. Furthermore, one page can be transferred at one time through the sense amplifier input/output gate 8 between the page buffer 8 specified by the address of the page address buffer 2 and the row of the memory cell array 10 specified by the row array of the address buffer 3. Furthermore, the contents of the page buffer 8 can be read or rewritten by specifying a page buffer address and a column address from outside the DRAM. D
The port portion of the RAM is provided with a data input buffer 4 and a data output buffer 5, and also provided with a column decoder 6 and a row decoder 7 for decoding column addresses and row addresses of the memory cell array 10. With this configuration, the conventional high-speed page mode is further expanded to enable high-speed access to multiple pages.

DRAM with multiple page buffers 8
can also be considered as a RAM that is a combination of DRAM and SRAM. SRAM can be considered a type of cache of DRAM. In the present invention, how to use the plurality of page buffers 8 can be freely determined outside the DRAM as described above. Table 1 shows what kind of operation mode the DRAM takes depending on the control signal from the outside of the DRAM.

[0015]

[Table 1]

In FIG. 1, a DRAM control circuit 1 controls the operation mode of the DRAM according to external control signals. External control signals include a row address strobe signal (hereinafter referred to as *RAS), a column address strobe signal (hereinafter referred to as *CAS), a write enable signal (hereinafter referred to as *WE), and a page mode signal (hereinafter referred to as *WE).
(hereinafter referred to as *PG). All of them are negative logic, but in the text of this specification, instead of using a horizontal bar as shown in the tables or figures, "*" is used to represent the same thing. In addition, in Table 1 described earlier, *RAS and *CAS are "L" if they become "L" during access.
”, *PGras indicates *PG at the falling edge of *RAS, and *PGcas indicates *PG at the falling edge of *CAS.

As described above, the DRAM according to the present invention has D
By controlling from outside the RAM, it has various operation modes as listed in Table 1. Hereinafter, each operation mode will be explained in detail based on an example.

[0018]

Embodiment FIGS. 2 to 5 are diagrams showing timing charts in each mode. These assume the DRAM in Figure 1, and A0 to A10 are 1s specified from outside the DRAM.
It is a 1-bit address, and P0 to P1 are page buffer addresses specified from outside the DRAM. If you give an 11-bit address twice, you can specify a 4 mega address, and if you give a 2-bit address, you can specify 4 addresses.

FIG. 2(a) shows a read cycle. Same as the conventional read cycle, A at the falling edge of *RAS.
0 to A10 are sampled and latched into the chip as row addresses. *At the falling edge of CAS, A0 to A1
0 is sampled and latched into the chip as a column address, and since the *WE signal is "H", it is known that it is a read cycle. Since *PG is "H" at the falling edge of either *RAS or *CAS, a normal read access is performed. *Read data is obtained at Dout after a certain period of time after CAS falls.

FIG. 2(b) shows a write cycle. Same as the conventional write cycle, A at the falling edge of *RAS.
0 to A10 are sampled and latched into the chip as row addresses. *At the falling edge of CAS, A0 to A1
It samples 0 and latches it into the chip as a column address, and since the *WE signal is "L", it knows that it is a write cycle. If *PG is "H" at the falling edge of either *RAS or *CAS, a normal write access is performed. *Din sampled at the falling edge of CAS is written to the designated memory cell.

FIG. 3(c) shows a multipage mode read start cycle. The multi-page mode read start cycle is the same as the read cycle in FIG. 2A except for *PG and P0 to P1, and the data read to Dout is also the same. In the multi-page mode read start cycle, *PG is set to "L" when *RAS falls. As a result, P0 at the falling edge of *CAS
~P1 is sampled. The row data specified by RA is written to the page buffer specified by P0 to P1.

FIG. 3(d) shows a multipage mode read cycle. In multi-page mode read cycle, *CAS is set to "L" while *RAS is kept at "H".
”. At the fall of *CAS, *WE, *
PG, A0 to A10 (CA), and P0 to P1 are sampled. At this time, *WE and *PG are kept at "H". As a result, the contents of the column address CA of the page buffer designated by P0 to P1 are read to Dout. Since there is no phase for inputting row addresses and there is no need to access the memory cell array, access speeds and cycle speeds comparable to those of SRAM can be achieved. In the conventional page mode, *RAS is set to “L” during page access.
However, in this multi-page mode, *RAS can be returned to "H" and the contents of the page buffer can be read out at any time even after another access cycle has started.

FIG. 4(e) shows a multipage mode write start cycle. The multi-page mode write start cycle is the same as the write cycle shown in FIG. 2B except for *PG and P0 to P1, but no write is performed to the memory cells. *PG is set to "L" at the falling edge of *RAS, and set to "H" at the falling edge of *CAS. P0 to P1 are sampled at the falling edge of *CAS. In this cycle, the contents of the row at row address RA are written to the page buffer specified by P0 to P1. However, only the contents of the column of the column address CA of the page buffer are written with the data given by Din.

FIG. 4(f) shows a multipage mode write cycle. In multi-page mode write cycle, *CAS is set to "L" while *RAS is kept at "H".
”. At the fall of *CAS, *WE, *
PG, A0 to A10 (CA), P0 to P1, and Din are sampled. At this time, *WE is “L” and *PG is “
This causes the data given from Din to be written to the column of the column address CA of the page buffer specified by P0 to P1. Writing to the memory cell array is not performed. Input the row address. Since there is no phase and there is no need to access the memory cell array, it is possible to achieve access speeds and cycle speeds comparable to those of SRAM.In the conventional high-speed page mode, *RAS is kept at "L" during intra-page access. However, in this multi-page mode, *RAS is set to “H”.
” and even after another access cycle,
You can write to the page buffer at any time. In the multi-page mode write cycle, writing to the memory cell array is not performed, so when it is desired to transfer from the page buffer to the memory cell array, the following two cycles are executed.

FIG. 5(g) shows a multipage mode write start cycle. The multi-page mode write start cycle is the same as the write cycle shown in FIG. 2A except for *PG and P0 to P1. *PG is *RAS
Set to "H" at the falling edge of *CAS, and set to "L" at the falling edge of *CAS. P0 to P1 are sampled at the falling edge of *CAS. In this cycle, first, Di
The data given by n is written. Further, the contents of all columns of the page buffer after writing are written at once to the row of the row address RA of the memory cell array. The contents of the specified page buffer are retained in the state in which Din is written, so even after the multi-page mode write end cycle, the contents shown in FIGS. 2(b), 3(d), and 4(e)
, the cycle shown in FIG. 4(f) can be executed.

FIG. 5(h) shows a multipage mode write-back cycle. In the multi-page mode write-back cycle, everything other than *PG and P0 to P1 is shown in Figure 2 (a).
), but in the multipage mode write back cycle, *PG is set to "H" at the falling edge of *RAS, and *PG is set to "L" at the falling edge of *CAS. put. As a result, P0 to P1 are sampled at the falling edge of *CAS. Unlike the read cycle, the data read to Dout is from P0 to
This is the content of column address CA of the page buffer specified by P1. At the same time, the contents of all columns of the designated page buffer are written at once to the row at row address RA of the memory cell array. The contents of the specified page buffer are D
Since in is retained in the written state, even after the multipage mode write end cycle, as shown in FIG. 3(d),
The cycles shown in FIGS. 4(f), 5(g), and 5(h) can be executed.

[0027] DR with the multi-page mode described above
A simple system example using AM is shown in FIGS. 6 and 7. FIG. 6 shows the entire computer system, in which the CPU 11
are instruction cache 11a and data cache 12b
Take advantage of. Further, a configuration example of the memory control circuit 13 in FIG. 6 is shown in FIG. In this example, it is assumed that 64 4 megabit multi-page DRAMs 14 are used, 32 megabytes of memory is connected, and access is performed in units of 64 bits (8 bytes). In FIG. 7, the page tag 16 has the same number of page addresses (=4 in this example) as the number of page buffers of the multi-page DRAM 14.
column address), and when a page address is given from the outside, it is possible to search whether the page address is stored in the tag. As a result of the search, a signal indicating a hit or a miss and a signal indicating which page buffer it was in if there was a hit are output. The page tag 16 contains information indicating whether the contents of the page buffer are valid, information indicating whether the contents of the page buffer and the contents of the corresponding row of the memory array are the same (clean when the same, dirt when different).
) is also managed. Therefore, a hit occurs when the page addresses match and the page buffer is valid.

In FIG. 7, a selector 15 selects and outputs a row address or a column address, and a control circuit/timing generation circuit 17 sends a control signal to the multi-page DRAM 14. The input/output buffer 18 acts as a buffer when data of the multi-page DRAM 14 is input/output.

As with general cache management, the write-through method and the write-back method can be considered for managing the page buffer. First, an example of a control method using the write-through method will be explained. In the case of the write-through method, since the data is always clean, clean/dirty information is not necessary. First, read access will be explained. If the address you are trying to read hits the page tag, DR
Since the page is on the AM page buffer,
The hit page buffer number is placed on P0 to P1 and read at high speed in a multi-page mode read cycle. Since memory access generally has locality, the probability of hitting a page tag is high. On the other hand, in the case of a lead that misses a page tag, 1 out of 4 buffers
Select one buffer. The selection method is, for example, LRU (
Least RecentlyUsed). The multi-page mode read start cycle reads the contents of the requested address and transfers the contents of the page from the memory array to the selected page buffer. At the same time, the address in the page tag is rewritten to the address of this page and set to valid.

Next, write access will be explained. If the address you are trying to write hits a page tag, that page is on the DRAM page buffer, so put the hit page buffer number in P0 to P1 and end the multipage mode write. Write in cycles. The contents of the page tag (excluding LRU information) remain unchanged. On the other hand, in the case of a write that misses a page tag, a normal write cycle is performed, and
Do not change the contents of the page tag.

Next, an example of a write-back control method will be explained. In the case of the write-back method, when a write hit occurs, a write is performed using a multi-page mode write cycle, and when a write miss occurs, a write is performed using a multi-page mode write start cycle. When replacing a page buffer, if the buffer is dirty, the page buffer is transferred to the memory array by a multi-page mode write-back cycle, and then a new page is transferred to the page buffer.

As described above, by controlling the DRAM page buffer from the outside, the average time required for memory access can be reduced. Note that some special DRAMs for image processing buffer multiple pages, but this multiple page buffer is for multiple ports, and does not have multiple page buffers for one port. Therefore, it is different from the present invention.

[0033]

[Effects of the Invention] As explained above, according to the present invention,
Since it has multiple page buffers, even if the instruction code area and data code area are on different pages, a page buffer can be secured for each area and high-speed access can be continued.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the configuration of a DRAM according to the present invention.

FIG. 2 is a diagram showing a timing chart.

FIG. 3 is a diagram showing a timing chart.

FIG. 4 is a diagram showing a timing chart.

FIG. 5 is a diagram showing a timing chart.

FIG. 6 is a diagram showing an example of a system configuration using a DRAM according to the present invention.

FIG. 7 is a diagram showing a configuration example of a memory control circuit.

[Explanation of symbols]

1 DRAM control circuit 2 Page address buffer 3 Address buffer 4 Data input buffer 5 Data output buffer 6 Column decoder 7 Row decoder 8 Page buffer 9 Sense amplifier input/output gate 10 Memory cell array 11 CPU 12a Instruction cache 12b Data cache 13 Memory control circuit 14 Multi-page DRAM 15 Selector 16 Page tag 17 Control circuit/timing generation circuit 18
input/output buffer

Claims (4)

[Claims] 1. A data input buffer (4) that buffers data input from the outside, and a data output buffer (4) that buffers data output to the outside.
5), a memory cell array (10) that stores data, an address buffer (3) that buffers an external address signal indicating the address of data stored in the memory cell array (10), and an address buffer (3) that stores data.
), a row decoder (7) that decodes a row address held by the address buffer (3), and a column decoder (7) that decodes a column address held by the address buffer (3), and a column decoder (7) that decodes a column address held by the address buffer (3), and a
) of the memory cell array (10). a plurality of page buffers (8) that hold data contents corresponding to one row; a page address buffer (2) that buffers an external page address indicating the address of the plurality of page buffers (8); A sense amplifier input/output gate (9) serving as a gate for data transferred between the cell array (10) and the data input buffer (4), data output buffer (5), or page buffer (8).
and the data input buffer (4) according to the external row address strobe signal, column address strobe signal, write enable signal, and page mode signal.
A DRAM control circuit (1) that controls the data output buffer (5), the address buffer (3), the column decoder (6), the row decoder (7), and the page address buffer (2). Dynamic RAM featuring 2. When reading data from the dynamic RAM according to claim 1, if any one of the plurality of page buffers holds the specified data, the specified data is read from the page buffer. When reading, if none of the page buffers holds the specified data, select page buffer 1, transfer the data of one row of the memory cell array containing the specified data to this page buffer, and transfer the data of one row of the memory cell array containing the specified data to this page buffer. A dynamic RAM control method that reads specified data. 3. When data is updated by writing data to the dynamic RAM according to claim 1, specified data is written to the memory cell array to update the data, and any of the page buffers is updated before the update. A dynamic RAM control method that also updates data in the page buffer if the data is held. 4. When updating data by writing data to the dynamic RAM according to claim 1, if none of the page buffers holds the data before update, select one page buffer, A dynamic method that writes the contents of the page buffer to the corresponding row of the memory cell array, transfers the row contents of the memory cell array containing the unupdated data to the page buffer, and updates the data of the page buffer that holds the unupdated data. RAM control method.