JPH0337747A - Storage device controller, disk cache method and disk cache system - Google Patents

Abstract

PURPOSE:To form the disk cache system provided with both a high speed property of an SRAM and a large capacity property of a DRAM by using simultaneously the DRAM and the SRAM. CONSTITUTION:A storage device controller 1 is provided with a DRAM control part 5 and an SRAM control part 6, and both the RAM control parts 5, 6 execute an access to a DRAM 3 and an SRAM 4, respectively in accordance with an instruction of other control part 10. A memory address of each RAM 3, 4 in such a case is supplied from a memory address control part 8. Also, a data control part 9 converts mutually parallel data of a RAM and serial data of an auxiliary storage device, or switches and connects a data bus of the RAM to the auxiliary storage device side or a microprocessor 2 side. This storage device controller 1 is provided between a host computer and the auxiliary storage device. In such a way, a disk cache system provided with both a large capacity property of the DRAM 3 and a high speed property of the SRAM 4 can be constructed.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a storage device control device, and in particular, it is possible to use a dynamic RAM and a static RAM at the same time, and it is possible to use a dynamic RAM and a static RAM simultaneously. The present invention relates to a storage device control device capable of simultaneous transfer between data and a disk cache system using the same.

[Prior Art] Conventionally, data transfer between a host computer's main storage device and an auxiliary storage device such as a magnetic disk device was not performed directly between the two, but instead was transferred to a memory faster than the auxiliary storage device. A method is known in which the effective access time of the auxiliary storage device is shortened by transferring a partial block from this memory to the main storage device, and this method is called a disk cache method.

A conventional storage device control device that supports such a disk cache method is the AlC manufactured by Adabuchik.
610 and 2400126 manufactured by Emulex Corporation. The former uses static RAM (
The latter uses a dynamic RAM (hereinafter referred to as DRAM) as the memory.

[Problems to be Solved by the Invention] In the conventional technology described above, the memory that can be used for data transfer between the host computer and the auxiliary storage device is limited to either SRAM or DRAM. However, when only SRAM can be used, there is a problem that there is insufficient capacity to store data. On the other hand.

If only DRAM can be used, there is no problem with capacity, but there is a problem with high speed data transfer.

Further, even if there is a device that supports both DRAM and SRAM, a device that accesses either one simply by selecting a mode cannot access both DRAM and SRAM at the same time.

The present invention provides a storage device control device that can connect both a DRAM and an SRAM at the same time, and can use both simultaneously to perform programmable data transfer between a host computer and an auxiliary storage device, and a storage device using the same. The purpose is to provide a disk cache method and system.

[Means for Solving the Problems] In order to achieve the above object, a storage device control device of the present invention is a storage device control device that controls access to an auxiliary storage device in accordance with instructions from a host computer.
a first memory control unit that controls access to the dynamic RAM; a second memory control unit that controls access to the static RAM; and a memory address that outputs the access address of the dynamic RAM and the access address of the static RAM. with the control section.

The memory address control section and a control section that controls the first and second memory control sections are provided.

According to another aspect, another storage device control device according to the present invention is a storage device control device that controls access to an auxiliary storage device in response to instructions from a host computer.
a microprocessor that receives an access request from the host computer to the auxiliary storage device; a first memory control unit that controls access to the dynamic RAM;
a second memory controller that controls access to static RAM; and a memory address comprising first and second registers that hold an access address for the dynamic RAM and an access address for the static RAM given by the microprocessor. a control unit;
a data control unit having a serial/parallel converter that mutually converts between parallel data in the dynamic RAM and static RAM and serial data in the auxiliary storage device; and a control section that controls a second memory control section, a memory address control section, and a data control section.

The data control unit preferably includes the dynamic R
It has a selector that switches and connects the AM and static RAM data buses to the serial/parallel converter side or the microprocessor side.

The disk cache method according to the present invention stores a copy of some data in the auxiliary storage device in memory.

In a disk cache method that improves the effective access speed of the auxiliary storage device by accessing the memory, a dynamic RAM and a static RAM are used as the memory, and when data is written from the host computer to the auxiliary storage device, the host combination A portion of the data from May 11 is written into the static memory, and the data is written from the static memory to the auxiliary storage device and transferred to the dynamic memory.

Another disk caching scheme according to the present invention.

Store a copy of some data in the auxiliary storage device in memory,
In the disk cache method for improving the effective access speed of the auxiliary storage device by accessing the memory, a dynamic RAM and a static RAM are used as the memory.

When reading data from the host computer to the auxiliary storage device, it is determined whether the target data exists in the dynamic RAM or static RAM, and if it exists in the static RAM, the data is transferred from the static RAM to the host computer. If the data exists only in the dynamic RAM, it is transferred from the dynamic RAM directly or via the static RAM to the host computer, and if it does not exist in any RAM, the target data is read from the auxiliary storage device. After writing the data into both RAMs, the data is transferred from the static RAM to the host computer.

A disk cache system according to the present invention stores a copy of some data in an auxiliary storage device in a memory, and improves the effective access speed of the auxiliary storage device by accessing the memory. .

A first RAM with a large capacity and low access speed and a second RAM with a small capacity and high access speed are used to enable data transfer between at least the second RAM and the auxiliary storage device and the host computer. In addition, data transfer between the first and second RAMs is enabled.

[Operation] The storage device control device according to the present invention has a DRAM control section and an SRAM control section, and both RAM control sections control the DRAM and SRAM control sections, respectively, according to instructions from another control section.
access. At this time, the memory address of each RAM is given from the memory address control section. Further, the data control section mutually converts parallel data in the RAM and serial data in the auxiliary storage device, or switches and connects the data bus of the RAM to the auxiliary storage device side or the microprocessor side.

By providing the storage device control device of the present invention between a host computer and an auxiliary storage device, it is possible to construct a disk cache system that has both the large capacity of DRAM and the high speed of SRAM.

Furthermore, various data transfers such as those described below can be realized.

In other words, when transferring data from the host computer side or the storage device side, it is possible to write data to DRAM and SRAM simultaneously, and when transferring data from DRAM or SRAM to the storage device side, it is possible to write data from DRAM to SRAM or SRAM. Data transfer to DRAM can be performed simultaneously. Furthermore, the microprocessor in the storage device control device can also directly access DRAM or SRAM, and it is possible to transfer data from DRAM to the storage device and from SRAM to the host computer at the same time. M.P.
It is also possible for U to directly access memory. Furthermore, data can be transferred from the DRAM to the infant computer at the same time as data is transferred from the SRAM to the storage device, and the microprocessor can directly access the memory during this time.

Furthermore, by integrating the storage device control device or the buffer control section within this device into a single chip, the number of parts, wiring area, and board area can be reduced.

(Hereinafter, blank spaces) [Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a block diagram of a system in which SRAM and DRAM are connected to a storage device control device according to the present invention.

The storage device control device 1 includes DRAM3 and SRAM4.
are connected, and the storage device control device 1 controls data transfer between an auxiliary storage device (hereinafter simply referred to as a storage device) and a host computer (hereinafter simply referred to as a host) via these memories.

The storage device control device l is a microprocessor (hereinafter referred to as M
It has a built-in PU (PU) 2, which controls the system as shown in Figure 1. The A-1 bus is the MPU2's address bus, and the D-1 bus is the MPU2's data bus. The storage device control device 1 also includes a DRAM control section 5. It has an SRAM control section 6, a selector 7, a memory address control section 8, a data control section 9, and a control section 10. storage device controller],
The portion other than the MPU 2 constitutes a buffer control section.

As is well known, the DRAM 3 is a memory that can be written to and read out at any time and requires a memory content retention operation (refreshing), and the SRAM 4 is a memory that can be written to and read at any time and does not require a memory content retention operation.

Currently, the mainstream SRAM is 32K x 8 bits or 64 x 4 bits, and its acceleration time is about 15 ns. On the other hand, DRAMs are mainly 1 MX 1 bit or 256 K x 4 bits, and the access time is at most 80 ns. in this way,
DRAM has approximately four times the capacity of SRAM, and
RAM is about five times faster than DRAM.

The DRAM control unit 5 controls the DRAM 3 and
It outputs a row address strobe signal -RAS and a column address strobe signal -CAS for latching an address inside M3. Further, a read control signal -RD and a write control signal -WD to the DRAM 3 are output. Further, the memory address outputted from the memory address control section 8, which will be described later, is time-divided into row addresses and column addresses and outputted. The SRAM control unit 6 controls the SRAM 4 and outputs a read control signal -MRD and a write signal -MWR to the SRAM 4.

Note that in this specification and drawings, -'' represents negative logic, but it will be omitted in the following description.

Since the DRAM control section 5 and the SRAM control section 6 are well known, their specific configurations will not be described in detail here.

The memory address control unit 8 controls the DRAM 3 and the SRAM.
Internally, as shown in FIG. 5, memory address registers 81 and 82 for DRAM and SRAM are respectively provided. Furthermore, it has a selector 83 that selects either the output address of the register 81 or the address of the MPU 2, and a selector 84 that selects either the output address of the register 82 or the address of the MPU 2. In addition, for DRAM and S
By providing two (or more) memory address registers 81 and 82 for RAM, for example, D
It is also possible to transfer data at the 2nth address to the SRAM 4 while data at the nth address in the RAM 3 is being transferred to the storage device.

As shown in FIG. 5, in data transfer between the storage device and the memory, the data control unit 9 converts serial data from the storage device side into parallel data, and conversely converts parallel data from the memory side into serial data. It also has a serial/parallel converter 91 for converting the data bus of the memory into the data bus of the MPU 2 or the serial /parallel data converter 91
It has a selector 92 connected to one of the data buses.

The control unit 10 includes the above-described DRAM control unit 5, SRAM control unit 6, selector 7, memory address control unit 8. and controls the data control section 9.

In addition, as shown in FIG.
For the RAM control unit 6, DRAM3 and SRAM4
It has a wait (WAIT) circuit 101 that controls applying a wait to a cycle accessing.

Further, the buffer control section can operate with either the reference clock source of the MPU or the reference clock source of only the buffer control section, depending on selection by a selector (not shown). If the MPU's reference clock source can be used as is in the buffer control section, only one external crystal oscillator will be required, reducing the number of parts, board area, and cost. Furthermore, compared to the case where the buffer control section is operated using a clock source different from the reference clock source of the MPU, synchronization of control signals performed when the MPU accesses the buffer memory, for example, is not necessary. On the other hand,
If you operate with only the reference clock source for the buffer control section,
Since the reference clock source of the MPU is usually low-speed, this is effective when it is desired to access the buffer memory using a higher-speed clock.

The specific operation of the apparatus shown in FIG. 1 will be explained below.

As shown in FIG. 1, on the storage device controller.

After MPU2 decodes the host request command, MPU
According to the instruction No. 2, reading and writing are performed to the storage device.

The disk cache system writes the data transferred from the host side to the storage device and also writes it to the memory under the control of the MPU 2, so that the data that the host side wants to read next exists in the memory (
In this case, the cache is said to have been hit, and this ratio is called the hit rate), compared to reading data from the storage device, data can be transferred from memory, effectively allowing faster access to the storage device. .

In such a disk cache system, when SRAM is used as the cache memory, data transfer between the host side and the memory can be performed at high speed, but SRAM
The capacity for storing data in M is not so large, and the hit rate of the cache is naturally low. On the other hand, when DRAM is used as a cache memory, the cache hit rate becomes high because the data storage capacity of DRAM is larger than that of SRAM.

However, since the access time of DRAM is slower than that of SRAM, data transfer between the host side and memory is
This results in lower speed compared to AM.

Therefore, in this embodiment, the following operations are performed by the storage device control device 1. First, consider a case where the host outputs a request to read one sector to the storage device control device 1. In this case, the MPU
2, the data control unit 9 converts the serial data from the storage device side into parallel data, and then
After writing the contents into the DRAM 3 and SRAM 4 simultaneously and storing one sector worth of data, the one sector worth of data is subsequently transferred from the SRAM 4 to the host side.

This operation will be explained in detail.

In FIG. 1, when data transferred from the host side is stored in DRAM3 and SRAM4, when the host issues a read request for one sector of data,
MPU2 decodes the request and sends DRAM3 and SRA
6 or SRA which inverts the contents of the sector supplied to M4
Hit determination is performed on both M4 and DRAM3.

If the desired content is found in SRAM4 (i.e.

If the data is hit), the data is transferred from the SRAM 4 to the host. If SRAM4 is not hit and DRAM3 is hit, one of the following three methods is executed. The first method is.

The target content is directly transferred from the DRAM 3 to the host side. The second method is to first transfer data to the SRAM 4 and then transfer the desired data from the SRAM 4 to the host side. This method uses DRAM3
Since data is transferred from the SRAM 4 to the host side, it takes time to transfer all the data requested by the host side.

After data is transferred to SRAM4, the data can be transferred from SRAM to the host side at high speed.Compared to simply transferring data from DRAM3 to the host side, the time occupied by the host bus can be shortened, and the same data can be transferred again. When requested by the host side, it becomes possible to directly transfer target data from the SRAM 4 at high speed. The third method is D
At the same time as transferring from RAM3 to the host side, SRAM4
This is the way to transfer it to. With this method, when the same data is requested again from the host side, the target data can be directly transferred from the SRAM 4 to the host side at high speed.

If the desired data is not found in either SRAM 4 or DRAM 3, the data must be read from the storage device.

FIG. 2 shows the timing when data from the host side or the storage device side is simultaneously written to the DRAM 3 and SRAM 4. As the reference clock, the reference clock for the buffer control unit or the reference clock for the MPU is used by switching.

When reading data from a storage device 1. MPU2 is D
- DRAM in the memory address control unit 8 via the 1 bus.
The memory address is stored in the address register 82. This value is input to the DRAM control unit 5 via the A-2 bus. Next, the storage device control device 1 detects a sector designated by the host, and converts the data portion of the sector from serial data to parallel data using the data control unit 9.

When the control unit 10 recognizes from the C-2 signal that 8 bits of parallel data have been accumulated, the control unit 10 first
In order to enable access to the DRAM 3, an instruction to access the DRAM 3 is prompted by the C-3 signal. As a result, as shown in FIG. In order to output to the A-4 path side, the C-4 signal from the control section 10 is used to select and output the A-4 path side. Almost at the same time, the DRAM control unit 5
R for latching the row address inside DRA-M3
Outputs AS signal. Subsequently, the DRAM control unit 5
A control signal WR for writing data to RAM3 is output.

Next, the control unit 10 transfers the DRAM 3 to the DRAM control unit 5.
While validating the access to the SRAM 4, the C-5 signal prompts the SRAM control unit 6 to instruct the SRAM 4 to access the SRAM 4. continue,
In order to validate the contents of the SRAM address register that have been output from the memory address control unit 8 to the A-3 bus in advance, the A-3 bus side of the selector 7 is validated by the C-4 signal. At this time, the lower bits of the address input to the SRAM 4 are the same as the column address input to the DRAM 3.

Next, the DRAM control unit 5 transfers the column address to the DRAM 3.
Outputs a CAS signal for latching. continue,
The SRAM 11 section 6 outputs an MWR signal for writing data into the SRAM 4.

Here, for example, the SRA connected to the storage device control device l
Assume that M4 has an extremely fast access time compared to DRAM3.

DRAM control section 5 and SRAM $J control section 6,
Since they operate with the same clock source, if the clock frequency is used to match the cycle time of the fast SRAM 4, if the DRAM 3, which has a slow cycle time, is used, it cannot be accessed in one normal access cycle.

Therefore, in such an example, as shown in Figure 2, W
By applying weights to DRAM3 and SRAM4 using the AIT signal, the cycle time can be slowed down. That is, it becomes possible to access DRAM3 and SRAM4 simultaneously in the same access cycle.

The settings are determined by the C-1 output from the control unit 10 to the DRAM control unit 5 and the SRAM control unit 6, respectively.
This is done using the C-8 signal and the C-8 signal, and a wait can be applied while each signal is effectively output, making the above-mentioned simultaneous access possible in accordance with the cycle time of the DRAM 3 and SRAM 4.

By repeating such operations, r sectors worth of data from the storage device side can be written to the DRAM 3 and SRAM 4.

Next, from the storage device side, DRAM3 and SRAM4
The operation of transferring one sector worth of data written to the SRAM 4 from the SRAM 4 to the host side will be explained.

First, the control unit 10 sends the C-5 to the SRAM control unit 6.
The signal prompts an instruction to access the SRAM4. As a result, the SRAM control section 6 controls the memory address control section 8.
In order to select the contents of the SRAM address register output from the A-3 bus to the A-3 bus, the A-3 side of the selector 7 is enabled by the C-4 signal. Subsequently, the SRAM control unit 6
In order to transfer data to the host side, SRAM4
Outputs data read signal MRD to. By repeating these operations, one sector worth of data is transferred to the host.

The above is an example of a series of operations for transferring data from the storage device side to the host side. By performing such operations, the data transfer to the host side is Since the SRAM 4 is used for transfer, high-speed data transfer can be achieved and the time occupied by the host side bus can be shortened. Furthermore, compared to a system that uses only SRAM 4 as a cache memory, DRAM can be more effective as a disk cache by taking advantage of the fact that it has a larger data storage capacity than SRAM of the same price.

Next, an example of the operation when the host outputs a write request for one sector to the storage device control device 1 will be described.

In this case, one sector worth of data from the side to host 1 is transferred to the SR.
The data is written in the AM, and the data is transferred from the SRAM 4 to the data control unit 9, where the parallel data is converted into serial data and transferred to the storage device. Furthermore, data is transferred from the SRAM 4 to the DRAM 3 using the time during which parallel data is converted to serial data.

Figure 3 shows data stored in SRAM4
The timing when reading from M4 and writing to DRAM3 at the same time is shown.

First, the control unit 10 prompts the SRAM control unit 6 to instruct the SRAM control unit 6 to access the SRA-M4 using the C-5 signal. Subsequently, the contents of the SRAM address register of the memory address control unit 8 which have been outputted in advance are made valid at the output of the selector 7 by the C-4 signal. Furthermore, SRAM4
Data is written by outputting a data write signal MWR to the memory. These operations are repeated to complete data transfer for one sector. Thereafter, as shown in FIG. 3, the SRAM controller 6 outputs a data read signal MRD and transfers the data to the data controller 9. At this time, S
After the parallel data output from the RAM 4 is converted into serial data by the data control unit 9, there is some time until all bits are output to the storage device side. Utilizing this time, data is moved from SRAM4 to DRAM3.

In order to perform this series of operations, the control unit 10
It is necessary to output a delayed ride request to the M control unit 5 using the C-6 signal.

By performing the above operations, while SRAM4 is being used to transfer data from the host side to the storage device side, simultaneous transfer from SRAM4 to DRAM3 becomes possible, allowing SRAM4 to be used for high-speed data transfer. This means that the DRAM 3, which has a large data storage capacity, can be used as a cache memory.

Another case of data transfer is 1. For example, if the host side does not make any requests to storage device control device 1, during that time, storage device control device 1 receives the highest read request from the host side. If the data contents are stored in DRAM3, the contents are transferred from DRAM3 to SRAM4.
By simultaneously transferring the data to the SRAM 4, when the host side requests the data, the data can be transferred from the SRAM 4 to the host side at high speed.

This sequence operation is shown in FIG.

That is, data read from DRAM3 is written to SRAM'4 during the same cycle.

Furthermore, the storage device control device 1 has a built-in MPU 2 and an MP
It is possible for U2 to directly access DRAM3 and SRAM4, and the contents of DRAM address register 82 and SRAM are stored in memory address control unit 8.
The contents of the address register 81 or the address from the MPU 2 are selected by selectors 83 and 84 in the memory address control section 8 in response to the C-7 signal from the control section IO. Furthermore, selectively connecting the data bus of the memory to either the data bus of the storage device or the data bus of the MPU 2 is performed by a selector in the data control unit 9 in response to a C-9 signal from the control unit 10. 92. Therefore, by the selection operation of these selectors, M
It becomes possible for PU2 to directly access the memory.

As a refresh operation for retaining the memory contents of the DRAM 3, this supports a so-called CAS-before-RAS refresh mode, and periodically enters a refresh operation.

In addition, the storage device control device 1 controls whether the storage device side or the CDRAM
3 and SRAM4 while data is being transferred.
Using the time to convert serial data to parallel data, data can be transferred to the host side at the same time, and direct access from MP 0.2 to the system is also possible. Sara ↓ Two again. DRAM3 to SRAM4
Simultaneous transfer from SRAM4 to DRAM3 is also possible.

This makes it necessary to improve the priority order in data transfer.

Therefore, the priority order in data transfer will be described.

The highest priority is the refresh operation of DRAM3, which is to prevent the internal memory of DRAM3 from being destroyed.The highest priority is data transfer between the storage device and memory. , in the serial data/parallel data converter 91 inside the data control section 9.

This is because when serial data from the storage device side is transferred and 8 bits are accumulated, the parallel data must be output to the memory, otherwise there will be no register to store the next serial data. Next is when MPU2 accesses memory, and next is when DRAM3/SRAM4
The lowest level is data transfer between the host side and memory.

As described above, according to this embodiment, it is possible to perform simultaneous transfer between RAM and SRAM as in the example described above, and it is also possible to realize data transfer only in SRAM mode or only in DRAM mode. possible and DR
Programmable data transfer using AM and SRAM becomes possible, making it more effective as a disk cache system.

That is, DRAM and SR are included in the storage device control device.
By providing a control unit that simultaneously controls AM, it is possible to realize data transfer commensurate with the transfer speed of the host side, and moreover, it is also effective as a disk cache system.

Furthermore, by incorporating the storage device control device into one LSI, the number of parts, wiring area, and board area can be significantly reduced. In addition, by making the storage device control device a component of the hard disk controller board, , it is possible to construct a flexible hard disk system. Alternatively, by incorporating the buffer control section in the storage device control device into one LSI, there is an effect that various memory systems can be easily constructed.

[Effects of the Invention] According to the present invention, by using DRAM and SRAM simultaneously, highly flexible data transfer can be performed between the DRAM, SRAM, host, and auxiliary storage device, and this device can be used. enables programmable data transfer between the host and storage device,
It is possible to realize a disk cache system that combines the high speed of SRAM and the large capacity of DRAM.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG.
3 and 4 are timing charts showing the data transfer operation in FIG. 1, and FIG. 5 is a block diagram showing the detailed configuration of the main part of the first @. 1...Storage device control device, 2...MPU, 3...
DRAM, 4...S RAM, 5...DRAM control unit, 6...SRAM control unit, 7...Selector, 8...
...Memory address control section, 9...Data control section, 1
0...Control unit, 81.82...Memory address register, 91...Serial/parallel data converter, 1
01...Wait circuit.

Claims (1)

[Claims] 1. A storage device control device that controls access to an auxiliary storage device in response to instructions from a host computer, comprising: a first memory control unit that controls access to dynamic RAM; and a first memory control unit that controls access to static RAM. a second memory control unit that controls access to the dynamic RAM; a memory address control unit that outputs the access address of the dynamic RAM and the access address of the static RAM; the memory address control unit and the first and second memory control units; What is claimed is: 1. A storage device control device comprising: a control section for controlling a storage device control section; 2. In a storage device control device that controls access to the auxiliary storage device in response to instructions from the host computer, the microprocessor receives an access request from the host computer to the auxiliary storage device, and controls access to the dynamic RAM. a first memory control unit that controls access to the static RAM; a second memory control unit that controls access to the static RAM; and an access address of the dynamic RAM given from the microprocessor and the static R
a memory address control unit having first and second registers that hold access addresses of the AM; and a serial/parallel controller that mutually converts between the parallel data of the dynamic RAM and static RAM and the serial data of the auxiliary storage device. A data control unit having a converter; and a control unit that controls the first and second memory control units, the memory address control unit, and the data control unit in accordance with instructions from the microprocessor. storage device controller. 3. The storage device control device according to claim 2, wherein the data control section has a selector that switches and connects the data buses of the dynamic RAM and static RAM to the serial-parallel converter side or the microprocessor side. 4. In a disk cache method in which a copy of some data in an auxiliary storage device is stored in a memory and the effective access speed of the auxiliary storage device is improved by accessing the memory, a dynamic RAM and a static RAM are used as the memory. When writing data from the host computer to the auxiliary storage device, the data from the host computer is first written to the static memory, and the data is written from the static memory to the auxiliary storage device and transferred to the dynamic memory. Features a disk cache method. 5. In a disk cache method in which a copy of some data in an auxiliary storage device is stored in a memory and the effective access speed of the auxiliary storage device is improved by accessing the memory, a dynamic RAM and a static RAM are used as the memory. When reading data from the host computer to the auxiliary storage device, it is determined whether the target data exists in the dynamic RAM or static RAM, and if it exists in the static RAM, the data is read from the static RAM to the host computer. If it exists only in a dynamic RAM, transfer it from the dynamic directly or via the static RAM to the host computer,
If the target data does not exist in either RAM, the target data is read from the auxiliary storage device and written in both RAMs, and then the data is transferred from the static RAM to the host computer. 6. In a disk cache system that stores a copy of some data in an auxiliary storage device in memory and improves the effective access speed of the auxiliary storage device by accessing the memory, the memory has a large capacity and low access. A first RAM with high speed and a second RAM with small capacity and high access speed.
is used to enable data transfer between at least the second RAM and the auxiliary storage device and the host computer, and also to enable data transfer between the first and second RAM. Disk cache system.