WO1996031038A1 - Data transmitting method and transmission/reception circuit used therefor, and signal processor - Google Patents

Data transmitting method and transmission/reception circuit used therefor, and signal processor Download PDF

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Publication number
WO1996031038A1
WO1996031038A1 PCT/JP1996/000746 JP9600746W WO9631038A1 WO 1996031038 A1 WO1996031038 A1 WO 1996031038A1 JP 9600746 W JP9600746 W JP 9600746W WO 9631038 A1 WO9631038 A1 WO 9631038A1
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WO
WIPO (PCT)
Prior art keywords
signal
circuit
data
transmission
reference clock
Prior art date
Application number
PCT/JP1996/000746
Other languages
French (fr)
Japanese (ja)
Inventor
Tomonori Sekiguchi
Yoshinobu Nakagome
Takeshi Sakata
Takayuki Kawahara
Katsutaka Kimura
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP7/65442 priority Critical
Priority to JP6544295 priority
Priority to JP7/99201 priority
Priority to JP9920195 priority
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Publication of WO1996031038A1 publication Critical patent/WO1996031038A1/en

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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0008Synchronisation information channels, e.g. clock distribution lines
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/04Speed or phase control by synchronisation signals
    • H04L7/041Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L2007/047Speed or phase control by synchronisation signals using special codes as synchronising signal using a sine signal or unmodulated carrier

Abstract

The purpose of this invention is to realize high-speed data transmission by reducing the waveform distortion which occurs when binary digital data signals are transmitted through a transmission line. A sinusoidal reference clock signal (Ck1) is transmitted together with data signal (D1) synchronously modulated in amplitude. The modulated signals are received and demodulated according to the received clock signal to obtain the original data (Dr2). In the synchronous amplitude modulation, a sine wave (Vddq) having the same period and phase as those of the reference clock signal (Ck1) is modulated to have an amplitude larger or smaller than that of the signal (Ck1) depending upon the information (1,0) of the digital data. This data transmitting method can be used for data transmission between the microprocessor and storage device of a computer.

Description

Akira fine

[Name of invention]

Data transmission method, transmission used therewith, the receiving circuit device and a signal processing device

[Technical field〕

The present invention relates to a data transmission method, transmission used therewith, receiving circuit device and a signal processing device, further speaking rather to more, CP U (Central Processing Uni t, central processing unit) quit Lee down Note of Li such as definitive circuit device to signal processing apparatus connected by a transmission line such as a bus, regarding the configuration of the configuration and signal transmitting unit of the output circuit portion of the circuit device.

Background of the Invention

In recent years, large-scale integrated circuit (hereinafter, LSI and abbreviation) Ri by the advances of technology, operating frequency of the microphone and Russia process Tsu service (MPU) is 1 0 0 exceeds the MH z have been realized for the that. Also work 1 0 0 MH z or Oite in Note Li Thin click b eggplant-random 'A click Seth Note Li (DRAM) have been reported.

However, even come in speeding the LSI Chi Tsu VConnect of the circuit arrangement, in the signal processing apparatus of word over click Stacy tio N'ya personal co down computer or the like that uses an LSI is a Po Doreperu implementing the LSI, the call to speed to the speed of the LSI Ji Tsu Purebe Lumpur, Ru difficult der for the following reasons.

Signal transmission between LSI Chi-up of the circuit device of the above-described Yo I Do signal processing device, Roh down-Li te down, the pulse signal that by the zero (NRZ) code is used. When the wavelength of the harmonic components contained in this pulse signal tank becomes comparable to the wiring on the board, the behavior and the wiring is a distributed constant line, the signal wiring terminal or branched, LSI Pas Tsu cage it Oko a significant reflection due to the parasitic fin duct data Nsu ya parasitic key Yano Sita Nsu, the pulse waveform is the waveform distortion such as Li Ngin grayed raw Jill. Waveform distortion of this is the flame causes piece of speed.

For example, when transmitting signals between FIG 1 7 LSI Chi-up 1 I 2 on the board 1 7 0 Do you'll shown in (a) and 1 7 3, the equivalent circuit thereof cormorants good of (b) It can be expressed in. Internal circuit 1 7 8 LSI 1 7 2 are original function circuit, Chi also the output circuit 1 7 6 for converting the output of the internal circuit into a signal suited to the transmission line 1 7 1, LSI 1 7 3 transmission one also input circuit 1 7 7 that converts the received signal of the line or et al suitable signal to the processing of the internal circuit 1 7 9.

Also, Li one Zadoff frame and ball Ndi Nguwa Lee Ya like packages exists between the LSI and the transmission line, it is parasitic capacitance C and parasitic Lee emission duct capacitor Nsu L parasitic element 1 7 4, 1 with a 7 5. Although this in this input terminal is shows the case independent, if the input-output common, because the parasitic capacitance of the terminals Naru rather further large Oite the pulse transmission waveform distortion is Naru rather more sizes, conventionally used and which transmits the (output) circuit shown in FIG 8. Transmitting circuit 1 8 0 has an output stage 1 8 1, p MOS tiger emissions Soo data and n MOS Bok run-Soo data ing from the drive circuit 1 8 2, 1 8 3 and the output control circuit 1 8 4. IV 1 1 or al IV 1 5 or shows the I converter circuit in in FIG, NAND 2 is NAND circuit, NOR cis indicates NOR circuit. Output control circuit 1 8 4 signals D 0 e is the-out bets low Reperu, the O regardless output O ut the value of the input signal I n high Lee down impedance state. Signal D oe is-out preparative high level input signal I n and the same signal is output. Generally, preparative run-register the size of the pre-stage of the internal circuit 1 7 8 which generates an input signal I n is minor, because a large output stage 1 8 1 Tiger down Ges other size, and a drive circuit using the I converter column that was rather than the size the size of the tiger down register in gradually.

Shi Mi Interview Les transmission waveform when using the transmission circuit of Figure 1 8 - a waveform diagram of the sheet Yo emissions results shown in Figure 1 9. This Shi Mi Interview Les - in Mr. Yo down, was use the following conditions. Supply voltage, V dd power, '1. 5 V, V ss power,' is 0 V. Transmission line characteristics fin peak one dance and 5 0 Omega, and a length of 2 cm. Termination is a 0. 7 5 V, the resistance R tt of 5 0 Omega Roh Kkeji Lee Ndaku data Nsu L voltage V tt was 1 0 n H, the capacitance C is 5 p F. Output resistance of the output circuit is against the load of 2 5 Omega is about 2 2 Omega has gained amplitude Praz Smile eggplant 0. 4 V.

The waveform I 0 2 9 and〗 0 3 0 at the transmitting end and the receiving end of the feeder and transmitting the rectangular wave output circuit or et period 1 O ns was shown. This is because the data becomes "0, 1, 0, 1" in that you are transferred in cycle 5 ns. The transmitting end, the reflection at the receiving end is rather large, large Li down swinging is Ji live. Margin is for the voltage V tt minimum point of by that waveform re down Gin grayed when Ri rising signal Ri 0. 2 2 V der, which is 5 5% of the one side of the amplitude 0. 4 V . The minimum point of this is, as well as cormorants or to me drops below the voltage V tt, receiving circuit cormorant or to determine by mistake that it has received two of the pulse. Therefore, margin is the Most small, reliability in transmitting high-speed signals is reduced.

Also, disturbance of by that waveform multiple reflection, a plurality of receiving circuits into one transmission circuits of when you transmitted by via the bus becomes more noticeable. In word over click Stacy tio down and Paco Nalco down Manipulator Ichita like, Note re LSI is often a This used in the module configuration shown in FIG. 2 0 (a. That is, motherboard one tripod 2 0 0 main TIP re module 2 0 2 of the DRAM has a plurality placed Lee Nme mode Li 2 0 1 and, a plurality of SRAM 2 0 4 or Ranaru key catcher Tsu push from 2 0 5 is arranged. in this case, memory inter is connected Note Rivas 2 0 7 in common. 2 0 an equivalent circuit of (a) shown in FIG. 2 0 (b). one Note Li 2 0

4 pair and via a bus 2 0 7 plurality of memory elements 2 0 1 - 1-2 0 1 - 7 are connected. Note Li element 2 0 1 - 1-2 0 1 - 7, 2 0 4 in the LSI Chi-up,

And it is connected to the bus 2 cm intervals. Termination of bus 2 0 7 are shorted with a termination resistor R tt, is connected to a termination power supply (voltage V tt). 2 0 4 transmission LSI, memory element 2 0 1 - and 7 the receiving LSI - 1 ~ 2 0 1. All Note internal configuration of the Li element 2 0 1 one 1-2 0 1 one 7 although the same, clarity for memory element 2 0 1 - 7 only showing the internal configuration. Although this in this input and output terminals are shows the case of independence, when the input and output terminal is common, because the parasitic capacitance of the terminal Naru rather large, the disturbance of the waveform is carpenter Ri good.

Then the transmission circuit 2 0 8 of LSI 2 0 4 in Fig. 2 0, the stain Interview Reshi tio emissions result of the received waveform when the pulse transmission was rows summer with circuit 1 8 0 1 8 2 1. Send a square wave of period 1 0 ns from LSI 2 0 8, the transmitting end of the LSI 2 0 8, LSI 2 0 1 - 1, 2 0

1 one 4 and 2 0 1 - 7 each I waveforms at the receiving end of

0 shown in 3 1, 1 0 3 2 1 0 3 4 and 1 0 3 7. Large ringing occurs in the received waveform. 0 or margin Hawazu for the voltage V tt minimum point of Li Ngin grayed waveform. A 0 9 V. This is 2 2% of the one side of the amplitude 0. 4 V. This is because the multiple reflection occurs at parasitics and bus branches of LSI that is connected to the middle of Bruno scan.

Also, as the problem of high-speed data transmission, there is a problem of increase in power Roh size b. The data transmission that by the NRZ code between LSI, since the voltage of the output terminal at the time of transition data changes abruptly, the output circuit is required to charge the load capacity in a short time the transmission line. Change of Ri per unit time of the current flowing to the power supply for this is Ri Do rather than size, this is the Roh size b such as ringing in the parasitic Lee emissions duct data Nsu of the power supply pin of the LSI.

Et al is, in the high-speed data transmission, ski-menu between click lock and data is also a problem. Click lock in the conventional data transmission, the transmission of data, Remind as in FIG. 2 2 (a), the data transmission line 2 2 1 termination is not performed, the voltage on line is V dd or et V ss or swings. In this case, each tooth S 1 2 2 3 - 1, 2 2 3 - 2 ··· 2 2 3 - for click lock and data that will be supplied to the 8 are transmitted in the same direction, the scan key Yoo over the small bur, since the data transmission line 2 2 1 data and click lock transmission line 2 2 2 click lock and is transmitted in the reverse direction, skew that by the propagation delay on the transmission line There was faster arising data transmission rate, the click lock period is short Ku, since the relative proportion of scan queue for click lock period is increased, the time of latches data Thailand Mi Nguma - Jin is reduced. It should be noted that the 2 2 4 - 1 ... 2 2 4 - 8 transmission latches, 2 2 5 - 1 ... 2 2 5 - 8 receiving latches, 2 2 6 - 1 ... 2 2 6 - 8 CMOS Lee N'noku Ichita type transmitting circuit 2 2 7 - 1, ... 2 2 7 - 8 show a receiving circuit of a CMOS Lee down inverter type.

To solve this problem, as one of solutions Figure

Techniques using La Nbasui pointer-safe Esu shown in 2 3 are known. In its One in La N'no S w te monounsaturated E over be made public patent publicity flat 5 - it has been described rather than the more in 5 0 7 3 7 No. 4. 2 3 3 - 1, ... 2 3 3 - 8 LSI, 2 3 4 one 1 ... 2 3 4 - 8 transmit latches, 2 3 5 - 1 ... 2 3 5 - 8 receiving latches , 2 3 6 - 1 ... 2 3 5 - 8 NMOS open-drain type transmitting circuit, 2 3 7 - 1 ••• 2 3 7 - 8 differential type receiver circuit, 2 3 8 It shows the click lock source. In this Lee printer-safe Esu and partitioned returns Ri folding the click lock line 2 3 2, and a transmitting click lock the one used by the other as receiving click lock. Also, transmission data Den master 2 3 3 - 1, a plurality of slave 2 3 3 - 2 ... 2 3 3 - performed between the 8, the data transmission between slave not performed. Slave 2 3 3 - 8 or et al master 2

3 3 - 1 when transmitting data to, slave 2 3 3 _ 8 transmits data in synchronism with the transmission click lock, Ma is te 2 3 3 - 1 receiving click Lock You will receive the data in synchronization with the click, ing to the call data and the click lock is transmitted to the left direction. Conversely, the master 2 3 3 - 1 or we scan Rebusu Les chromatography Bed 2 3 3 - when transmitting data to the 8 data and click lock is transmitted to the right. Therefore, always for click lock and data are transmitted in the same direction, the scan queue is low reduced. There is a problem that the click lock terminal is increased in only to this resolution means.

Also, in order to realize high-speed data transmission in Lee printer-safe E over scan this, it terminates the data transmission line, § Figure 6-2 Operation Low type small amplitude Yi using open-lane transmission circuit and using the pointer-safe Esu. For this reason, the high-level signal is a constant value in the terminal voltage V tt, low-level is n MOS for pull-down field device characteristics (2 3 3 - 8 - 1 ... 2 3 3) Rajin-out Ya will be affected by the change. To suppress the influence of this, but controls the n MOS driving force for pull down the voltage of the low Reperu and off I one de carbonochloridate click, the control circuit is complicated, Ji-up you have problems with the surface product is increased.

DISCLOSURE OF THE INVENTION

The main purpose of the present invention, feed out the data transmission method that Ki out and this for performing data transmission between circuit devices constituting the signal processing apparatus at high speed with high accuracy and a method thereof, to provide a receiver circuit device it is O to this. In particular, the data transmission between LSI constituting the circuit arrangement of a signal processing apparatus such as word over click stearyl one tio Nyapa Sonaruko down computer, to suppress the rate of harmonic components including or being a transmission waveform of the data, data transmission method disturbance of the transmission waveform and transmits the converted into Ku has signal Ji live and transmitter circuit to be used therewith, is a this to provide a receiving circuit device.

A second object of the present invention can indicate whether a unit time changes in those Ri of the power supply current is reduced to a low polarization, to provide a circuit device having a row intends transmitting and receiving circuits less data transmission with Bruno size b it is.

A third purpose of the present invention, this that provides a circuit device having a transmitting circuit and a receiving circuit to reduce the scan queue between that Do a problem in high-speed data transmission click lock signal and the data signal it is when.

A fourth object of the present invention is O by this that provides a circuit device having a transmitting circuit and a receiving circuit large transmission that Ki de margin against your Keru output level to the small amplitude Lee printer off Esu.

The fifth purpose of the present invention, the signal processing data rate is that Ki de and this efficiently performed in the transmission line of one system the transmission of input and output signals of the circuit arrangement to handle different multiple data Ru der and child to provide an apparatus.

To achieve the above object, the data transmission method of the present invention, reference clock lock signal of the signal level one to digital Rude data (hereinafter abbreviated as simply data) to be a plurality of transmission signals at the transmission section constant period compared with the level, the de one data signal has the reference clock lock signal the same period, or amplitude compared to the amplitude of the reference clock locked signal I by the information of the data signal Oki signals representative of not smaller - is converted to (hereinafter modulation de data Ru and referred), and transmits to the receiver at the reference clock locked signal and the transmission line the modulated data signal. Hereinafter, abbreviated as sync amplitude modulation conversion of the data signal.

The receiver detects the difference between the amplitude of the modulation data and the reference clock locked received or al the transmission line, and demodulates the binary data signal of also.

Also, as the apparatus used in the data transmission method, a transmitting circuit apparatus that by the present invention, reference clock locked signal generator for generating a reference clock lock signal Ru sinusoidal der a constant cycle When a data signal source for inputting a data signal to be transmitted, the transmission of data to be signals the reference clock lock signal with the same phase, Chi also cycle, the information of the data signal amplitude to be transmitted the synchronous amplitude modulation circuit and the sync amplitude modulation circuit response Ji and into a signal that approximates a sine wave or sine wave even One of not smaller amplitude hear large compared to the amplitude of the sine wave of the reference clock-locking signal the a is modulated data and the reference clock-locking the output is provided a transmission circuit having an output terminal for outputting to the transmission line path.

Also, comparing the receiving circuit device that by the present invention is a receiving terminal for receiving the modulated data and reference clock locked, the large and small of the amplitude of the modulation data and reference clock-locking from the receiving pin a comparison unit to determine the magnitude (detector) is provided with a reception circuit having a demodulation unit for converting the output of the comparator based on the saved data is the signal.

Furthermore, the signal processing device that by the present invention is constructed by connecting the receiver circuit device, a transmission circuit device plurality and through the transmission line. Incidentally, the receiving circuit apparatus, including also the transmitting circuit apparatus Ru both the transmission and receiving circuits.

According to preferred correct embodiments of the present invention, when the data signal to be transmitted is a plurality of sequences, using a reference clock lock signal of frequency that differs for each sequence, the sync amplitude modulation for each sequence performed, a configuration for transmitting by frequency multiplexing. Also, the transmitting circuit apparatus and the reception circuit unit, to configure a single LSI with an internal circuit for processing data for each binary. Also, according to the another preferred correct implementation, the upper Symbol sinusoidal modulation circuit is synchronized with the data to be transmitted, the transmission should do data levels of click lock signal that is outside of the above SI configured cormorant by converting a sine wave having a level by Ri size squid small is not the level of the reference signal Tsu by the information. Oite to the above structure, the sine wave is strictly limited to the sine wave rather than also of the sine wave and the near similarity score is high waveform, including for example, even the harmonic component is small. Transmitting, receiving circuit device, including but not limited to, circuit elements are constituted by LSI, for example, Note Li, microstrip click b Pro Se Tsu Sa, the control circuit or the like.

Data transmission method and transmission of the present invention, by the reception circuit unit lever, since the waveform of the data signal transmitted is a waveform approximate to a small sine wave of harmonic branch pair and Transmission line to transmit the waveform and disturbance of parasitic elements such as compared to the rectangular wave multiple reflection occurs in the waveform is rather small, or a change in power supply current rather small, generation of Roh I's reduction in parasitic I Ndaku data Nsu supply pins It is. This is data from transmission method that by the present invention because of, feed, Ri by the and this to have use of the receiver circuit apparatus, a high Oite reliable especially high-speed data transmission enables high-speed data transmission.

These and other purposes of the present invention, structure and features will become more or bright et al in Tsu by the description of embodiments in connection with the following drawings.

BRIEF SurudoAkira OF THE DRAWINGS

Figure 1 (a) and (b) are respectively fed implementing one embodiment of Lud over data transmission method by the present invention, Ru waveform diagram der for configuration and operation principle description of the receiver.

Figure 2 is a circuit diagram of a transmitting circuit apparatus of Figure 1.

3 (a) and (b) is a waveform diagram for professional click view and operation described respectively the configuration of a sine wave click-locking the generating means for use in the above examples.

Figure 4 is a circuit diagram of the receiving circuit of Figure 1.

Figure 5 is a transmission that by the present invention, it is Thailand Mi Nguchiya one preparative illustrating the operation of one embodiment of a receiver circuit apparatus.

Figure 6 is sent that by the present invention are pro-click diagram showing a transmission circuit model for effective description of the receiver circuit apparatus.

Figure 7 is a diagram showing a one-to-one transmission and reception waveforms of the transmission showing a Walsh Mi Reshi Yo emissions result by the circuit model of FIG.

Figure 8 is a feed that by the present invention are pro-click diagram showing a transmission circuit model for effective description of the receiver circuit apparatus.

Figure 9 is a diagram illustrating a point-to-multipoint transmission of the transmitting and receiving waveform representing the I that shoe Mi Reshi Yo emissions result in the circuit model of FIG.

Figure 1 0 (a) and (b) is a truth table of Me another circuit diagram and description of another embodiment of each transmitting circuit device that by the present invention.

Figure 1 1 is a block diagram showing a transmission system for explaining another embodiment of a data transmission method according to the invention.

Figure 1 2 is a block diagram showing the structure of a co Npyu Ichita which is an embodiment of the by that signal processing apparatus according to the present invention.

Figure 1 3 is a pro click diagram showing a is another embodiment of the co-down computer configuration of a signal processing apparatus according to the present invention.

Figure 1 4 is a diagram showing a waveform diagram and a signal in the frequency domain of the signal used in the signal processor of FIG 3. Figure 1 5 is a circuit diagram of a full I filter used in the signal processing apparatus of FIG 3.

Figure 1 6 is a waveform diagram for explaining the operation of the signal processing apparatus of FIG 3.

Figure 1 7 is a view Subuguchi click view the configuration of a conventional pulse data transmission device.

Figure 1 8 is a circuit diagram of a signal circuit transmission in the conventional pulse data transmission device.

Figure 1 9 is fed by the conventional pulse data transmitting apparatus is a waveform diagram showing a received waveform.

Figure 2 0 (a) and (b) is a perspective plan view and an equivalent circuit diagram showing each main Lee Nme mode Li and model of the bus lines of the common signal processing device.

Figure 2 1 is a waveform diagram showing a reception waveform according to a conventional pulse data transmission device.

2 2 is a pro click diagram showing a configuration of a conventional data transmission device.

Figure 2 3 is a block diagram showing the structure of another conventional data transmission apparatus.

[BEST MODE FOR CARRYING OUT THE INVENTION

It will be specifically described below with reference to the accompanying drawings embodiments of the present invention.

Ingredients Example 1>

Figure 1 (a) and (b) is sent you implement by Lud over data transmission method of the present invention, respectively, Ru waveform diagram der for construction and operation principle description of an embodiment of a receiver circuit apparatus.

This example, 2 to a receiving circuit device constituted by the transmitting circuit device 1 or et plurality of LSI constituted by LSI - 1 ... 2 - 8 in sync amplitude-modulated data D 1 and reference clock locked C k 1 each transmission line 3 - 1 and 3 - 2 through the transmitting and. A plurality of receiving circuits device 2 - 1 - 2 - 8 since the same operation, hereinafter, the transmitting circuit device 1 and the receiver circuit unit 2 - data transmission between 1 (one-to-one transmission) Nitsu have to be described. In the figure, the transmission line 3 - 1 only one shown, but but it may also be in parallel of a plurality of lines. Also, the transmission lines 3 - 1 and 3 - 2 are electrical characteristics, the wiring patterns, are rather substantially like the load.

Transmitting circuit device 1 of the click lock transmitting terminal 5 and the reception circuit equipment 2 - 1 of click lock receiving terminal 6 transmission line 3 - is by re connected to 2. Similarly, the transmitting circuit device 1 of the data transmission terminal 7 and the receiving circuit unit 2 - 1 of the data reception terminal 8 transmission line 3 - is connected Ri by the 1. Transmission line 3 one 1, 3 - 2 at both ends are connected to a constant terminal potential V tt by a resistor R tt. Transmission line 3 - 1 and 3 - 2 are used to control the characteristics Lee down impedance is constituted by a microphone and Russia be sampled Li Tsu plug Lee emissions that by the multilayer substrate and is configured in the same wiring butter over emissions . Therefore, the transmission line 3 - 1 及 Beauty 3 - to receive the influence of 2 substantially similarly to Roh I's effect and signal delay, relative magnitude relationship between the reference clock locked C kl with modulation data D 1 is influence this and Do rather than the transmission of modulation data received is that Ki out.

Transmitting circuit device 1 has a transmitting circuit 9. Transmitting circuit 9 transmission line 3 - 3, 3 - 4 via respective receiving a click lock C kt sinusoidal click lock V ddq and Bruno pulse wave, an internal circuit (not shown) or the data D t 1 to be transmitted in al in Tsu by the synchronization amplitude modulation into a modulation data D 1. Click lock C kt in system clock lock is found added LSI Chi-up outside will be only obtained external clock locked source or al of the transmitting circuit apparatus 1, the internal circuitry of the transmission circuit device 1 also be added to, that controls the operation Timing of the internal circuit. Click lock V ddq the click lock C kt phase is substantially a match.

Referring to the operation of the transmitting circuit 9 to FIG. 1 (b), namely the principle of synchronous amplitude modulation will be described.

The click lock transmission terminal 5 is click lock V ddq is added through a fixed resistance 1 0 (resistance value R c 1). Sine Therefore, click locks C k 1 is obtained by dividing the click lock voltage V ddq sinusoidal in parallel connection resistance R tt of the terminating resistor, 2 and the fixed resistor 1 1 (resistance value R c 1) Ru signal der of the waves. The children of the signal and reference clock locks C t 1.

- How, click lock V ddq is added via a variable resistor 1 0 (resistance R dl) in the data transmission terminal 7. Supporting one in. The signal D 1 of the data transmission terminal 7 click Lock the voltage of the click V ddq R tt / 2 and the resistor 1 0 (resistance value R d 1) Ru signal Der divided sine wave. Variable resistance R dl of the resistor 1 0 is varied Tsu by the control circuit 1 2 Te 従Tsu the data D t 1 which is the output of the internal circuit. In particular, that Ki out and this changing of magnitude by comparing the amplitude of the data D 1 of the sine wave to the amplitude of the reference clock lock C kt. Ni will Yo of this, information of data D t 1, ie, "1", "0" depending on the two values ​​of the child to modulate the magnitude by comparing the amplitude to the amplitude of the reference clock-locking the is defined as synchronous amplitude modulation. . In FIG. 1 (b), the data D t 1 information force ヽ ' "0, 1, 1, 0,' is shows an der Ru example transmitting circuit 9 or we sent to the modulated de - data D 1 is reference clock locked C kl and equal Shii period, but with a phase and One by the contents of the amplitude-out transmission all data, the amplitude of the reference clock locked C k 1 every half rhino click Honoré Ri changes to the jar by Naru rather small phrase or size.

Receiver circuit apparatus 2 - 1, the receiving circuit 1 3 - with 2. Receiving circuit 1 3 - 2, the transmission line 3 - 1 and 3 - 2 and through the modulation data D 2 and reference clock are respectively terminals 8 and six et sync amplitude modulation Lock receive click C k 2 and it compares this is found by the comparator 1 4 one 1, the comparison result La Tchikai path 1 5 - Ri by the and this to latches 1, demodulates the original data D t 1. It is necessary to Tsu good to convert these to the NRZ signal. Figure 2 is a circuit diagram of a transmitting circuit apparatus 1 of FIG. 1. In this real 施例, transmitting circuit apparatus 1 is made up of a single LSI Chi-up. LSI Chi-up has a transmitting circuit 9 you the internal circuit 2 0 and the data D t 1 output der Ru NRZ code of the internal circuit 2 0 and input. Also, the LSI chip 1 DC power source V dd, V ss and sinusoidal click lock V ddq, click lock C kt pulse waveform of the rectangular wave Ru is supplied.

The internal circuit 2 0 click lock C kt and the DC power source V dd, V ss is applied. Since click lock C kt is the also determine the Thai Mi ring circuit operation, but also with a click lock C kt sinusoidal that Ri feet you wear in the determination of Thailand Mi ring, when defining the Timing of both or falling edge of di or falling edge of di edge click lock rising or falling edge of di and falling of will ho using pulsed click-locking but efficient Doo ing.

Data D t 1 which is processed in the internal circuit 2 0 is a NRZ code which is synchronized with the click lock C kt.

The transmitting circuit 9 n MOS preparative run-register (M nl, M n 2, M n 3) and p MOS preparative La Njisuta (M p 1, p 2, M 3) Ana were connected in parallel b Gusui Tsu Chi 2 1 2 2, 2 3 are provided. Ana b Gusui pitch acts as a resistor 1 0, 1 1 of FIG. 1, modulates the data D tl to the data D 1 modulated synchronous amplitude. Further, when you Ku Description bright-more, Ana b Gusui pitch 2 1, also because obtain reference clock lock C k 1, receiving a click lock V ddq source (de Rei down) terminal of that, reference clock Lock is configured Ri by a clause C k 1 to the n MOS us down register M n 1 and p MOS door La Njisuta M p 1 to output the de Tray emissions (source) terminal or et al. n MOS preparative run-register M nl voltage V dd to the gate one Bok electrode is added, the gate electrode of the p MOS tiger emissions g is te M p 1 fixed potential such as ground potential is Karoe. Accordingly, Ana b Gusui pitch 2 1 tigers emissions register M nl, p 1 acts as a sort of resistance element having a predetermined ON resistance thereof gate one Bok width, is re determined by the gate one Bok length etc. , and it outputs the click lock has small Ri by click V dd reference clock was Tsu also the amplitude lock C k 1.

Necessarily, although reference clock locked C kl not need to be a click Lock amplitude have small as against the click V ddq a comparison of sync amplitude modulated form and both signals modulated data D 1 and consider, it is convenient to form a click lock V ddq or al reference clock has a small amplitude lock C k 1.

Ana b Gusui pitch 2 2, 2 3, together with the EXNOR circuit 2 4 converts the output signal D t 1 of the internal circuit 2 0 modulated data signal D 1, which is synchronized amplitude modulation. The EXNOR circuit 2 4 and the output signal D t 1 of click lock C kt and an internal circuit 2 0 pulse wave is input, the signal click lock C kt and D negative output G 2 of the exclusive logical sum of t the issue. Or analog Gusui pitch 2 2, 2 3 Ana Russia Holdings I pitch 2 1 in the same manner as in n MOS door La Njisu data (M n 2, 3) and p MOS door La Njisuta (M p 2, 3) and There click lock V ddq is input to the source over the scan (de Tray down) electrode of each tiger down Soo data are connected in parallel, each door run-register of de Tray emissions (source) electrode or et al. It outputs a synchronization amplitude modulated data D 1. Also, the door to the La Njisuta gate electrode of M n 2 £ 1 ^ 0 1¾ circuit 2 4 of Deca pressurized tut is, the tiger down Soo data M p to 2 of gate electrode output of the EXNOR circuit 2 4 inverter IV 1 by Li inverted signal is applied to, bets are La gate electrode of the emission register M n 3 voltages V dd fixed potential is applied, the preparative run-register M p 3 gate the ground voltage V ss fixed potential is applied to one Bok electrode.

It should be noted, Ana Russia Gusui pitch 2 1, 2 2, 2 3 MOS tiger down registers that make up the (Μ η 1 ··· Μ η 3, p 1 ·· ■ ρ 3) is, between the outside of the LSI since production rose Tsu key in is part of a transmission circuit that affect, in Tsu by the and the child to the gate of the door length length Ku than that of the MOS door La Njisuta you are use to the internal circuit 2 0, characteristic of that Ki out and this little click the influence of roses luck.

3 (a) and (b) is a waveform diagram for the block diagram and operation described shows a configuration of each click lock generator that occur the click lock C kt and V ddq is there.

The click lock C kt and V ddq apparatus for generating is implemented on the board 3 0 same along with LSI transmitting circuit device 1. Apparatus for generating the click lock C kt is composed of a water crystal oscillator 3 1, apparatus that occur a click lock V ddq, in addition the output of the crystal oscillator 3 1 Ropasufu I filter 3 2 Te, the output of the mouth one Roh staple filter 3 2 and click lock V ddq. Russia Basufu Ri by mosquitoes Tsu Bokuo off frequency of Lee Noreta 3 2 and the child to be set in the vicinity of the fundamental frequency of the click-locking C kt, Remind as in FIG. 3 (b), Bruno Rusuku lock click lock V ddq of C kt phase and sine wave substantially synchronized is obtained.

Figure 4 is Ru circuit Zudea of ​​an embodiment of a receiver circuit device that by the present invention.

This embodiment is constituted by a single LSI Chi-up, the differential amplifier 4 1 and latches 4 2 - 1, 4 2 - 2 and the receiving circuits 1 3 with the output D of the receiving circuit 1 3 having an internal circuit 4 3 for processing the r 2.

Differential amplifier 4 1, reference clock locked C k 2 and sync amplitude la potential difference detection to the subsequent stage of the modulated data signal D 2 latch circuit 4 2 received - 1 and 4 2 - in the present embodiment supplies the 2, differential amplifier 4 1, its n MOS Bok run-register M n 4 and the data signal D 2 which receives the reference clock lock C k 2 of the sine wave to the gate electrode and receive Keru n MOS door run-register M n 5 to the gate electrode, n MOS Bok run-register! Vl n 4, and a load MOS we down Soo motor M p 4, 5 to be connected to the 5, n MOS preparative run-register M n 4, 5 the source electrode of the commonly connected to the n MOS preparative run-register It is configured Ri by the and M n 6. Et al is, the differential amplifier 1 is connected between the power supply voltage V dd and the fixed potential V ss, de Tray down electrode or these tiger emissions register M n 5, group Junku lock C k It outputs an output signal corresponding to a potential difference between 2 and data signal D 2.

Also, latches circuit 4 2 - 1, 4 2 - 2, n MOS preparative run-register (M n 7 forces, et M nl 2) and p MOS preparative La Njisu motor (M p 7 Kaka et M pl I Ri is configured in CMOS tiger is configured Ri by the 2) Nsufu § gate circuit and the inverter circuit (IV 4 ... IV 6). Also, the Bok La Njisu motor M p 7, M n 8, M n 9, M nl 0, M p 1 1, gate electrodes of M p 1 2, the signal of the reference clock locked C k 2 an amplifier circuit 4 4 for amplifying and shaping are supplied in through the delay circuit 4 5. DOO La Njisuta M n 7, p 8, M p 9, p 1 0, the M n 1 1, gate electrodes of M n 1 2, the inverted signal of the output of the delay circuit 4 5 inverter IV 7 There is supplied. Also, the output signal D m of the differential amplifier circuit 4 1 is supplied to the supply source. De Rei down electrode DOO La Njisuta M n 7, M p 7, M n 1 0, p 1 0, preparative La Njisuta M p 9, M n 9, M p 1 2, M n 1 2 of the source. de Tray down electrodes or data from D r 2 which is demodulated into NRZ code is supplied to the internal circuit 4 3 ing. Figure 5 is a waveform diagram for operation description of the transmission circuit and the receiving circuit of the first embodiment. Used for the explanation reference numerals used in FIGS. 2 and 4.

Also not a, a description of the operation of the transmission circuit. Sinusoidal click lock V ddq is Ru sinusoidal der width V pa vibration which vibrates about a fixed voltage V tt. The reference clock lock pin 5 of the transmitter circuit 9, a sine wave click lock V ddq is applied by passing the analog Gusui pitch 2 1. Door run-Soo data M nl 及 beauty M p 1 of the gate is Roh I § vinegar each voltage V ddq and V ss, Ana Russia Gusui pitch 2 2, Ru always on state near. Therefore, the click lock transmitting terminal 5, 6 although reference clock locked C kl of sinusoidal, is C k 2 appear, the amplitude V ck of that the amplitude V pa of analog Gusui pitch 2 1 the partial pressure value by the parallel connection of on resistance R 1 and the terminating resistor R tt.

Vck = Vpa- (Rtt / 2) / (Rl + Rtt / 2)

And analog Gusui Tsu Chi 2 3 The data terminal 7 is always in the ON state, is connected in parallel with it, a sine wave clauses through the analog Gusui Tsu Chi 2 2 that participates signal to gate lock V ddq is supplied. Therefore, although a sine wave appears on the data transmission pin 5, 6, the amplitude of Ana port Gusui Tsu Chi 2 2 changes the power sale good I'm crab follows is on-or off. Ana Russia Gusui pitch 2 2 is-out Oh Ru door in the off-amplitude V off is Ru Kima in the O-down resistor R 3 of the analog Gusui pitch 2 3. Vof f = Vpa- (Rtt / 2) / (R3 + Rtt / 2)

Analog Gusui Tsu amplitude V on the can and switch 2 2 is on the analyst b Gusui Tsu ON resistance R 2 of the switch 2 2, Ru Kima resistance value R 2 3 of parallel connection of R 3.

Von = Vpa- (Rtt / 2) / (R23 + Rtt / 2)

However, R 2 3 = R 2 · R 3 / (R 2 + R 3)

In here, in order to meet V on> V ck> V off, set the on-resistance of the analog Gusui Tsu Chi and R 3> R 1> R 2 3. Above, Ri by the analog Gusui pitch 2 2 on / O off, that Ki the amplitude of the sine wave data D 1, click lock C k 1 good Ri magnitude Ku or small phrases out with this .

Next, Ni would Yo described above describing control of analog Gusui pitch 2 2, click Lock using the difference in voltage click C k 1 and the data D 1, the data D t and the modulation to be transmitted in the NRZ code in order to correspond the data D 1, below cormorants the next control row, the NRZ code, "1" is V dd, "0" represents the V ss. First, click lock C kt is "1" in the click lock C kl, can the data D 1 is oscillated at the positive side is the magnitude of the two sine wave amplitude magnitude and voltage matching was because, in order to represent the data "1", "0", respectively, the amplitude of the data D 1 is V on, not good if V off. - How, click lock C kt force ヽ * "0" click lock C k 1 in, can the data D 1 is swing to the negative side, the reversal magnitude of the amplitude of the magnitude and voltage to reason, in order to display the data "1", "0", respectively amplitude data D 1 is the aforementioned state opposite to V off, and V on.

To perform the above control, Ru with EXN 0 R circuit 2 4. Circuit 2 4 outputs "1" to come two inputs and C kt and D t 1 gar 致, it outputs "0" to a different and come. Click Lock Ru added EXNOR of click C kt and the data D t 1 on the gate G 2 of switch's 2 2. Sweep rate pitch 2 2 n MOS the gate is connected directly to G 2, for p MOS the gate one I that is connected to G 2 and through the inverter IV 1, sweep rate pitch 2 2 the G 2 is "1" Deo and down, "off at 0. Therefore, click locks C kt force, '" 1 "in-out Noto Ri Do and G 2 = D t 1, data D t 1 force ヽ ' "1" Death Lee pitch 2 2 is on, "0,' I turned off by. Click lock C kt is "0" in-out Noto Ri Do and G 2 = D t 1 (D t 1 represents a negative signal D t 1), the data D t 1 force, ' "1" sweep rate pitch 2 2 is turned off, turned on at "0". Accordingly amplitude control mentioned above is realized. As this, EXNOR circuit 2 4 and the variable resistor and rather work with sweep rate pitch 2 2, 2 3 and Ri by the and this using, synchronization of the NRZ code split Ri those have the potential amplitude modulated signal and this is to output is that Ki out. Ri by a potential difference Di Sita Le signal magnitude relationship to the this assign, on the receiving side Ki out and this for demodulating a signal the synchronous amplitude modulated by a simple differential amplifier circuit and the like are conventionally known are that. Comparing reference clock lock C k 2 received (click lock C kl and the same) and (same as the data D 1) data D 2 by the receiving circuit 2, the differential amplifier 4 1, amplifies, and it outputs the door run-register M n 4 and the output signal D m corresponding to the potential difference supplied to the M n 5. The output signal of this D m is a rectangular NRZ code Do Let 's are shown in FIG. Remind as in FIG. 5, Ri good definition of the corresponding sync amplitude modulation wave and the NRZ code (split Ri person skilled in), the output signal D m is demodulated into NRZ code. Receiving click lock C kr of the demodulated signal rats Jiseul for this amplifies Ri by the reference clock lock C k 2 to the amplifying circuit 4 4, the delay of Ri by the delay circuit 4 5 Oh Ru in to the signal. Reference clock locked C k 2 is shaped while being amplified Ri by the amplifying circuit 4 4, is a rectangular pulse wave Do you'll shown in click lock C kr in FIG. Click for receiving to determine the Thai Mi ring of latches circuit 4 2 cormorants yo this lock C by kr to and this using a signal-like rectangle shape the sine wave Li La Tsu latch circuit 4 2 of Thailand Mi ring ∎ it can exactly determine. Also, the receiving click lock C kr are shorted with a delay circuit 4 5, since you form La Tchita I Mi in g of the subsequent La Tutsi circuit against the output signal D m 9 0 degrees (1 4 cycles) is the phase of the FIG signal. Using receiving click lock C kr, the output signal D m the latches 4 2 - 1, 4 2 - 2 latches to the signal D r 2 the demodulated output. Latches circuit 4 2 - 1, the inverter circuit IV 3, IV 4 and Bok run-register M n 8, La output signal D m and One by the positive retrace 遝経 path composed of M p 8 pitch to. Similarly latches circuit 4 2 one 2, inverter circuit IV 5, IV 6 and Bok run-g is te M n 1 1, p 1 1 output signal D m and One by the positive feedback circuit constituted by the the latches. First stage sweep rate pitch each latches circuit in this embodiment (M n 7, M p 7, n 1 0, M p 1 0), a positive feedback of sweep rate pitch (M n 8, M p 8, n 1 1, p 1 1) and an output stage of the sweep rate pitch (n 9, M p 9, M nl 2, p 1 2) by Ri configured, each Thailand ra Mi ring latch circuit 4 2 - 1 and latches circuit 4 2 - 2, and the sweep rate Tsu Chi each stage is configured to up to work alternately. Ri by the configuration described above, latches circuit 4 2 - 1 and 4 2 - 2 Gala Tsu Ji and output operations constitute power sale by performed alternately perform a high-speed operation. Note that the demodulated output signal D r 2 is supplied to the internal circuit 4 3 LSI 4 0, predetermined processing Ru is performed in the internal circuit 4 3. With the power supply voltage V dd and ground potential V ss is applied to the internal circuit 4 3, and determines the operation Timing of the internal circuit 4 3 is supplied Parusuku lock signal C kt not shown.

Also, Ana b Gusui Tsu MOS we Nji static constituting the switch (M n 4 - M n 6, M p 4, M p 5) affects but-out production Baratsu between the external LSI of the receiving circuit - because it is a part, is rather clause received a MOS door La and down the gate one Bok length compared to the register in Tsu by the length and Gusuru this-out characteristics Baratsu effect used in the internal circuit 4 0 be able to.

Mitsurui Te, illustrating the effect of this embodiment. The O Ri 1-one transmission to the data transmission apparatus of this embodiment shows a model when the Hare row in FIG. Click lock receiving terminal 6 4 of the transmitting circuit apparatus 61 of the click lock the transmission terminal 6 2 and the reception circuit unit 6 2 is connected Ri by the transmission line 6 6. Terminal 6 2, 6 4 as well as the presence of parasitic elements of the package between the heat transmission line 6 6, the transmitting circuit apparatus 61 of the data transmission terminal 6 3 and receiver circuit apparatus 6 2 data reception terminal 6 4 is connected to Ri by the transmission line 6 7. Termination of the transmission line 6 6 6 7 are terminated to V tt Ri by the termination resistor R tt. Pro click 9 Ri transmission circuit der which is shown in Figure 2, block 1 3 are the same configuration as the receiver circuit 1 3 is shown in Figure 4.

Figure 7 shows a sheet Mi Yu Le over sheet Yo down waveform that on the model of the signal transmission device of FIG. Shi Mi Interview Reshi ® emission conditions are the same as the conventional example Figure 1 9. , Respectively which in the transmission terminal 6 2 and 6 3 reference clock locked C k 9 and the modulation data D 9 is obtained. Receiving reference clock locked C k 1 0, also for the receiving modulated data D 1 0, the waveform disturbed rather name the magnitude relationship between the voltage and click lock C k 1 0 and the data D 1 0 that it has been kept. Received data D r 1 0 of the waveform D r 1 0 the transmission data is positive and rather Togawakaru this being demodulated. Figure 8 shows a model for performing by Ri to-multipoint transmission in the data transmission device of another embodiment. In here, LSI Chi-up of 8 1 transmitting circuit apparatus 8 2 - 1, ... 8 2 - 7 represent LSI Chi-up of receiver circuit device, click lock pin and the data terminal They are respectively independent transmission line 8 6,8 7 connected. Termination of the transmission line 8 6,8 7 are shorted with a termination resistor R tt, is connected to a termination power V tt. The reception circuit unit of the multiple is intended all the same, receiving circuit unit 82 in FIG - shows the internal structure only two. The configuration of the transmitting circuit apparatus 8 1 and the receiving circuit system 82 includes a transmission circuit unit 81 and the reception circuit unit 8 is Ji second configuration the same in FIG. 6, a description rather saving.

Figure 9 shows a sheet Mi Yu Le Shiyo down waveform by that signal to the transmission device model in Figure 8. Shi Mi Interview Reshi ® emission conditions are the same as the conventional example Figure 2 0. In FIG, C kl 1, C k 1 2, C kl 5, C kl 8 and D ll, D 1 2, D 1 5 D 1 8 each circuit device 8 1, 8 2 - 1, 8 2 - 4 8 2 - shows the 7 reference clock locked and stains Interview, single sheet Yo emission waveform of the modulated data. In each receiving end, the transmission waveform disturbed rather name magnitude of click lock and the data voltage is maintained. Demodulated data of the receiving circuit devices have also been demodulated to Ri if transmission data.

Can possible to get a Do effect would Yo follows according to the first embodiment. First, for transporting the re data by the sine wave or near the waveform, it is less disturbance of the received waveform. Because the sine wave is between sinusoidal or be added to al without the phase, even happening multiple reflection Den transmission line of the branch and the parasitic element, or the like, there is no Ji raw disturbance in waveform. Sync amplitude modulated signal changes the amplitude of time, complete but contain some harmonics for non-sinusoidal, the proportion when compared to the pulse wave has the small. The cormorants I mentioned in the prior art, disturbance of the received waveform is fundamental and reflection Oh Rui with 髙調 wave occurred in the difference of receiving how phase shift Luke et al, the sync amplitude modulated wave, compared to the pulse wave disturbance of the waveform is rather small with. Also, since the a reference clock lock and data information "1" in 髦圧 difference modulation data "0 and table, transmits the modulated data and the reference clock-locking even occur multiple reflections on the transmission line if the line Oke in the same conditions, modulated data is referenced to lock undergoes reflection on earthenware pots by the same, the voltage difference is or or transmitted stored, accurate data transmission can Ru.

Second, the current change of Ri was Oh unit time is not be small. This is harmonic has rather small in pairs to a pulse wave, the change in voltage is for gradual and Kana. Therefore, Roh Lee's that by the current change is also small rather than re-used to drive an external load, the raw Jill current change in the stomach Ndaku data down scan of the power supply terminal is reduced.

Thirdly, in the receiving circuit, it is easy Ru preparative reference clock Lock the click and data synchronization. That is, in the present embodiment, transmission in Shin circuit, dolphin et phase with the reference clock lock C k 1 and the data D 1 Ri by the and this dividing the sine wave V ddq occurred.

Fourth, Kagekanzashi the transmission circuit when configured with elements arranged in the same LSI Chi Tsu the flop, rather Ku to undergo Baratsu-out of the effects of characteristics between LSI devices, the come Baratsu the characteristics of the device is that Ki out data transmission without. Since the reference clock locked C k 1 and the data D 1 is Oite generated to the transmitting circuit 9 in the same LSI, the amplitude difference between the reference clock lock C kl and the data D 1 in device characteristics in the same LSI It is determined . Therefore, even with different device characteristics among the LSI Ri by the temperature change of the Rajin-out Ya operation if production of reference clock locked C k 1 and data D 1 to magnitude relation between the amplitude difference It does not give Kagetazuna. Hand, is-out Baratsu the element characteristics in the same LSI generally the same - LSI between Baratsu can very constituting the door Ru this and the I Li element characteristics roses embodiment for not be small compared to the Tsu Ru can be accepted in the Ku have data transmission of the key.

Ingredients Example 2>

Figure 1 0 (a) and (b) respectively show a truth table for the operation Description of the circuit diagram and circuit of another embodiment of a transmitting circuit apparatus that by the present invention. This embodiment, a transmit circuit and sends the transmitting circuit and the NRZ code to send the data in synchronization amplitude modulation signal provided, consists in earthenware pots by that for as needed using the both circuits Te toggle that. For example, if the high-speed data transmission is necessary, terminates the transmission line, and transmits the sync amplitude modulated signals, improved by re reliability and this you suppress the disturbance of the transmission waveform, low-speed data transmission If in sufficient, it has line transmission of NRZ code without termination of the transmission line, as possible out and this to reduce the power that has been consumption by terminating resistors.

In FIG. 1 0 (a), LSI Chi-up 1 0 0 of the transmitting circuit apparatus of the other internal circuit 1 0 1 operating power supply voltage V dd and ground potential V ss with accepted NRZ code, the transmission circuit 1 0 2 have a, in the et, with the transmission circuit 1 0 2 Ana port Gusui pitch 2 1, 2 2, 2 3, and the switching control circuit 1 0 3 with synchronous amplitude modulation and NRZ code. Analog Gusui tree with the same numbers for the circuit to the same components as those of the switch such Figure 2, saving rather detailed description.

Each analog Gusui pitch 2 1, 2 2, 2 3 Bok La Njisuta M n 2 1 constituting the, M p 2 1, M n 2 2, M p 2 2 M n 2 3, M p 2 3 sources ( the de Tray down) electrode Ana b Gusui pitch 2 1 force with positive Tsuruhaku lock V ddq is commonly supplied, Luo reference clock locked C k 2 1 sine wave is supplied , analog Gusui pitch 2 2, 2 3 or colleagues output signal D 2 1 that by the modulated data signal or NRZ code is synchronous amplitude modulation is selectively output.

Switching control circuit 1 0 3, a logic gate EXNOR 2 receiving the LSI 1 0 0 externally Rano ls e click lock C kt and data D t 2 1 Ru output der of the internal circuit 1 0 1, control signal a me, and oR circuits oR undergoing aND circuit aND 1 and the data signal D t 2 1 and the control signal a me undergoing D oe 1, an aND circuit aND 2 receiving an output signal of the circuit aND 1 and EXNOR 2 , the control signal D oe 1 the aND circuit the aND 3 receiving the output signal of 及 beauty oR circuit is constructed inverted signal and whether we NOR circuit NOR 1 where Ru receiving the output of the oR circuit of the control signal D oe 1.

Et al is, the output signal G 2 1 of the AND circuit AND 1 is supplied to the gate electrode of the preparative La Njisuta M n 2 1, inversion signal of that is supplied to the tiger down Soo motor M p 2 1. Also, the output signal G 2 2 of the AND circuit AND 2 is supplied to the gate Bok electrode bets run-register n 2 2, the inverted signal is supplied to the gate electrode of Bok La Njisuta M p 2 2. Output signals G 2 3 of the AND circuit AND 3 was or is supplied to the gate 耄極 bets run-Soo motor M n 2 3, supply of the gate electrode of the inverted signal Bok La Njisuta M p 2 3 It is. Output signals G 2 of or NOR circuit NOR 1 4, the data transmission terminal 1 0 4 and its source over scan de Tray down path MOS n connected preparative La Njisu data M n between the ground potential V ss It is connected to the gate Bok electrodes 2 4.

Switching control circuit 1 0 3, the control signal D 0 e 1 and the control signals A me signal will rows switching operating modes in. Based on the truth table is shown in Figure 1 0 (b) for explaining the operation of the switching control circuit 1 0 3.

At the beginning, the case out Kai enable signal D oel is "0 (mouth first level)", gate output signal G 2 1, ■ · ■ 2 4 all force of "0" to Do Ri, Ana Russia Gusui pitch for 2 1 ... 2 3 n MO preparative run-register M n 2 4 are turned off, reference clock locked C k 2 1, also to high emissions are impedance in the transmission data D 2 1.

Output Lee Ne one enable signal D 0 e 1 force, '' Ri by the signal A me For 1 (high level), for switching the sync amplitude modulation signal and NRZ code. Signal A me is "1" bets the can, data G 2 1 Ri Do to "1", sweep rate pitch 2 1 is turned on at all times. for the AND circuit AND 2 is opened rather, click the data G 2 2 lock C kt and D t 2 1 of the output was one preparative EXNOR is transmitted. Also, the output G 2 4 is "0 Do Ri, preparative La Njisuta M n 2 4 will always off Thus, sync amplitude modulation circuit is active one made, and this operation of the circuit of Ru added sine wave synchronized operation and equal Mr rather Li of the circuit of FIG. 2 of example 1, a sine wave click lock V ddq the click lock C kt in allowing the transmission of sync amplitude modulated signal. Ana port Gusui Tsu Chi in the output stage of the sync amplitude modulation circuit is likewise on resistance as in Example 1 are set.

Then, in-out signal A me is "0" Noto, the signal G 2 1 2 2 force, ' "0" and Do Ri, Ana Russia Gusui pitch 2 1, 2 2 is turned off. The signal G 2 3 data D t 2 1 signal G

The 2 4 data 'D t 2 1 is transmitted. Therefore, reference clock C click C k 2 1 is Ri Do in Nono Lee Lee emission peak one dance, the activated NRZ output circuit, and this for the sinusoidal click lock V ddq Ru added DC voltage in the signal D 2 1 data D t 2 1 its or until output allows transmission of a normal NRZ code. When using the circuit of this embodiment to the transmission circuit of Figure 1, when transmitting an NRZ mode, since click lock transmission pin 5 is high Lee down Bidansu, click lock C of the receiving terminal k 2 - C voltage of k 8 is Ri Do not constant at V tt, that Ki de be used to Re call to the or or reference voltage. Also, in the case of this, the transmission line 3 - 2, 3 - 1 of the terminating resistor at both ends but it may also be rather SeMMitsuru products.

Control signal A me of this embodiment, Ri enable signal der to control the transmission circuit 1 0 2 activity and non-activity, the transmission circuits 1 0 2 when applied to the die Na Mi click RAM in addition to the ∎ you can in this transgression to be formed on the door also the La I toy enable signal and the CAS signal, that Ki out and this also be formed signal or et al. and I enable the output of the LSI 1 0 0 outside . Also, the control signal A me is to send the output signal D 2 1 as the amplitude modulated signal, also that having a function of a mode signal for selecting whether to transmit the NRZ code Nodea Li, depending needs addition to being configured will Yo performs re Ri LSI 1 0 0 externally et signal receiving modes switching of, in advance mode prior to mounting of the blanking Li down Bok substrate such constant potential as a determined control signal a me is Ru can also be a call to configure cormorant'll be applied.

Et al is, the transmission circuit 1 0 2 of the present embodiment is connected to the transmitting end because of a function of the 髙I down pin one dance, the transmission line 1 1 0 Remind as in FIG. 1 1 each LSI (circuitry device) 1 1 1 ... 1 1 8 comprises both a receiving circuit 1 1 9 a transmission circuit 1 2 0, and the this to the click lock and transmit and receive terminals of the data in common can Ru. The transmission line 1 1 0 other LSI the signal subjected to the Hare Chi single LSI transmission of the connected LSI to D 0 e 1 to "0", the transmission circuit 1 2 0 to high emissions impedance state line received Te intends. In addition, it is also possible with the child that is responsible for transmission that by the NRZ code even in the case of this. Since the transmission circuit 1 2 0 to the cormorants good of this is composed of cormorants by a high-level emission peak dance, Ki out and the child to share a transmission terminal and the receiving terminal, Mr. decrease cutting the number of bottles LSI that Ki out of high-density mounting.

Incidentally, MOS preparative run-Soo motor M n 2 1 constituting the analog Gusui pitch - M n 2 3, M p 2 1 - M p 2 3 及 beauty M n 2 4 is in relation to the external LSI for field variability of device characteristics to influence, Ri by the and the children that rather than the size of the gate length than that of the M 0 N door La Njisuta to be used in the internal circuit 1 0 1, clause under the influence of the-out element Baratsu that Ki de Ku and children that make up the high-not output circuit reliability. <Example 3>

1 2 Ru block Zudea showing the configuration of an embodiment of by that signal processing apparatus according to the present invention. This embodiment is to apply the sending and receiving circuit apparatus of the present invention to a bus signal transmission in the Ah Turkey down computer signal processing apparatus ash.

Co down computer 1 2 0 port one de on the microphone B Burose Tsu Sa (MPU) 1 2 1, process Tsu Sa 1 2 SRAM for temporarily storing data and the like used in 1 (scan data tee Tsu click. random 'a click Seth' Note Li) 1 2 2, DRAM to play the role of the main Note Li you store the data (die Na Mi-click-random 'access' Note Li) 1 2 3, di scan click 1 2 4, di spray Lee 1 2 5 or the like is connected as an external storage device. Each individual component or circuit device described above, are connected by carbonochloridate Interface 2 6, MEMO Li Nokusu 1 2 7, I 0 bus 1 2 8.

Process Tsu Sa 1 2 1 and performs the transmission high-speed data between the calibration Tsu shoe 1 2 2, since key catcher Tsu shoe 1 2 2 constituting a small number of SRAM, as a form of data transmission Pro Se Tsu Sa 1 2 1 and the SRAM 1 2 2 the Roh Interface 2 6 connected directly to the one-to-one often become transmitted. Therefore, disturbance of even the transmission waveform during high-speed data transmission is that Ki de be used by that data transmission small fry compared to the bus, to the normal NRZ code. And force, while, during the pro cell Tsu Sa 1 2 1 and the SRAM 1 2 2 Because the transmission of high speed data is required, using a sweater transmission method that by the present invention. When using synchronous amplitude modulation Ru good in the present invention, since the flow steady disappearance 费電 flow and through the terminal resistor R tt Do Let 's are shown in Figure 1, the viewpoint et present invention vanishing 费電 force Ru can be a child to adopt a signal transmission that by the normal NRZ signal without employing a data transmission that. Also, using the NRZ code in order a high-speed transmission of data, and if Do you'll be adopted terminating resistor, synchronous amplitude modulation and the difference is less that I also present embodiment the power consumption of the viewpoint et al because, o to carry out by that data transmission method according to the present invention

- How, for data transmission between the key catcher Tsu shoe 1 2 2 and main Lee Nme mode Li 1 2 3, in order to configure the main Lee emissions Note Li in a number of DRAM, TIP Rivas 1 2 7 become bus transmission was through. Also, since the high-speed data transmission is required between the key catcher Tsu push from 1 2 2 and main Lee Nme mode Li 1 2 3 performs the onset bright data transmission method, high Mel reliability of data transmission .

Note Li bus 1 2 7, the bus adapter 1 2 9 and through IZO Roh force is connected to the Interface 2 8 ヽ ', 1 0 Roh scan 1 devices on the 2 8 (di scan click 1 2 4 , di scan-play 1 2 5, etc.) are relatively because a low-speed operation, used by that data transmission to the normal NRZ code. In the case of this that can in this transgression constituting Ri by the mounting substrate part which is shown in Figure 2 0 co down computer system described in FIG. 1 2 (Mazabo de) is 2 Roh scan 2 0 7 force of 0, 'corresponding to the Note Li Nokusu 1 2 7 is shown in Figure 1 2.

Ingredients Example 4>

Figure 1 3 is a block diagram showing a configuration of another embodiment of by that signal processing apparatus according to the present invention. This example data of a plurality of systems having different made in transmission rate to a bus in the co down computer a signal processing 裝 location transmitted by frequency multiplexing, the application of the sync amplitude modulation of the present invention for the transmission of its co down pin Yuta in use shown in FIG. those are process Tsu Sa 1 3 1, main Lee emissions Note re controller 1 3 2, di scan click device 1 3 3, the display device 1 3 4 and these It is composed of a bus 1 3 5 for transmitting data between a circuit device. The output unit intends line synchronization amplitude modulation and demodulation Ru good in the present invention the transmission circuit and the receiving circuit of each circuit device is provided.

Pro Se Tsu Sa 1 3 main control unit 1 3 1 one 1 Ru internal circuit Der 1, (in FIG. 3) a plurality of a different this processing speed inputs and outputs pulse data lines. Transceiver circuit 1 3 1 one 2, a modulation unit 1 3 1 one 3 to be output to the path 1 3 5 multiplexes respectively synchronous amplitude modulating the output data of the three systems, received from the bus 1 3 5 receive three modulation data having different transmission speeds, separated, demodulator for converting the di Sita Lud one data 1 3 1 - with 4. 1 3 1 - a, 1 3 1 _ b, 1 3 1 - c are both synchronous amplitude modulator, 1 3 1 - d, 1 3 1 - e, 1 3 1 - f Nozzle down de Nokusu off filter, 1 3 1 - 6 is a decoder.

Note Re controller 1 3 2, main Lee Nme mode Li 1 3 2 is an internal circuit - 1 and transceiver circuit 1 3 2 - with two. Transceiver circuit 1 3 2 - 2, 1 integrated output data in each sync amplitude modulation of the modulator section to be output to the bus 1 3 5 1 3 2 - and 7 modulation section - a and Dora Lee carbonochloridate 1 3 2 , receives the reception modulated data, vans converted to di Sita Rudeta Dopasu off I filter 1 3 2 - with demodulator of 6 - d and deco over da 1 3 2.

Disk device 1 3 3 Di scan click Control This setup B over La 1 3 3 is an internal circuit - 1 and transceiver circuit 1 3 3 - transceiver having two circuits 1 3 3 - 2 1 integrated output data the modulator unit 1 3 3 their respective synchronized amplitude-modulated output to the bus 1 3 5 - b and dry carbonochloridate 1 3 3 - received and 7 of the modulation unit, the received modulated data, converted into di Sita Rudeta van Dono staple Lee Rireta 1 3 3 - e and deco over da 1 3 3 - with demodulation unit 6.

Display device 1 3 4 includes a transmitting and receiving circuits 1 3 4 as its input-output circuit - with 2. Transceiver circuit 1 3 4 - 2, modulator unit 1 to output 1 integrates the output data to the bus 1 3 5 respectively synchronized amplitude modulation 3 4 - b and Dora Lee carbonochloridate 1 3 4 - 7 modulation section If, receives the reception modulated data, vans Dopasufu I filter 1 3 4 for converting the data - with the demodulator of f and Deco over da 1 3 4 one 6. Transmission line 1 3 5 in parallel lines, with the reference clock lock the transmission line and the data transmission line. Incidentally, reference clock lock generator is provided in the illustrated not bur, each circuit instrumentation S 1 3 1, ... 1 3 4.

FIG 4 (a) shows a sine wave of reference clock locked to be used for 3 data transmission system the transmission speed of the signal processing apparatus of FIG 3. The operation slow order of each circuit device Day scan click device (FD) 1 3 3, the display control unit (DCR) 1 3 4, and main Lee Nme mode Li (MM) 1 3 2 forward, reference clock b Tsu is the frequency of click split Ri those not. Figure (b) shows the range of frequencies devoted the split Li. For example, the 2 0 MH z ~ 3 0 MH z display control device about (DCR) 1 3 4 to 5 0 MH z ~ 1 0 about 0 MH z in to Disk device (FD) 1 3 3,, main Lee Nme Mo Li (MM) 1 3 2 to 1 5 0 H z ~ 3 0 0 Ru by dividing the degree of H z.

Figure 1 5 is Ru circuit Zudea showing a configuration of the bandpass off I filter. Roh down Dono staple Lee Soreta is a combination of Russia over Roh scan off Lee Noreta 1 5 0 L and the high Roh staple I Ruta 1 5 0 H is configured. Mouth one Bruno staple Lee Noreta 1 5 0 L and Nono Lee Bruno scan full I filter 1 5 0 H, respectively two child capacitor and (C, C 1, C 2) 1 5 1 a ~ 1 5 1 c, 2 One of the resistive element is composed of (R, R l, R 2) 1 5 2 a ~ 1 5 2 c and op emissions flop (OP) 1 5 3 a ~ 1 5 3 b.

In Ropasufu I filter 1 5 0 L, 2 two resistors 1 5 2 a which is connected to the input terminal 1 5 4 a or et series, the received data signal to an op down flop 1 5 3 a is input, an output terminal 0 (OUT) 1 5 5 a or al, is negatively fed back to the input of op amp 1 5 3 a. Also, it is connected to the middle of the capacitor 1 5 1 to via a 2 two resistors 1 5 2 a. Mosquito Tsu door off frequency f 0 of the furnace over Roh scan off I filter 1 4 0 L is,

1

2 π C 1 C 2 R

To become. Also, Q value Q is,

1 C 1

Q = - -

The 2 C 2.

Also, in Nono Lee Bruno staple I filter 1 5 0 H, the input terminal 1 5 4 b or al, and through two equal said go Nden Sa 1 5 1 c connected in series, op amp 1 5 3 b signal is input, a portion the output terminal 1 5 5 b or al, is negatively fed back to the input of the op-down flop 1 5 3 b. Also, to be connected to two child capacitor 1 5 1 c intermediate to via resistor 1 5 2 b.

Nono Lee carbonochloridate staple filter 1 5 0 H mosquito Tsu-off frequency f 0 of, 2 κ C \ - C 2 R

To become. Also, Q value Q is,

1 R 1

Q = - - -

2 R 2

To become. Ni will this Yo, low Ninety-nine staple I Ruta 1 5 OL and Nono Lee carbonochloridate scan off Lee Soreta 1 5 0 mosquitoes Tsu Bok-off frequency of the H is co-Nden support 1 5 1 a~ l 5 1 c and resistance 1 5 2 a~ 1 5 2 in Tsu by the value of c ∎ You can set. Figure 1 6 is a Thailand Mi emissions Guchiya one Bok showing an operation example according to the transmission circuit of the CPU definitive in FIG 3. Figure 1 3 send and receive circuit 1 3 1 - 3 of the modulator 1 3 1 - a, b, data S 1 of 髙 I order NRZ code frequency at c, S 2 and

The signal S 3, by using the sine wave of FIG. 1 respectively 4 frequencies f 1, f 2, and f 3 performs synchronous amplitude modulation, FIG.

1-6 modulation data fml, obtain fm 2 and fm 3. These modulated data fml, fm 2 and fm 3 are frequency multiplexed Tsu by the multiplexing circuit 1 3 5, it is transmitted as a signal to the bus 1 3 5. To Also contrary, the circuit device 1 3 2

1 3 3 and 1 3 4 or et respective modulated data fml, when fm 2 and fm 3 are output to the path 1 3 5, transceiver circuit 1 3 1 - 3 demodulator 1 3 1 - 4 van Dopasufu I filter 1 3 1 - d, separates the f and c in these, Deco - da 1 3 1 - 6 Tsu by the, the NRZ code to decode the S l, S 2 及 beauty S 3.

Above, cormorants I described with reference to FIGS. 1 3 to FIG 1 6, the signal processing apparatus of the fourth embodiment (co down computer) is provided with a multiplexer, a plurality of circuit devices having different operating speeds and CPU between, Runode to transfer signals by multiplexing, slow devices of signals operating speed, also signals of high operation speed device, ∎ you can at present on the same time on the same bus. Me other this, operating slower due to the device bus rather this Togana the operation of other devices are occupied is inhibited, multiple devices with different operating speed by using the same bus it is possible to speed up the system you are. In particular, if the stand performing synchronous amplitude modulation using sinusoidal waves, the multiplexing circuit can be realized by word Lee yard OR circuit, the frequency separation in the structure simple full I filter Do Let 's are shown in FIG. 1 5 can Runode, Ru can be easily formed on the LSI.

Also, rather good only bus 1 3 5 single one system, as compared with the prior art Ru a dedicated bus for each operating speed, has at rather small footprint, the portable signal processing device also of application it becomes easy.

Having described embodiments of the present invention, the invention is also limited to the above embodiments of the can rather than, Ru various changeable der without departing from the scope and spirit thereof. In Example, reference clock Lock has been described the example of transmitting the de one other 1-bi Tsu Bok every half rhino click Le clauses earthenware pots by transmitting data of 1 bit per site click Le it may be.

As a reference clock lock, rather than to be a sine wave Ru can that you use the pulse waveforms other than the waveform you approximate to it. In this case, although the high-frequency distortion some problems remain, for obtaining an external click lock V ddq or al reference clock locked C k 1 and modulated data D 1, reference clock locked C k 1 and the modulated data It is easy Ru preparative synchronization D 1. Et al is, click lock V ddq force of the external, since the shape formed using a circuit element arranged to al reference clock locked C k 1 and modulated data D 1 in the same LSI, the characteristics of the LSI Baratsu Kino Kagekyo to undergo rather Ku, that Ki out accurate data transmission is not Kage饔 to come Baratsu characteristics of the circuit elements.

Furthermore, when transmitting by multiplexing data of a plurality of systems shown in FIG. I 3, an example has been described in three systems, not even to be limiting for this number.

Claims

W required of range
1. And have contact to the data transmission method you demodulated in modulating the digital data Rudeta signal transmission all-out 2 value transmission section and transmitted by via a transmission line receiver, the digital Lud one data signal by the transmission unit levels compared to levels of reference clock-locking signal having a constant period, Ri amplitude depending on the binary information in the de I di data Rude data signal by the level of the reference clock-locking signal performed to that synchronous amplitude modulation converting the modulated data signal of atmospheric squid or small have voltage waveforms, in the transmission line, and transmits the reference clock-locking signal and the modulated data signals simultaneously, the receiving unit It said reference clock port Tsu have use a click signal you characterized that you demodulating the modulated de one data to digital data Rude data signal of the binary data transmission method.
2. The reference clock lock signal to the data signal and the same position phase, the same period as the even One sinusoidal waveform, amplitude the di di capacitor Le data of the modulated data signal a sinusoidal signal claim 1 Ki载 data transmission method which is characterized that you a signal that is controlled by the digital Rude data signal binary signal.
3. The digital data Rude data signal 2 values ​​Ri Oh the data of a plurality of systems the transmission rate that Do different, a plurality of modulated signals modulated by the transmitting unit performs frequency multiplexing to output sent to said transmission line data transmission method according to claim 2 characterized and this.
4. A signal source that occur a digital data Rudeta signal transmission all-out two values, and the reference clock lock signal generating circuit that occur even One reference clock lock signal a predetermined amplitude, said digital Rude data a sync amplitude modulation circuit that occur modulated data signal signal is converted to an amplitude of the magnitude against the level of the reference clock-locking signal, the reference clock locked signal and the modulated data signal transmission lines transmitting circuit apparatus characterized and this that having a terminal and also One transmitting circuit you output to.
5. The reference clock lock signal with even One signal a sinusoidal wave, and the modulated data signal is Tsu by the amplitude of the sinusoidal waveform digital Rude data signal binary information to variable transmission circuit instrumentation according to claim 3, wherein you characterized and this Ru signal der £.
6. The signal source is one internal circuitry der that processes the data signal, the internal circuit, the reference clock lock signal generating circuit and said sync amplitude modulation circuit formed on the same LSI Ji-up transmission circuit equipment according to claim 5 characterized and this.
7. The reference clock lock signal generating circuit order to that occur outside or al addition we first external clock port Tsu said reference clock-locking signal based on the click signal of the LSI Chi-up said is constituted by a first external clock-locking signal dividing resistance element you reduce the amplitude of said sync amplitude modulation circuit said digital Rude data signal response Ji to the first external clock information Lock transmitting circuit device according to claim 6 you characterized that it has been configured by the circuit for changing the amplitude of the click signal.
8. The transmission circuit further includes a first output circuit you output to the transmission line to digital data Lud one data signal of the binary to a pulse signal, the sync amplitude modulation circuit or the first circuit transmitting circuit apparatus according to any one 5- to claim you characterized and also one this switching control circuit for selectively driving the 7 of.
9. Digital data Rude data signal of the binary comprises that different Do plurality of data series in the transmission rate, the sync amplitude modulation circuit 及 beauty the reference clock-locking signal generating circuit corresponding to said plurality of data series to a plurality respectively provided, further a plurality of said sync amplitude output transmitting circuit apparatus of any one to seventh claims 5 you characterized that you circuit you multiplexed is added to the modulation circuit .
1 0. Reference clock Lock synchronization with click signal and the reference clock lock signal, the information of di Sita Rudeta binary signal is table with the magnitude against the amplitude of the base Junku lock signal modulation de - a terminal for receiving a data signal, a detection circuit that detect the magnitude against the amplitude of the reference clock Lock have use a click signal the modulation data signal or al the reference clock-locking signal, the receiver circuit apparatus also characterized one and this reception circuit converting circuit whether et ing that converts into di-di data Rudeta signal outputs a binary detection circuit.
1 1. The detection circuit is a differential amplifier shall be the input of the reference clock locked signal and the modulated data signal, characterized that you said converting circuit is constituted by latches circuit receiving circuit according to claim 1 0 shall be the.
1 2. Above the reference clock on the input side of the detector circuit lock signal and claim it characterized and this provided a full I filter which Ru passes the frequency components of the modulated data signal 1 0 or 1 1 receiving circuit according to.
1 3. And the receiving circuit, according to claim 1 0 or 1 1 you an internal circuit that processes the output of the receiving circuit, characterized that it has been composed of a single LSI Chi-up reception circuit equipment of.
1 4.2 value of de I di data Rude data first internal circuit and the binary di di motor Rudeta signal even One transmission circuit transmitting circuit circuit that converts the applied signal to a transmission for outputting a signal equipment and a receiving circuit device, Oite even One transceiver and a transmission line to connect the above transmitting circuit apparatus and the receiving circuit device,
A modulation circuit said transmission line having a first and second transmission lines, the upper Symbol transmitting circuit outputs the modulated de-di- data Rude data signal said first transmission line of the binary, the de Lee Sita synchronization with the Rude data signal, and the reference clock lock signal that have a predetermined amplitude possess a reference clock lock generating circuit you sent to said second transmission line, the modulation circuit is the digital the Rudeta signal consists Ni Let 's that cis converted to the modulated data signal representing the amplitude of the magnitude against the above reference clock-locking signal,
The reception circuit unit, the a receiving circuit connected to the first transmission line and said second transmission line, Chi also a second internal circuit Ru receives the output signal of the receiving circuits, the receiving that you circuit is configured Ni Let 's that converts the de I di data Le binary data signal corresponding to the amplitude of the magnitude against the modulated data signal to said reference clock-locking signal transceiver it characterized.
1 5. The signal transmitting and receiving apparatus, and et al, and external clock-locking generator that occur even Tsu first external clock-locking signal waveform of sinusoidal, the external clock locked occur the external clock-locking signal connects the circuit and the transmit circuit device have a third transmission line you supplied to the transmitting circuits device,
The reference clock-locking generation circuit and the partial pressure of the first external clock-locking signal is configured Let 's that occur the reference clock-locking signal,
To modulate the modulation circuit is the first external clock-locking signal amplitude de I di data Rude by Ri said di di capacitor Rudeta signal and this changing Ri by the information of the data signal of the binary transceiver according to claim 1 4 characterized that it has been configured Let 's that.
1 6. In the transceiver device is al, fourth chromatic above external clock lock generating circuit transmission line of an oscillation circuit you oscillating at a predetermined frequency, full I filter Li the oscillation output of the oscillation circuit possess a down Holdings Ru off I filter circuit, the output of the oscillator circuit, and through the fourth transmission path is supplied to the first internal circuit 及 beauty the modulation circuit, the full I filter the output of the circuit, transmitting and receiving apparatus according to 請 Motomeko 1 5 you wherein and the third call to through configured earthenware pots by being supplied to the reference clock lock generating circuit transmission paths .
1 7. The reference clock lock generating circuit, the first signal corresponding to the external clock locked in have a receiving Keru resistive element, the upper Symbol modulation circuit, the first external clock Lock receiving a signal corresponding to the click, and have a variable resistive element Li resistance value by the information of the de I di data Rudeta signal is variable, each of the said first and second transmission line terminating resistor There connected the reference clock lock generating circuit, a signal that corresponds to the first external clock lock outputs a signal voltage dividing Ri by the and and the terminating resistor the resistance element, the modulation circuit and features that you have made by the Hare configured you output a signal a signal corresponding to the first external clock-locking and re partial pressure due to the above variable resistive element and the termination resistor transceiver according to claim 1 6 you.
1 8. The modulation circuit is constituted earthenware pots by forces out by converting the magnitude of the voltage with respect to the upper Symbol reference clock lock signal the de I di data Rude data signal, the receiving circuit the reference clock Lock transceiver according voltages to any and this that having a differential amplifier circuit that compares Shi have a claims 1 to 4 shall be the features of claim 1 7 of the click signal and the output signal of the transmission circuit .
1 9. Microstrip click b Pro Se Tsu service and, the microphone B Pro Se Tsu The process first you store data that are use to the storage device and the first storage device and the first and second of and through the transmission line is connected, the first storage device you have been the first Ki愴 device even one signal processor and a second storage device which memorize the data to forward to the , have a transmission circuit you output data through the second transmission line,
The transmission circuit comprises Ni Let 's you output reference clock-locking signal that have a predetermined amplitude based on the external clock lock signal supplied externally et al to the second transmission line, signal processing apparatus characterized that it has been configured Let 's you output to the said second transmission line path as the data by changing the amplitude of the external clock lock signal.
2 0. The first storage apparatus comprises a scan data te I click run-Damua click Seth Note Li, the second storage device die Na Mi click run-Damua click cell scan MEMO Li in the signal processing apparatus according to claim 2 0 characterized that it has been configured.
2 1. The above microstrip click B profile Se Tsu Sa and the first storage device is connected through the third transmission line, said first storage peripherals, said third transmission line and through the configured Let 's you transmit Ki憧 been de I Sita Rude data signal, the de I di data Rude data signal is a signal corresponding to the magnitude of that voltage against the DC level It characterized and this output Te claims 1 9 or claim 2 0 signal processing according unit 2 2. the third and the above microstrip click b profile Se Tsu tHE and the first storage device fourth transmission line is tangent to via of the first storage device, reference clock locked signals that have a predetermined amplitude-out based on the external clock lock signal supplied externally et al to be with and to shape formed, the external clock □ click signal of by Ri the first come to and this that controls the amplitude Configured Let 's that form a di-di data Le signal δ himself 憶 the device
Said reference clock lock signal on Ji »4 the microstrip click port Pro Se Tsu is by the Hare configured supplied to support the de I di data Rude data signals through the transmission line, said first and through the third transmission line signal processing apparatus according to claim 1 9 or claim 2 0 you characterized that it has been by the Hare configuration supplied to the microstrip click b Pro Se Tsu Sa .
2 3. To the signal processing apparatus is al, an oscillation circuit that form a click lock signal you have a predetermined frequency, and this Ru said external clock locked signals a full I filter Li down Gus It possesses a full I filter circuit that form a external clock lock signal has less high frequency components compared with Li the click lock signal by the said click lock signal and the external clock locked signals the first storage device and a signal processing apparatus according to claim 1 9 or claim 2 0 you characterized and the second arc configured earthenware pots by being supplied to the storage device.
2 4. Performs signal processing, a plurality of signal processing Debai scan of a plurality of kinds of de I di data Rudeta signal transmission rate Tsu and through a single transmission line connected with the bus different and the di-di Oite the transmission and reception of data Rudeta signal to be One signal processing device line cormorant Ma Yi-click b profile cell Tsu support,
The microstrip click b Pro Se Tsu Sa is the data modulated and to that modulation unit modulates the de I di data Lud over data of the plurality of types and frequency multi duplex multiplexing you output to the transmission line and also Tsu first transmitting circuit section, you demodulation and separation unit you separate a plurality of kinds of data obtained by frequency-multiplexed input or al the transmission line, the modulated data cormorants strange Chi Yo Chi also a well Tsu first receiving circuit and a demodulator,
It said plurality of signal processing devices Noso respectively, the separation de I di data Rude data signal of a specific transmission rate in the data of the microstrip click port Pro Se Tsu support either et outputted more and off I filter you, and the full I filter output or al data demodulation to that the second reception even Tsu and demodulator circuit, you output by modulating the heat transmission all-out data to the transmission line One also a second transmission circuit this signal processing apparatus said.
PCT/JP1996/000746 1995-03-24 1996-03-22 Data transmitting method and transmission/reception circuit used therefor, and signal processor WO1996031038A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP7/65442 1995-03-24
JP6544295 1995-03-24
JP7/99201 1995-04-25
JP9920195 1995-04-25

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19707668A1 (en) * 1997-02-26 1998-08-27 Alsthom Cge Alcatel Method of testing of communication paths in digital communication networks
US6081550A (en) * 1997-02-26 2000-06-27 Alcatel Method of testing clock paths and network elements for carrying out the method
WO2003013091A1 (en) * 2001-07-27 2003-02-13 The Pulsar Network, Inc. Appartus for extracting a clock signal and a digital data signalfrom an amplitude modulated carrier signal in a receiver, whereinthe symbol rate either coincides with or is half of the carrier frequency
US7292629B2 (en) 2002-07-12 2007-11-06 Rambus Inc. Selectable-tap equalizer
US8634452B2 (en) 1999-10-19 2014-01-21 Rambus Inc. Multiphase receiver with equalization circuitry
US8861667B1 (en) 2002-07-12 2014-10-14 Rambus Inc. Clock data recovery circuit with equalizer clock calibration

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19707668A1 (en) * 1997-02-26 1998-08-27 Alsthom Cge Alcatel Method of testing of communication paths in digital communication networks
US6081550A (en) * 1997-02-26 2000-06-27 Alcatel Method of testing clock paths and network elements for carrying out the method
US9998305B2 (en) 1999-10-19 2018-06-12 Rambus Inc. Multi-PAM output driver with distortion compensation
US8634452B2 (en) 1999-10-19 2014-01-21 Rambus Inc. Multiphase receiver with equalization circuitry
US9544169B2 (en) 1999-10-19 2017-01-10 Rambus Inc. Multiphase receiver with equalization circuitry
US6771712B2 (en) 2001-07-27 2004-08-03 The Pulsar Network, Inc. System for extracting a clock signal and a digital data signal from a modulated carrier signal in a receiver
WO2003013091A1 (en) * 2001-07-27 2003-02-13 The Pulsar Network, Inc. Appartus for extracting a clock signal and a digital data signalfrom an amplitude modulated carrier signal in a receiver, whereinthe symbol rate either coincides with or is half of the carrier frequency
US7292629B2 (en) 2002-07-12 2007-11-06 Rambus Inc. Selectable-tap equalizer
US8861667B1 (en) 2002-07-12 2014-10-14 Rambus Inc. Clock data recovery circuit with equalizer clock calibration

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