JPH0574166A - Memory device and time base collector circuit - Google Patents

Abstract

PURPOSE:To enable responding to the altering of a memory capacity while simplifying circuit in the perimeter of the memory by performing a write/read accessing of a word line of a memory cell array through a word line access circuit for writing and a word line access circuit for reading both arranged in a shift register structure. CONSTITUTION:A data is inputted into a memory cell array 12 from an input buffer 21. An input clock corresponding to the input data is compared with a reference clock by means of a frequency comparison circuit 25 so that a writing clock corresponding to the resulting frequency difference is generated to be applied to a word line access circuit 22 for writing. In this manner, a word line WL is accessed sequentially to write the input data into a memory cell array 12. Then, the reference clock is applied to a word line access circuit 23 for reading and the word line WL is accessed sequentially to read out a data. This enables responding even to the altering of a memory capacity while simplifying circuits in the perimeter of a memory cell.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device and a time base collector circuit, and more particularly to a time base collector for inputting a signal containing jitter in the time axis direction and outputting a signal from which the jitter in the time axis direction has been removed. The present invention relates to a memory device and a time base collector circuit suitable for application to the above.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram of a conventional memory device, and particularly illustrates a case where the memory device is applied to a time base collector. As shown in FIG. 3, this device has a RAM section (random access memory section) 2 and a RAM control section 1 for controlling the RAM section. The RAM control unit 1 includes a write address counter 3 which operates by a clock 4W including jitter and a read address counter 6 which operates by a stable clock 4R from a crystal.
And an address control circuit 5 for sending an address 7, a chip select signal 8 and a read / write signal 9 to the random access memory section 2 based on the address signals from the write address counter 3 and the read address counter 6.
Have and.

On the other hand, the RAM section 2 receives an address 7 from the RAM control section 1, an address buffer 10 for decoding a row address from the address buffer 10, and a column address from the address buffer 10. The column decoder 13 and the memory cell array 12 to which an address designated by the row decoder 11 and the column decoder 13 is accessed
And a data control 16 for giving data of the data I / O bus 18 to the memory cell array 12 through the column decoder 13 at the time of writing, and a column decoder 1 at the time of reading.
3 to access the memory cell array 12 and derive data to the data I / O bus 18, and the data control 16 by the chip select signal 8 and the read / write signal 9 from the address control circuit 5. Circuit 1 for supplying control signals to the
4 and the chip select signal 8 from the address control circuit 5
And a logic circuit 15 for applying a control signal to the output buffer 17 based on the read / write signal 9.
Incidentally, the chip select signal 8 from the address control circuit 5 is also given to the row decoder 11 and the column decoder 13. Further, the output buffer 17 is selected by the chip select signal 8 at the time of reading,
When writing, the data control 16 is selected.

The operation of the above-described structure will be described below.

The clock 4W including the jitter, which is input to the RAM control unit 1, is given to the write address counter 3. Based on this, the write address when writing data to the memory cell array 12 is sent from the write address counter 3 to the RAM section 2 as the address 7.

The address 7 introduced into the random access memory unit 2 is input to the address buffer 10 and temporarily buffered. The row address is the row decoder 1
1, the column address is given to the column decoder 13. As a result, the row address of the memory cell array 12 is designated by the row decoder 11, and the column address of the memory cell array 12 is designated by the column decoder 13.

On the other hand, by the chip select signal 8 from the RAM control unit 1, the row decoder 11 and the column decoder 1
Selection / deselection of 3 is performed. Further, selection / non-selection of the data control 16 and the output buffer 17 is determined by signals output from the logic circuits 14 and 15 based on the combination of the chip select signal 8 and the read / write signal 9. The read / write signal 9 is applied to the logic circuits 14 and 15 so as to select either the data control 16 or the output buffer 17. As a result, it is possible to perform 2-port operation by switching by the address control circuit 5 at the time of writing data and at the time of reading data.

It is assumed that the data string input to the data I / O bus 18 is input according to the clock 4W including the jitter component. In this case, the write address counter 3 generates a write address based on the clock 4W including the jitter component, and the address 7, the chip select signal 8 and the read / write signal 9 are given to the RAM section 2 through the address control circuit 5. As a result, in the memory cell array 12, it is possible to write the data string in synchronization with the clock 4W including the jitter component, that is, by considering the jitter. Incidentally, writing of data from the data I / O bus 18 is performed through the data control 16.

On the other hand, it is assumed that the data in the memory cell array 12 is output to the data I / O bus 18 in synchronization with the stable clock 4R by the crystal, that is, as a data string from which jitter is removed. In this case, the read address counter 6 ensures a stable clock 4R from the crystal.
Generate a read address based on. Then, the address control circuit 5 gives an address 7, a chip select signal 8 and a read / write signal 9 to the RAM section 2. As a result, it is possible to read from the memory cell array 12 in synchronization with the stable clock 4R by the crystal, that is, to read a data string without jitter. Incidentally, reading of data from the memory cell array 12 to the data I / O bus 18 is performed through the output buffer 17.

Through the above operation, it becomes possible to remove the jitter component of the input data string including the jitter, and it is possible to configure a device such as a time base collector.

[0011]

As described above, in the conventional memory device, the RAM controller 1 receives the write address counter 3 to which the clock 4W containing the jitter component is input and the stable clock 4R by the crystal. The RAM section 2 is operated as a 2-port RAM by switching between the write address counter 6 and the address control circuit 5. Therefore, address setting and access to the memory cell array 12 are different systems at the time of reading and writing. Therefore, not only address control becomes complicated, but also the number of circuit elements and wirings increases,
The chip size becomes large when integrated into an LSI. Further, it is not possible to easily deal with the increase or decrease of the memory capacity, and the modification of each control circuit becomes very complicated.

The present invention has been made in view of the above,
It is an object of the present invention to provide a memory device and a time base collector circuit that realize a simplified circuit configuration.

[0013]

A memory device of the present invention includes a memory cell array having a plurality of memories for storing data, input means for adding input data to be written in the memory cell array to the memory cell array, and Output means for outputting data read from the memory cell array; an input clock corresponding to the input data;
The reference clock is compared with the frequency, write clock generating means for generating a write clock according to the frequency difference between them, and a plurality of shift registers are configured by cascade connection, at the time of writing, receiving the write clock, A word line access unit for writing, which sequentially accesses a plurality of word lines of the memory cell array, and a cascade connection of a plurality of shift registers.
Read word line access means for receiving the reference clock and sequentially accessing the plurality of word lines of the memory cell array.

The time base collector circuit of the present invention comprises an input means to which input data is added, a memory cell array having a plurality of memories for storing the input data, an input clock corresponding to the input data, and a reference clock. , And a write clock generating means for generating a write clock according to the frequency difference between them, and a cascade connection of a plurality of shift registers. The memory cell array receives the write clock at the time of writing. Write word line access means for sequentially accessing a plurality of word lines and a cascade connection of a plurality of shift registers. When reading, the reference clock is received to sequentially access the plurality of word lines of the memory cell array. The read word line access means for accessing and the memory And output means for outputting the read data as a time base corrector-processed data from Riseruarei configured as comprising.

[0015]

The input data can be added to the memory cell array via the input means. The memory cell array is accessed by the write word line access means. That is, the write clock generation means compares the frequencies of the input clock corresponding to the input data and the reference clock, and generates the write clock according to the frequency difference between them. This write clock is added to the write word line access means. As a result, the write word line access means sequentially accesses the plurality of word lines in the memory cell array, and the input data is written in the memory cell array.
A reference clock is applied to the read wordline access means. The read word line access means sequentially accesses word lines in the memory cell array to read data. The read data is output to the outside via the output means as the data subjected to the time base collector processing.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention. As shown in FIG. 1, the clock 4W including the jitter component and the stable clock 4R by the crystal are input to the frequency comparison circuit 25. As a result, the frequency comparison circuit 25 outputs the write clocks WCK and NWCK. On the other hand, a stable clock with crystal 4
Read clocks RCK and NRCK are generated from R. The word line WL for accessing the memory cell array 12 is connected with a write word line access circuit 22 and a read word line access circuit 23 having a shift register configuration. The write word line access circuit 22 is supplied with the write word line access start signal 24, and the write clock WCK,
The NWCK is configured to access the word lines WL one after another. On the other hand, the read word line access circuit 23 is supplied with the read word line access start signal 26, and the read clocks RCK and NRC.
It is configured to sequentially access the word lines WL by K. Data including jitter to the data input bus 19 is added to the memory cell array 12 via the input buffer 21. Read data from the memory cell array 12 is output to the data output bus 20 through the output buffer 17.

The operation of the above-described structure will be described with reference to the time charts (A) to (G) of FIG. By the way, the same figure (A) is a read clock RC
K, FIG. 7B shows the word line WL at the time of reading, FIG. 7C shows the word line WL at the time of writing, and FIG. 7D shows the first example WCK1 of the write clock WCK, and FIG. ) Is WCK which is the second example of the write clock WCK
2, (F) is the third example of the write clock WCK, WCK3, and (G) is the fourth example of the write clock WCK.
2 shows WCK4 which is an example of.

In order to control the word line WL of the input buffer 21, addressing is performed by separate serial shift registers of the write word line access circuit 22 and the read word line access circuit 23 at the time of reading and writing. .. Then, for the n word lines, the word line precharge is started from the point where the read and the write are deviated by 1/2 by the write word line access start signal 24 and the read word line access start signal 26. ..
That is, a 2-port line memory is configured. The write clocks WCK and NWCK supplied to the write word line access circuit 22 are generated by the frequency comparison circuit 25 based on the frequency comparison between the clock 4W including the jitter component and the stable clock 4R by the crystal. This write clock WCK, NWC
The word line WL at the time of writing data is determined by K.

When the clock 4W including the jitter component is equal to the stable clock 4R by the crystal, the write clock WCK is the write clock WCK2 of FIG. It becomes the write clock WCK3 of (F), and one word line is accessed per read / write cycle.

On the other hand, when the frequency of the clock 4W including the jitter component is higher than that of the stable clock 4R by the crystal, the waveforms of the write clock WCK are (E) and (F) according to the respective frequency differences. Write clocks WCK2 and WCK3 and (D) write clock WCK
The number becomes 1, and a cycle for accessing two word lines per read / write cycle appears.

On the other hand, a stable clock 4R by a crystal, and a clock 4W including a jitter component
When the frequency is low, the waveforms of the write clock WCK become the write clocks WCK2 and WCK3 of (E) and (F) and the write clock WCK4 of (G) according to the respective frequency differences, and read / write There is a cycle for accessing the word line one cycle before the cycle.

That is, the data including the jitter from the data input bus 19 is based on the write clocks WCK and NWCK generated according to the frequency difference between the clock 4W including the jitter component and the stable clock 4R by the crystal. , Is read from the input buffer 21 into the memory cell array 12. Then, the read clock R generated based on the stable clock 4R by the crystal
The data is output from the output buffer 17 to the data output bus 20 by CK and NRCK. In this case, the read clock RCK is read / read as shown in FIG.
One write cycle is generated, and the word line WL at the time of reading corresponds to this, as shown in FIG. On the other hand, as shown in FIG. 7C, the word line WL at the time of writing corresponds to the frequency difference between the clock 4W including the jitter component and the stable clock 4R due to the crystal. Therefore, as a result, the time base collector operation can be performed.

As described above, by changing the memory configuration for the time base collector operation from the RAM configuration to the 2-port line memory, the address control can be configured by only the shift register. Therefore, a complicated circuit around the memory becomes unnecessary, and the number of elements and the number of wirings can be reduced. Further, the increase / decrease in the memory capacity can be easily dealt with only by changing the number of stages of the word line access shift register at the time of reading / writing.

[0025]

As described above, according to the present invention, the word line of the memory cell array is written / read-accessed through the write word line access circuit and the read word line access circuit of the shift register structure. Therefore, the circuit around the memory cell can be greatly simplified, the chip area can be reduced even in the case of LSI, and the change of the memory capacity can be easily dealt with.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of the configuration of FIG.

FIG. 3 is a circuit diagram of a conventional example.

[Explanation of symbols]

 1 RAM control section 2 RAM section 3 Write address counter 4R Stable clock by crystal 4W Clock including jitter component 5 Address control circuit 6 Read address counter 7 Address 8 Chip select signal 9 Read / write signal 10 Address buffer 11 Row decoder 12 Memory cell array 13 Column decoder 14 Logic circuit 15 Logic circuit 16 Data control 17 Output buffer 18 Data I / O bus 19 Data input bus 20 Data output bus 21 Input buffer 22 Write word line access circuit 23 Read word line access circuit 24 Write word line access start signal 25 Frequency comparison circuit 26 Read word line access start signal

Claims (2)

[Claims] 1. A memory cell array having a plurality of memories for storing data, input means for adding input data to be written in the memory cell array to the memory cell array, and output means for outputting data read from the memory cell array. A write clock generating means for comparing the frequencies of an input clock corresponding to the input data and a reference clock and generating a write clock according to the frequency difference between them; and a cascade connection of a plurality of shift registers. And a write word line access unit for sequentially accessing a plurality of word lines of the memory cell array in response to the write clock at the time of writing, and a cascade connection of a plurality of shift registers. In response to the memory cell array, Sequentially accessing the word lines, the memory device characterized by comprising a lead word line access means. 2. The frequencies of an input unit to which input data is added, a memory cell array having a plurality of memories for storing the input data, an input clock corresponding to the input data, and a reference clock are compared. , A write clock generating means for generating a write clock according to the frequency difference between them, and a cascade connection of a plurality of shift registers, and at the time of writing, receives the write clock and sequentially operates a plurality of word lines of the memory cell array. A read word line, which is configured by a write word line access unit for accessing and a cascade connection of a plurality of shift registers, receives the reference clock at the time of reading, and sequentially accesses the plurality of word lines of the memory cell array. Access means and data read from the memory cell array Time base corrector circuit characterized in that an output means for time base corrector processing is output as the data subjected to.