JPH0343843A - Counter circuit - Google Patents

Abstract

PURPOSE:To facilitate the control of a counter circuit with smaller hardware quantity by dividing a counter into the higher and lower rank parts, using a register which holds the count value to form the higher rank counter, making the lower rank counter count a small number of bits and adding the carry of the lower rank counter to the higher rank counter. CONSTITUTION:A counter 20 counts up each event and an overflow signal if produced is set to a count-up request flag 21 for each event. The contents of a register file 24 are successively read out in each cycle and inputted to one of both inputs of an incrementer 26. At the same time, the contents of the flag 21 of the corresponding event are inputted to the other input of the incrementer 26 via a multiplexer 22. The incrementer 26 adds 1 to the contents of a register file only when the contents of the flag 21 are equal to 1. Then the result of addition is written into the registers of the same address in the file 24. Thus a counter circuit is easily controlled with the smaller hardware quantity.

Description

[Detailed description of the invention] [8! Regarding counter circuits that count multiple types of asynchronous events for each event, this counter circuit is provided for each event and counts the number of occurrences of the event, with the aim of providing a counter circuit that requires less hardware and is easy to control. a counter consisting of a small number of bits, a count-up request flag that receives carries from these counters and holds them, a multiplexer that selects the output of these count-up request flags, and a reset signal that is applied to the count-up request flag at a predetermined period. a control circuit that controls the selection of the multiplexer; a register file that is provided for each event and holds the upper bits of the counter as a count value; a register file that provides a pointer to the register file and controls the control circuit; It is constructed by a pointer generation circuit that provides a signal, an incrementer that adds the output of the multiplexer and the output of the register file at a corresponding address, and the result is stored at the corresponding address of the register file.

[Industrial Application Field] The present invention relates to a counter circuit that counts multiple types of asynchronous events for each event, and more specifically, in order to analyze the operating state of a computer system, the present invention relates to a counter circuit that counts a plurality of types of asynchronous events for each event. , relates to a counter circuit that counts various data during system operation.

Traditionally, counters of this type have been created as additional circuitry to the system. However, as computer systems have become more highly integrated in recent years, a variety of functions have been built into one VLSI, resulting in the problem that the operating state of a specific circuit cannot be recognized from the outside. For this reason, each V
In order to count the state of a specific circuit within an LSI, it has become necessary to incorporate a counter into the VLSt circuit.

[Conventional technology] FIG. 3 is a block diagram showing an example of a conventional circuit.

In the example shown in the figure, a counter 1 that receives an event count-up signal is provided for each event. Each counter 1 includes a register 1a that holds a count value, and an incrementer 1b that adds the value held in the register 1a and an event count up signal and holds the result in the register 1a. The degree of count value held by each counter 1 can be set by the required number of digits for each event.

FIG. 4 is a block diagram showing another example of the conventional circuit. In the circuit shown in the figure, the bits of the counter are divided into two fields, the lower bit field is stored in a hardware counter, and the upper bit field is stored in memory within the system. The part surrounded by the broken line is included in, for example, a VLSI, and a memory 10 that holds the upper bits of the count value for each event is provided externally. A counter 2 provided for each of a plurality of events counts up by one upon receiving an event count-up signal. The counter 2 is composed of a register 2a and an incrementer 2b as in the example shown in FIG.

The outputs of these counters 2 are sequentially switched by a multiplexer 3 and input to one input of an adder 4.

The other power of the adder 4 is connected to a memory 1 via a bus 5.
A count value within 0 is entered manually for each event.

In the memory 10, count values for each event from #O to #n are held. These count values are sequentially read out and added to the output of the counter 2 by the adder 4, and the result is stored again in the storage area at the same location in the memory 10.

In this method, the count value in the memory 10 is updated by a microprogram at intervals shorter than when the lower counter 2 overflows. Furthermore, the lower counter 2 is cleared at the time of reading, and the above-described operation is repeated for as many measurable vehicle images as possible.

[Problems to be Solved by the Invention] The method shown in FIG. 3 requires an incrementer for the bit width and a register to hold the count value for each measurable event, resulting in a problem that the hardware increases significantly. There is. On the other hand, in the method shown in FIG. 4, the incrementer requires only a few lower bits, so the amount of hardware is smaller than in the method shown in FIG. However, since an adder is required, and the upper bits of the count value are held in memory, it takes time to access them, and the width of the lower bits cannot be made very small.

Moreover, it is necessary to update the count value of each event at regular intervals, which poses a problem in that control becomes complicated.

The present invention has been made in view of these problems, and an object of the present invention is to provide a counter circuit that requires less hardware and is easy to control.

[Means for Solving the Problem] FIG. 1 is a block diagram of the principle of the present invention. In the figure,
A counter 20 is provided for each event and is composed of a small number of bits to count the number of occurrences of an event, a count up request flag 21 is held after receiving a carry from the counter 20, and a count up request flag 21 is provided for each event.
This is a multiplexer that selects the output of These counters 20 function as low-order counters that hold the low-order bits of events.

23 provides a reset signal to the count up request flag 21 at a predetermined period, and also outputs a reset signal to the multiplexer 22.
A control circuit 24 for controlling the selection of ζ is provided for each event.
A register file 25 holds the upper bits of the counter 20 as a count value; 25 is the register file 24;
A pointer generation circuit 26 provides a pointer to the output of the multiplexer 22 and a control signal to the control circuit 23;
This is an incrementer that adds the output of The output of the incrementer 26 is connected to a bus and read into, for example, a CPU via the bus.

The register file 24 is composed of registers #0 to #n for each event, and these registers hold the upper bits of the count value of the corresponding event. Further, if a RAM in the VLSI is used as the register file 24, all the circuits shown in the figure can be built into the VLSI.

[Operation] When each event is counted up by the counter 20 and an overflow signal (carry) is generated, the count up request flag 21 is set for each event. The contents of the register file 24 are read out sequentially every cycle and input to one input of the incrementer 26. The other input of the incrementer 26 receives the contents of the count-up request flag 21 of the corresponding event via the multiplexer 22.

The incrementer 26 adds 1 to the contents of the register file only when the content of the count-up request flag 21 is 1, and writes the result to the register at the same location in the register file 24. In this case, when selecting the lower counter 20, the corresponding count up request flag 21 is reset to "0°."
The number of measurable events m and the number of bits of the lower counter n are m
-2'', and when the number of measurable events is 16, the number of bits in the lower counter only needs to be 4, and it will be read once and reset before the count up request flag 21 is set next time. .

As described above, according to the present invention, only one bit of the count up request flag is sequentially switched and read from the lower counters 20, and the incrementer 26 can also update the count value.

Further, since the count value is held in the register file 24, it can be read and written every cycle, and all events can be updated in the minimum cycle. Furthermore, the register file 24 can have a much smaller hardware area than registers made up of flip-flops.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention. Components that are the same as those in FIG. 1 are designated by the same reference numerals. The illustrated embodiment shows a counter circuit capable of measuring 16 Fl events. In the figure, counter 20 is register 2
0a and an incrementer 20b, the event count up signal and the contents of the register 20a are incremented by the incrementer 20b, and the result is sent back to the register 20b.
It is designed to be held at a. The number of bits used in the register 20a is 4 bits.

The pointer generation circuit 25 includes a register 25m that holds a pointer value, and a counter 25b that updates the pointer value by 1 at a constant cycle. counter 25b
The count value is set in the register 25a again, and this sequence is repeated to update the pointer. The output of the register 25a not only indicates the register 24a for each event in the register file 24, but also provides a control signal of a constant cycle to the control circuit 23. Here, the register file 24 includes 16 registers 2 from #0 to #15.
It consists of 4a. Then, each register 24a has 3
It has a 2-bit configuration.

The control circuit 23 then controls the multiplexer 22 at regular intervals.
A reset signal is given at a constant cycle to the count-up request flag 21 for each event. As mentioned above, assuming that the register 24a that holds the count value has a precision of 32 bits, it is equipped with a register file 24 having a structure of 32 x 16 words, a 32-bit incrementer 26, and 16 lower modules (counters) 20. . Each lower module 20 includes a 4-bit register 20a, a 4-bit incrementer 20b, and a 1-bit count-up request flag 21. The operation of the circuit configured in this way will be explained as follows.

For each event, the counter 20 performs a count-up operation while the count-up request signal is "1". At this time, if the incrementer 20b exceeds 15, a carry occurs, and this carry is passed to the count up request flag 21.
held within. The output of each count up request flag 21 is input to a multiplexer 22. The multiplexer 22
is switched and controlled by a selection signal from the control circuit 23,
Read out sequentially. Here, count up request flag 2
After the contents of 1 are read out, it is reset by a reset signal from the control circuit 23.

Reading of the lower counter 20 is performed once every 16 cycles, and the count up request flag 21 is read. When this flag is "1", the count value in the corresponding register 24a in the register file 24 is determined by the pointer generation. The data at the address specified by the register 25a of the circuit 25 is read out, incremented by +1 by the 32-bit incrementer 26, and written back to the corresponding position in the register file 24. In this way, after the count-up request flag 21 is held for a maximum of 16 cycles, the control circuit 23
It is reset by a reset signal from.

Here, since a carry occurs only once every 16 cycles or more, in this embodiment, the lower counter 20 only needs to have 4 bits. After that, this operation is repeated for 16 events. Since the output of the incrementer 26 is connected to the bus, the count value for each event is read from the bus by, for example, the CPU.

[Effects of the Invention] As described above in detail, according to the present invention, the counter is divided into upper and lower parts, the upper counter is configured with a register that holds the count value, and the lower counter is configured with a register that holds the count value. By performing a counting operation and adding the carry of the lower counter to the upper counter, the count up can be done by an incrementer instead of an adder, and the hardware can be reduced. As described above, according to the present invention, it is possible to provide a counter circuit that requires less hardware and is easier to control.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention. FIG. 2 is a configuration block diagram showing an embodiment of the present invention; FIGS. 3 and 4 are block diagrams showing examples of conventional circuits. In Figure 1, 20 is a counter, 21 is a count up request flag; 22 is a multiplexer, 23 is a control circuit; 24 is the register file, 25 is a pointer generation circuit.

Claims (1)

[Claims] A counter (20) provided for each event and configured with a small number of bits to count the number of occurrences of the event, and a count-up request flag (21) that receives carries from these counters (20) and holds them. ) and a multiplexer (2) that selects the output of these count-up request flags (21).
2), a reset signal is given to the count-up request flag (21) at a predetermined period, and the multiplexer (22) is
); and a register file (24) that is provided for each event and holds the upper bits of the counter (20) as a count value.
a pointer generation circuit (25) that provides a pointer to the register file (24) and a control signal to the control circuit (23); ) and an incrementer (26) that adds the outputs of the outputs and stores the result at the corresponding address of the register file (24).