JPS62160529A - Data processor - Google Patents

Abstract

PURPOSE:To perform quickly an operation obtaining relations among data inputted in order, by not supplying clocks to a part of plural registers for data input in accordance with the status signal of an operator for pipeline processing. CONSTITUTION:Data X0, X1, ... are inputted successively to a register 2a in individual pipeline stages, and the same data are inputted to a register 2b one stage ahead. In each stage, set data Ai of the register 2a and set data Bi of the register 2b are compared with each other by an operator 1, and when a status signal 1s in the low level is outputted in case of Ai>=Bi. When the signal 1s is in the low level, the clock to be applied to the register 2a is suppressed in the next stage by a clock control circuit 3 to hold the contents of the register 2a, and the contents of the register 2b are updated with new input data, and maximum data is held in the register 2a finally.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device having an arithmetic unit that processes data by pipeline control.

[Conventional technology]

FIG. 3 is a block diagram showing the configuration of this type of conventional data processing device.
) are each data Ai with the addition of a clock.

This is a register for setting B1 and inputting these data to the arithmetic unit (1).

In FIG. 3, clocks are applied to registers (2a) and (2b) at the same time, and among them, register (2a)
The data AO, Al, A2,...e, Ai are
The register (2b) contains data BO, Bl, B2,
. . , Bi are each set once. Arithmetic unit (
In 1), the data in register (2a), that is, 2 pieces 1
Data Co, C1, C2, . . . showing the results of pipeline processing of the data sets.

Output C1.

[Problem that the invention seeks to solve]

In conventional data processing devices such as those described above, a pair of data set in registers (2a) and (2b) are processed in a pipeline each time a clock is applied, thereby significantly improving system performance. It's increasing. However, 1(n
It is not suitable for determining the relationship between data that is input at the same time, such as determining the maximum value or minimum value.

This invention was made to solve this problem, and aims to provide a data processing device that can perform high-speed calculations to determine the relationship between data, such as the maximum value and minimum value of sequentially input data. purpose.

[Friendly means of solving problems]

The data processing device according to the present invention includes a plurality of registers, an arithmetic unit that pipelines friend data set in these registers, and a clock that is applied to some of the registers by a predetermined status signal for the arithmetic result of the arithmetic unit. It is equipped with a clock control circuit that prevents the clock from increasing.

[Effect]

In this invention, in response to a predetermined status signal for the operation result in the previous pipeline stage, the clock control circuit suppresses the application of the data set clock to some registers, thereby preventing the data set from being applied to the next stage. Control the data input of the pipeline stages and find the relationship between data simply by repeating these operations.

〔Example〕

FIG. 1 is a block circuit diagram showing the configuration of an embodiment of the present invention, in which the same reference numerals as in FIG. 3 indicate the same elements. The difference from FIG. 3 is that a clock control circuit (8) is added to prevent the clock from being applied to the register (2a) in response to the status signal (1B) for a predetermined calculation result of the calculation unit (1). There is. The clock control circuit (8) is constituted by an AND circuit, and prevents the clock for data setting from being applied to the register (2a) when the status signal (1S) becomes 'L'.

The operation of the nine embodiments constructed as described above will be explained below with reference to the diagram of FIG.

First, data XO, Xi, X2, @ * @,
When determining the maximum value of Xl-1, Xi, Xi+1°..., data XO, Xi,
@m, X1-1. While inputting Xi, Xi+ll.@@, the same data is inputted to the register (2b) one stage earlier. In addition, the arithmetic unit (1) compares the set data A1 of the register (2a) and the set data B1 of the register (2b) at each pipeline stage, and
2 Outputs a status signal (1S) which is "L" when B is high and At(st), and moves on to the next process.

Here, in stage 1-2, data X1-2 is set in the register (2a) and data X1-1 is set in the register (2b), and X1-2 is set between these data.
(If there is a relationship of respectively) (1-1, Xi. At this time, if it is determined that there is a relationship of xl-1≧X1 between these data, the status signal (1S) is updated to 1.
It becomes “L”.

As a result, in the next stage 1, a clock control circuit (8
), the clock to be applied to register (2a) is suppressed, the contents of register (2a) are held as Xl-1, and the contents of register (2b) are updated to X1+1. At this time, data X1-1 and data X ill
When it is determined that there is a relationship of are added, and their contents are respectively X il
l, X is updated to i+2.

Such operations are performed using input data XO, Xi, X2 .・φ number.

Xl-1, Xi, Xi+1. If it is repeated as many times as ..., the maximum data will be held in register (2a), so
The maximum value can be determined by one cycle of calculation per input data element.

In the above embodiment, the case where the maximum value of sequentially input data is found is explained, but the configuration of the bar or clock control circuit (8) in which the status signal output from the arithmetic unit (1) is changed is also explained. By changing the data as appropriate, it is possible to perform high-speed calculations to find not only the minimum value of data input sequentially, but also the maximum and minimum values compared in absolute value.

Note that the above embodiment describes a data processing device equipped with two registers; however, in a device equipped with more registers, these registers are By adding a clock control circuit that prevents the data set clock from being applied to a part of the data, calculations for determining the relationship between data can be performed at high speed.

〔Effect of the invention〕

As is clear from the above explanation, according to the present invention, since the clock is not applied to some of the plurality of registers for data input by the status signal of the arithmetic unit that performs pipeline processing, A data processing device that can perform calculations for determining the relationship at high speed can be obtained.

[Brief explanation of drawings]

Fig. 1 is a block circuit diagram showing the configuration of an embodiment of the present invention, Fig. 2 is a diagram explaining the operation of the embodiment, and Fig. 3 is a block diagram showing one component of a conventional data processing device. It is a diagram. (1)...Arithmetic unit (2a), (2b)...Register (8)...Clock control circuit Note that the same reference numerals in each figure indicate the same parts, or t indicates corresponding parts.

Claims (2)

[Claims] (1) A plurality of registers, an arithmetic unit that performs pipeline processing on data input to these registers, and a data set for some of the registers in response to a status signal for a predetermined operation result of this arithmetic unit. 1. A data processing device comprising: a clock control circuit for suppressing application of an additional clock. (2) There are two registers, the arithmetic unit compares the set data of these registers, and the clock control circuit controls one of the registers in response to a status signal for a predetermined comparison result of the arithmetic unit. 2. The data processing device according to claim 1, wherein application of a clock is suppressed.