JPH04364525A - Parallel arithmetic unit - Google Patents

Abstract

PURPOSE:To operate computing elements efficiently in parallel and to process many data like a fuzzy set at a high speed by selecting inputs by multiplexers connected to the computing elements and performing basic arithmetic by the corresponding computing elements. CONSTITUTION:The parallel arithmetic unit consists of the basic computing elements 1-(n) such as an adder, a subtracter, and a multiplier, registers R1-Rn which hold the arithmetic results of the computing elements, and the multiplexers M11, M12,... Mn1, and Mn2 which input data Oj (j=1,...n) from respective registers. The computing elements 1-(n) are controlled with an operation command signal (cont.) from a controller and the multiplexers Mji are controlled with a selection command signal (sel.) from the controller. The computing elements 1-(n) can, therefore, select input data by the corresponding multiplexers. The respective registers R1-Rn are supplied with a constant clock signal from the controller.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel arithmetic device for efficiently performing operations on a large amount of data, such as fuzzy set operations, which are a combination of basic operations.

0002

2. Description of the Related Art In recent years, fuzzy theory has attracted attention as a useful method for handling ambiguity inherent in humans, and fuzzy arithmetic devices that perform information processing based on this theory have been studied. This arithmetic device is required to process at high speed a large amount of data expressed in fuzzy sets, which is an order of magnitude larger than normal digital arithmetic operations.

The following three methods are known as conventional arithmetic processing methods. (1) A method of processing by sequentially giving instructions to a single arithmetic unit like a general-purpose microprocessor.

(2) Pipeline processing in which a plurality of arithmetic units are connected in series, a register is provided between each arithmetic unit, and one operation is executed every clock.

(3) Parallel arithmetic processing in which a plurality of arithmetic units are arranged in parallel and operated simultaneously. One of the specific examples is shown in Figure 4.
As shown in the figure, a plurality of buses 1 to m are prepared for a plurality of arithmetic units 1 to n and one memory, and a common bus controller controls writing or reading from each arithmetic unit to the memory. This is a method to do so. The other method is to prepare a single bus for multiple arithmetic units 1 to n and one memory, as shown in FIG. This is a reading method.

[0006]

[Problem to be solved by the invention] However, the above (
According to method 1), speed-up cannot be expected because of sequential processing.

According to method (2), routine serial operations (for example, A+B+C) can be processed at high speed, but other operations require changing the procedure of each arithmetic unit, making it difficult to increase the speed. . In particular, in the case of fuzzy set operations, there are many types of operations compared to general digital operations, and the shape of the operations cannot be fixed, so there is a need for faster speeding in addition to routine operations. There is.

Further, according to the method (3), standard parallel operations (for example, A+B and C+D) can be processed at high speed, but there are the following problems.

In other words, in an arithmetic device in which a single memory is accessed by a plurality of arithmetic units as described above, operations are performed in parallel by the plurality of arithmetic units, but except for routine parallel operations, the memory is not accessed. Data transfer using the bus becomes an obstacle, making it difficult to increase speed. For example, for two input data A and B, (A+B)×(A-B)=
When performing an operation C, C is obtained by using three arithmetic units: an adder, a subtracter, and a multiplier. However, in order to do that, we need to add A+B using the adder and A+B using the subtracter.
-B, each result is sent to memory via the bus to hold the results of addition and subtraction, and then they are multiplied by a multiplier. data transfer, which takes time.

Therefore, an object of the present invention is to efficiently operate the arithmetic units in parallel when performing arithmetic processing using multiple types of arithmetic units, and to process large amounts of data such as fuzzy sets at high speed. The goal is to provide a device that can.

[0011]

[Means for Solving the Problems] A parallel arithmetic device of the present invention includes a plurality of arithmetic units, a plurality of registers that hold the arithmetic results of each arithmetic unit, and input data and input data from each register for each arithmetic unit. It is characterized by comprising a plurality of multiplexers that selectively input output data.

When the present invention is used for fuzzy set operations,
The arithmetic unit is configured to execute basic arithmetic operations used in fuzzy set arithmetic operations, and the multiplexer receives signals representing 1 and 0 necessary for fuzzy set arithmetic operations in addition to the input data. be done.

[0013]

[Operation] When input data is given, the input is selected by a multiplexer connected to an arithmetic unit that performs basic operations such as addition, subtraction, and multiplication to perform the desired operation on it. calculation is performed. The results are stored in a register connected to the arithmetic unit and sent to each multiplexer.

Next, a multiplexer connected to the arithmetic unit that performs the target operation selects the result of the arithmetic operation by the arithmetic unit, and executes the target operation. The results are stored in the corresponding registers and retrieved as output when needed.

When the above calculation is repeated, the previous calculation can be performed on the next data when the subsequent calculation is performed.

[0016]

Embodiment FIG. 1 shows the configuration of an embodiment of the present invention. This arithmetic device has a plurality of input data I1,...,Im
(in the illustrated example, m=2) and outputs a plurality of output data O1, . . . , On.

Its configuration consists of a plurality of basic arithmetic units 1 to n such as adders, subtracters, and multipliers, registers R1 to Rn that hold the arithmetic results of each arithmetic unit, and inputs for each arithmetic unit. A plurality of multiplexers M11, M12; M21, M22; which input data Ii (i=1, 2) and output data Oj (j=1, . . . , n) from each register;
...; Consists of Mn1 and Mn2. The number of multiplexers is determined by the number of input data and the type of arithmetic unit.

Each of the computing units 1 to n is controlled by an operation command signal (cont.) from a control device (not shown). Each multiplexer Mji is controlled by a selection command signal (sel.) from the control device. Therefore, each arithmetic unit 1 to n can select input data using a corresponding multiplexer.

On the other hand, each register R1 to Rn is supplied with a constant clock signal from the control device.

The operation of the arithmetic unit having the above configuration is as follows.

For example, for input data A and B, A+B
When performing the calculation -A×B, if an adder, a subtracter, and a multiplier are provided as calculation units, the calculation can be performed using the following procedure.

(1) A+B is executed by an adder and A×B is executed by a multiplier (parallel processing).

This is achieved by selecting inputs A and B with multiplexers connected to adders and subtracters, respectively. The results are stored in registers connected to the adder and subtracter, respectively, and are sent to each multiplexer.

(2) The results of the adder and multiplier are subtracted by a subtracter. This is achieved by selecting the results of the addition and multiplication with a multiplexer connected to the subtractor. The result is stored in a register connected to the subtracter and retrieved as output data when needed.

In this way, the calculation is performed in two steps. On the other hand, in conventional parallel processing, it is necessary to hold the result in memory for each operation, which increases the number of steps.

Furthermore, when repeating the above operation, (2
), the operation (1) can be executed on the next data.

For example, as shown in FIG.
A pair of data sequentially input from A1, B1; A2,
When repeating the above operation for B2 ; A3, B3 . When the operation (1) is executed and the operation (2) is executed at the next clock (CL3), the operation (1) can be executed on the next data A2, B2. Thereafter, calculations are performed on the input data in the same way, so the speed is much faster than conventional parallel processing.

FIG. 3 shows an example of the configuration when the arithmetic device of FIG. 1 is used for fuzzy set operations.

This arithmetic unit has four arithmetic units, namely an add/subtractor (Add/Sub.) 11, a multiplier (Mul.) 12, and a Min. /Max includes an arithmetic unit 13 and an arithmetic logic unit (ALU) 14. The arithmetic logic unit (ALU) 14 performs arithmetic operations such as addition and subtraction, AND,
Perform logical operations such as OR.

On the input side of each arithmetic unit, there is a pair of input data for inputting three input data A, B, and C, signals representing 1 and 0 necessary for fuzzy set operation, and output data from registers R1 to R4. multiplexers Mj1, Mj2 (j=1
,...,4) are provided. On the other hand, on the output side of each arithmetic unit, there are provided registers R1 to R4 and a multiplexer 15 that collectively outputs their output data O1 to O4.

According to the arithmetic device shown in FIG. 3, by combining four arithmetic units according to the arithmetic expression, operations often used in fuzzy set operations, such as A+B-A×B 1 ∧ A+B (∧ is Min operation )0 ∨
A+B-1 (∨ is Max operation) can be executed in one clock.

Although the embodiments have been described above, the present invention is not limited thereto. For example, the number and circuit configuration of the arithmetic units, registers, and multiplexers constituting the arithmetic device can be arbitrarily set as long as they realize the arithmetic function of the present invention.

[0033]

[Effects of the Invention] As described above, according to the present invention, arithmetic units can be efficiently operated in parallel and a target operation can be executed with the minimum number of steps, so that it is possible to process large amounts of data such as fuzzy information. Even in this case, it is possible to achieve high-speed calculation processing.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing an example of an arithmetic processing procedure according to the configuration of FIG. 1;

FIG. 3 is a diagram showing a configuration example when the arithmetic device of FIG. 1 is used for fuzzy set calculations.

FIG. 4 is a diagram showing the configuration of a conventional arithmetic circuit using a plurality of arithmetic units.

FIG. 5 is a diagram showing another configuration of a conventional arithmetic circuit using a plurality of arithmetic units.

[Explanation of symbols]

1 to n...Arithmetic unit, R1 to Rn...Register, Mji...
Multiplexer, 15...Multiplexer, I1, I2
, A, B, C...input data, O1~On...output data.

Claims (2)

[Claims] Claim 1: A parallel arithmetic device that executes a combination of basic arithmetic operations, including a plurality of arithmetic units, a plurality of registers that hold the arithmetic results of each arithmetic unit, and a plurality of registers that hold input data and each arithmetic unit for each arithmetic unit. A parallel arithmetic device comprising a plurality of multiplexers that selectively input output data from a register. 2. The arithmetic unit is configured to execute basic operations used in fuzzy set operations, and
2. The parallel computing device according to claim 1, wherein the multiplexer receives, in addition to the input data, a signal representing 1 and 0 necessary for fuzzy set computation.