JPS62194541A - Arithmetic circuit - Google Patents

Abstract

PURPOSE:To easily perform such anomalous calculations as (A+B), (A+B+1), (A-B) and (A-B-1) by controlling at least the carry input of the lowest stage in an addition/subtraction circuit. CONSTITUTION:The addition data received from addition circuits 51-5n are supplied to a register 6 together with the control signal received from a control bus 4. Then the addition data are read out to a data bus 1. Then the data received from the bus 1 are supplied to a 1-bit register 7 together with the control signal received from the bus 4. Thus the data on 1 or 0 is written to the register 7. The data received from the register 7 is supplied to the carry input of the circuit 51 of the lowest stage. Therefore the operation (A+B) is carried out when the data written to the register 7 is equal to zero. Then the operation (A+B+1) is carried out when the data received from the register 7 is equal to 1. Thus the anomalous calculation can be carried out just by supplying 0 or 1 to the lowest carry input.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an arithmetic circuit used in a digital signal processor or the like.

[Summary of the invention]

The present invention relates to an arithmetic circuit that performs addition and subtraction, and by controlling at least the carry input at the bottom stage, A+B and A+
B+1. This allows irregular calculations such as A-B and A-B-1 to be easily performed.

[Conventional technology]

For example, in a two-input adder circuit, an output of A+B can be obtained for inputs A and B.

In that case, if an output of A+B+t can be obtained in addition to the output of A+B, it can be effectively used for various processing in a digital signal processor or the like.

However, in order to perform such an operation of A+B+1, conventionally it was necessary to prepare a numerical value such as B+1 in advance, or to provide a configuration that further adds 1 to the addition output, but this cannot be easily performed using software or hardware. I couldn't.

By the way, in an adder circuit, for example, if the calculation result exceeds the number of digits of the circuit, a so-called carry signal indicating a carry is output.

When performing multi-digit arithmetic, this carry signal is supplied to the higher-order digit arithmetic circuit to perform the carry operation. Therefore, when performing multi-digit arithmetic, multiple arithmetic circuits are provided, and the carry IJ+ output of each arithmetic circuit is sequentially connected to the carry input of the arithmetic circuit of the most significant digit. Since a carry from the lower order is not possible, the carry input is grounded.

The inventor of the present application has focused on this point.

[Problem that the invention seeks to solve]

Conventional circuits have had problems such as not being able to easily perform irregular calculations such as A+B+1.

[Means for solving problems]

The present invention provides one or more addition or subtraction circuits 51)...
In the arithmetic circuit composed of the above-mentioned addition or subtraction circuit, 1- is arbitrarily applied to the carry input of at least the bottom stage 6υ.
! This is an arithmetic circuit that can supply (register (7)) data of 0 or 0 (register (7)).

[Effect]

According to this, by controlling the carry input of the lowest stage, the irregular calculations of A+8+1 and A-B-1 can be executed extremely easily.

〔Example〕

In the figure, the data from the data node (1) is supplied to the register +21 (31K, and the control
Predetermined control signals from each bus (4) are sent to register f2.
1 f31, and data A and B to be added are respectively written to register (2) f31. Addition circuit t! for each predetermined digit corresponding to the written data A and B! 5D (52...(5n)).

In these adder circuits (51) (52...(5n), the carry output of the lower digit is supplied to the carry input of the next higher digit, and this K constitutes a multi-digit adder circuit. Circuit 51) 53...(5n)
The added data is supplied to the register (6) K, and a predetermined control signal from the control path (4) is supplied to the register (6), and the added data is supplied to the data/9 path (1). is read out.

Furthermore, data from the data bus (1) is supplied to a 1-bit register (7), and the control path (4
) is supplied to the register (7), *1. Data n or 0'' is written to register (7). Data from this register (7) is supplied to the carry input of the lowest adder circuit 61).

Therefore, in this circuit, when the data written in the register (force) is 'fO', the calculation of KA+B is performed as in the conventional case, and when the data in the register (7) becomes 1',
An operation of A+8-+-4 is performed.

In this way, the irregular calculations of A+B and A+B+1 are performed, but according to the circuit described above, only "0" or "1" is supplied to the lowest carry input, so it is extremely easy to perform the irregular calculations. can.

In the above example, a 1-bit register was provided, but one bit of any data register may be used instead.

Further, although the above example describes an addition circuit, in the case of a subtraction circuit, irregular calculations of AB and A-8-1 can be executed.

〔Effect of the invention〕

According to this invention, by controlling the carry input of the lowest stage, the irregular calculations of A+B+1 and AB-1 can be executed extremely easily.

[Brief explanation of drawings]

The figure is a configuration diagram of an example of the present invention. (1) is datanos, f2) (3) (6) (7
) is a register, (4) is a control path, 51) 52
...(5n) is an adder circuit.

Claims (1)

[Scope of Claim] An arithmetic circuit comprising one or more addition or subtraction circuits, wherein data of 1 or 0 can be arbitrarily supplied to at least a carry input at the lowest stage of the addition or subtraction circuit.