JPH02178833A - Adder for adding data different in bit length - Google Patents

Abstract

PURPOSE:To minimize the hardware constitution to increase the operation speed by using an adder adapted to a smaller data size. CONSTITUTION:An adder 13 adapted to a smaller data size of data to be calculated and a plus one circuit 15 whose data size corresponds to the difference in the number of digits between data having a larger data size and that having the smaller data size are provided. When data to be handled are different in data size, the adder executes addition as data having the smaller data size, and one is added to remainder higher digits of data having the larger data size on demand. Thus, the operation speed is increased and the hardware constitution is simplified.

Description

[Detailed Description of the Invention] (Summary) Regarding an adder that adds data of different bit lengths, which handles addition data and augend data that have different bit lengths of binary numbers, an adder that matches the smaller data size is used. With the aim of minimizing the hardware configuration and increasing the operating speed, we created an adder whose data size matches the smaller of the data sizes of the data to be calculated. , a plus 1 circuit having a data size corresponding to the difference in the number of digits between large and small data sizes, and either the data that has been plus 1 by the plus 1 circuit or the original data that has not been plus 1. The circuit includes a selection circuit for making a selection, and an AND circuit for ANDing the carry output of the adder and the carry output of the plus 1 circuit and outputting a carry of addition data.

[Industrial application field]

The present invention relates to an adder that handles addition data and augend data having different binary bit lengths, and adds data of different bit lengths.

(Prior art) In the binary adder used in conventional processors, the fourth
As shown in the figure, two registers 1 store data X or Y with a maximum data size (bit length) of m bits.
, 2, an adder 3 according to the larger data size (m bits) of data X or Y, a carry register 4 that stores 1 when there is a carry in the addition result, and the addition result of the adder 3. As shown in Figure 5, for data with small data size (n bits, n<m), the missing digits are expanded by adding an O to the upper digits, and the data size is expanded to the larger data size. data size (m bits)
I added it after matching it to .

[Problem to be solved by the invention]

In the above-mentioned conventional binary adder, by providing an adder 3 adapted to the large data size of the data to be added, as the number of digits of data to be handled increases, the amount of hardware constituting the adder 3 increases exponentially. Moreover, the operating speed decreases significantly as the carry propagation time increases. In addition, as a carry measure, a carry look-ahead adder (C
When LA) was used, there was a problem in that the amount of hardware would further increase.

The present invention has been made in view of the above problems, and the technical problem set for solving the problem is to minimize the hardware configuration by using an adder suitable for the smaller data size. It is an object of the present invention to provide an adder for adding data of different bit lengths, which can reduce the number of bits and increase the operating speed.

[Means to solve the problem]

As a specific means for solving the above-mentioned problems, the present invention provides a method for configuring an adder that adds data of different bit lengths. An adder 13 whose data size is adjusted to the smaller one, a plus 1 circuit 15 having a data size corresponding to the difference in the number of digits between the larger data size and the smaller data size, and the plus 1 circuit 15 adds 1. A selection circuit 16 selects either the added data or the original data to which 1 has not been added, and the carry output of the adder 13 and the carry output of the plus 1 circuit 15 are ANDed to carry the added data. AND to output
It is equipped with a circuit 17.

(Function) With the above configuration, when calculating M-bit augend data and N-bit addition data, as shown in FIG. 11, the addition data Y is stored as it is in register 12, and then the upper (M-N) of the augend data
Data A from which bits have been taken is stored in the register 14, the contents of the register 11 and the contents of the register 12 are added by the adder 13, and the result is stored in the lower N of the register 18.
It is stored in the bit, and if there is a carry, it is output to the selection circuit 16 and the AND circuit 17. On the other hand, the contents of the register 14 are read into the plus 1 circuit 15 and the selection circuit 16, and the data input to the plus 1 circuit 15 is
is added thereto and output to the selection circuit 16. Selection circuit 16
Then, if a carry is input from the adder 13, the data input from the plus 1 circuit 15 is output, and if no carry is input, the data from the register 14 is output, and the upper register (M-N) of the register 18 is output. Store in bits. Furthermore, the carry output of adder 13 and the plus 1 circuit 1
It is ANDed with the carry output of No. 5 and output, and stored in the carry register 19.

In this way, in the calculation in adder 13, the upper (
The propagation time of the carry to M−N) bits can be omitted, and the time actually required to add data is the sum of the carry propagation time of the N bits in the adder 13 and the selection time in the selection circuit 16, which speeds up the processing. be done. Furthermore, regarding the hardware configuration, the amount of hardware is reduced and the cost is also lower than when all bit adders are configured.

〔Example 〕

Hereinafter, as an example of the present invention, M=4. A case in which the circuit is configured with N=2 gate circuits will be illustrated and explained.

Similarly to FIG. 1, the N (=2) bit register 11 is used to store the lower two digits of the augend data, and the N (=2) bit register 12 is used to store the added data. The adder 13 receives N (=2) bits of data from the two registers 11 and 12 and adds them together. The M−N (=2) bit register 14 stores the upper two digits of the augend data.

A plus 1 circuit 15 inputs data from this register 14 and adds 1, and inputs the output of this plus 1 circuit 15 and data from the register 14, and also inputs the carry output of the adder 13, depending on whether there is a carry or not. A selection circuit 16 is provided which selects and outputs either the output of the plus 1 circuit 15 or the data from the register 14. Further, an AND circuit 17 is provided which inputs the carry output of the plus 1 circuit 15 and the carry output of the adder 13 and outputs the AND. The M (-4) bit register 18 is
The output of the adder 13 is stored in the lower two digits, and the output of the selection circuit 16 is stored in the upper two digits. 1-bit carry register 1
9 stores the output of the AND circuit 17.

The adder 13, the plus 1 circuit 15, and the selection circuit 16 are implemented as shown in FIG.

The adder 13 is an A that inputs the first digit data X3 of the augend data and the first digit data Y1 of the addition data, respectively.
ND circuit 21 and OR circuit 22, and 2 of the augend data
The digit data X2 and the second digit data Y of the addition data. AND circuit 23 and OR circuit 24 which respectively input
, a circuit 25 that ANDs the data obtained by inverting the output of the AND circuit 21 and the output data of the OR circuit 22 to output the first digit addition data S3, and the data obtained by inverting the output of the AND circuit 23 and the OR circuit. AND with 24 output data
A circuit 26 that calculates and outputs the result, and an Exclusive circuit that performs an exclusive OR of the output data of this circuit 26 and the output data of the AND circuit 21 and outputs the second digit addition data S2.
e OR circuit 27, AND circuit 23 output data and O
A circuit 28 that ANDs the output data of the R circuit 24 and outputs the result, and an AND circuit 21 that outputs the output data of this circuit 28.
and an OR circuit 29 that performs an OR with the output data of and outputs a carry CL.

The plus 1 circuit 15 receives the third digit data X of the augend data.
A NOT circuit 31 inputs 1, inverts the input data, and outputs the third digit plus 1 addition data X. Exclusive that inputs and outputs the 4th digit plus 1 addition data Xpo
NOR circuit 32, data X1 and data X. and an AND circuit 33 that inputs and performs an AND operation and outputs a carry.

The selection circuit 16 inputs the inverted carry output from the adder 13, and also inputs the data X1 and performs an AND operation.
an AND circuit 35 which inputs the carry output from the adder 13 and inputs the output data of the NOT circuit 31 and performs an AND operation, and an OR between the output data of the circuit 34 and the output data of the AND circuit 35 The OR circuit 36 outputs the 3rd digit addition data S1, and the carry output from the adder 13 is inverted and inputted, and data X is input. A circuit 37 that inputs and performs an AND, inputs the carry output from the adder 13, and
An AND circuit 38 which inputs the output data of the exclusive NOR circuit 32 and performs an AND operation, and an OR circuit 39 which outputs the OR of the output data of the circuit 37 and the output data of the AND circuit 38 as the addition data So of the 4-way input. It consists of.

Data S obtained from each of these circuits. , Sl.

S2. Set S3 to the 4th and 3rd digits of register 18, respectively.
By storing in the second and first digits and storing the output of the AND circuit 17 in the carry register 19, a predetermined addition result can be obtained.

Using this embodiment, assume that the augend data is 0110 and the addition data is 11.

The input data to the plus 1 circuit 15 is Xo=O,X
□; Since it is 1, the plus 1 addition data XPo is output from the plus 1 circuit 15.

XPl is Xpo=1. Xpt"O. At this time, the carry C is C=0. The input data to the adder 13 is X2=1. Addition data S2 and S3
are respectively 52=O.

53=1. At this time, carry CL is CL=1. From these results, the output of the selection circuit 16 is +1
The addition data Xpo, Xp□ are selected and 5o=i, s,
=o, the addition result becomes 1001, and a correct result is obtained.

In this way, in the embodiment, the hardware is simple and the calculation results can be obtained quickly.

〔Effect of the invention 〕

As described above, in the present invention, when the data sizes of the data to be handled are different, addition is performed as data with a small data size, and 1 is added to the surplus high-order digits of data with a large data size as necessary. By adding them, the operating speed can be increased, the hardware configuration can be simplified and the amount of hardware can be reduced, and cost and space savings can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an adder according to the present invention, FIG. 2 is an explanatory diagram showing data of different digits, FIG. 3 is a block diagram showing a part of an embodiment according to the present invention, and FIG. FIG. 5 is a block diagram showing a conventional adder, and FIG. 5 is an explanatory diagram showing conventional data correction. 11.12.14,18.19...Register 13...Adder 15...Plus 1 circuit 16...Selection circuit 17...AND circuit

Claims (1)

[Claims] An adder (13) whose data size matches the smaller data size of the data to be calculated, and data corresponding to the difference in number of digits between the larger and smaller data sizes. a plus 1 circuit (15) having a size; a selection circuit (16) that selects either data to which 1 is added by the plus 1 circuit (15) or original data to which 1 is not added; A which ANDs the carry output of the adder (13) and the carry output of the plus 1 circuit (15) and outputs the carry of addition data.
An adder for adding data of different bit lengths, characterized by comprising an ND circuit (17).