JPH0474218A - Arithmetic circuit - Google Patents

Abstract

PURPOSE:To keep the interchange ability between the present and conventional types of arithmetic logic operation circuits by adding the hardware to an arithmetic logic operation circuit in order to mask the input and output signals of the arithmetic logic circuit. CONSTITUTION:The output of a 16-bit multiplier 1 passes through a 1st mask circuit 4a, and the circuit 4a masks a specific bit of an input signal based on the contents of a mask circuit control register 5a. Therefore, the low order 16 bits are masked to '0' out of 32 bits of the output signal of the circuit 4a. Then this mask data is shifted to the right by a bt by a 32-bit ALU 2b in terms of arithmetic. This arithmetic result is temporarily inputted to a totalizing register 3b through a 2nd mask circuit 4b. Then the ALU 2b calculates the input data and the contents of a lst totalizing register 3a to add them to the register 3a. Thus this totalizing result is equal to that obtained by a DSPI. Then the interchangeability is kept between the present and conventional types of arithmetic logic operation circuits.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an arithmetic circuit for a microprocessor.

[Conventional technology]

In recent years, due to improvements in LSI device technology, the data bit width of microprocessors has increased from the conventional 8 bits and 16 bits to 32 bits and 64 bits.

As a result, the number of bits in the arithmetic and logic operation circuit (hereinafter referred to as ALU) of microprocessors has increased as the data bit width has increased.

However, on the other hand, the International Telegraph and Telephone Consultative Committee Recommendations (CCI)
There are also applications for which calculation accuracy is determined by standards, such as audio encoding recommended in TT Recommendation) G., 721.

In these specific applications, compatibility in calculation accuracy is required, so even when using a microprocessor with more bits than a conventional one, it is necessary to perform calculations with the same number of bits as a conventional microprocessor. become.

However, in the ALU in a conventional microprocessor, for example, a 32-bit ALU can only perform calculations with 32-bit precision, so in order to maintain compatibility in calculation precision, data had to be corrected by software.

As an example of conventional data correction, DSP (
Digital signal processor: Digital
This will be explained by taking the signal processor as an example.

FIG. 5 is a block diagram showing the configuration of a first example of a conventional DSP.

In this first example, the DSP consists of a 16-bit multiplier 1, a 16-bit ALU 2a, and a first accumulation register 3a. Hereinafter, this first example of the conventional DSP will be referred to as DSP I.

FIG. 6 is a block diagram showing the configuration of a second example of a conventional DSP.

In the second example, the DSP has 16 hint multipliers 1 and 3
It consists of a 2-bit ALTJ2b, a first accumulation register 3a, and a second accumulation register 3b. Hereinafter, this second example of the conventional DSP will be referred to as DSP.

Note that a 16-bit multiplier means that both the multiplier and the multiplicand are 16
The result is a 32-bit multiplier.

In the following explanation, it is assumed that the data formats of the two DSPs are fixed-point two's complement representation as shown in FIG.

As an example of an operation, consider a product-sum operation such as, and al and Xl are, for example,
Assume that the data is as shown in FIG.

Further, here, for simplicity, it is assumed that al and Xl are decimal numbers with four digits after the decimal point.

Therefore, in the following explanation, a 16-bit binary number will be hypothetically replaced with a decimal number with 4 digits after the decimal point, and a 32-bit binary number will be hypothetically replaced with a decimal number with 8 digits after the decimal point.

Also, 2-1 in the 0 expression indicates a 1-bit arithmetic shift to the right in binary, or here, the 1-bit arithmetic shift to the right in binary is replaced as a 1-digit arithmetic shift to the right in decimal. I think about it.

The processing procedure for the above calculation is as follows.

1) Perform the calculation (multiplication of al -X+).

+2) The result of (1) is arithmetic shifted 1 bit to the right (ALU
calculation).

(31F2+ results are accumulated (ALU operation).

First, the calculation results in DSPI will be explained.

First, for the combinations of al and X+ shown in each row of FIG. 8, the output aI-X of multiplier 1 becomes a 32-bit value as shown in column A in FIG.

However, in this DSP (2), since the ALU 2a is 16 bits, the output of the multiplier 1 is 1. At the input section of L2a, the lower 1f of the 32 bits is truncated and becomes 16-bit data, which is actually A L U
The values calculated using 2a are shown in the middle column of FIG.

Next, this data is arithmetic shifted to the right by 1 bit using the ALU 2a. At this time, since the ALU 2a is 16 bits, the least significant bit of the data is dropped due to this shift, resulting in a value as shown in column E in FIG.

Next, this value is calculated by the ALU 2a and accumulated in the first accumulation register 3a.

The cumulative result is "0.0566".

Next, a case will be described in which the same operation is executed by DSPII.

In this case, since multiplier 1 is the same as that used in the DSP I described above, the output of multiplier 1 is the same as described above, and is shown in column A in FIG.

Next, this multiplication result is arithmetic shifted by 1 bit to the right. In this case, since ALU 2b is 32 bits in DSPII, the output of multiplier 1 is shifted as is in ALU 2b. The result is as shown in column B in FIG.

These values are calculated by ALU2b, and the first accumulation register 3
When it is accumulated to a, the accumulation result is '“0.056725
27'', which is different from the result with DSP I.

Next, processing is performed to match the calculation result of this DSP II with the calculation result of the DSP 2. In other words, in order to maintain the sameness of the intermediate results of the calculation, the lower bits of the output result of the multiplier 1 are changed to "o". Consider masking of the lower bits of the operation result of the ALU 2b to "0".

In order to perform the above-mentioned mask processing in the DSP II, it is necessary to use another accumulation register 3b in the block diagram of the DSPI shown in FIG. 6, and to perform the processing described below.

In addition, in the following explanation, it is possible to transfer the high-power result of the multiplier 1 to the second accumulation register 3b in the DSPII, and it is also possible to perform data calculations directly with the second accumulation register 3b in the ALU 2b. Assume that there is.

If the DSP is not capable of this, the amount of processing will further increase, but the essence of the explanation will not change.

DSPn processing involving mask processing is as follows.

(1) Transfer the output of multiplier 1 to second accumulation register 3b.

(2) The contents of the second accumulation register 3b and “'FFFF0
An AND operation is performed with OOO"°, and the result is transferred to the second accumulation register 3b.

(3) Arithmetic shift the contents of the second accumulation register 3b to the right by 1 bit.

(4) The contents of the second accumulation register 3b and “FFFF0O
OO'' and transfers the result to the second accumulation register 3b.

(5) Add the contents of the first accumulation register 3a and the contents of the second accumulation register 3b, and transfer the result to the first accumulation register 3a.

Through the above processing, the calculation result in DSPII is “0”.
．． 05660000'', and the same result as that obtained with DSP J is obtained.

In the above description, during the above processing, the masking processing in (2) and (4) is added to the processing in the DSP I.

Therefore, in this example, 8 pieces of data are accumulated, so
This is a total increase of 32 steps.

Such an increase in processing always occurs when the output of a 32-bit multiplier is treated as 16-bit data by the ALU.

[Problem to be solved by the invention]

As explained above, in the conventional arithmetic circuit configuration, the AL
Increasing the number of bits in U has the disadvantage of losing computation compatibility with conventional models.In order to avoid this and maintain computation compatibility, software processing for correction must be added. additional processing steps.

An object of the present invention is to provide a circuit that easily performs operations with fewer bits and with an arbitrary number of bits when a multi-bit ALU is not used, thereby eliminating the need for processing that was conventionally performed using software. However, the aim is to maintain compatibility with previous models.

[Means to solve the problem]

The arithmetic circuit of the present invention includes: a first mask circuit that masks an arbitrary bit of an input signal into one of two values and outputs the masked value to an arithmetic and logic operation circuit; and an output of the first mask circuit and an accumulation register. an arithmetic and logic operation circuit that performs arithmetic and logical operations with the output of the arithmetic and logic operation circuit; and a second mask that masks any bit of the operation result of the arithmetic and logic operation circuit into one of two values and outputs it to the accumulation register. A circuit, the accumulation register storing the output of the second mask circuit, and a register storing mask information specifying contents to be masked by the first and second mask circuits. .

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a DSP according to a first embodiment of the present invention.

As shown in FIG. 1, this DSP consists of 16-bit multipliers 1. A first mask circuit 4a, a 32-bit ALU 2b,
It is composed of a second mask circuit 4b, a first accumulation register 3a, a second accumulation register 3b, and a mask circuit control register (hereinafter referred to as a control register>5a).

ALU2b is 32 bits like the conventional DSPII.

In the DSP having the above configuration, the mask bits and mask polarity in the first mask circuit 4a and the second mask circuit 4b are controlled by the control register 5a.

In this embodiment, the control register 5a specifies that the upper n bits or the lower m bits of the input to each mask circuit are to be continuously masked.

For example, as shown in FIG. 2, the format of the control register 5a is determined.

“Mask presence/absence′” specifies whether to mask or not.
In this embodiment, "1" represents "with mask", and "0°" represents "without mask".

Next, ``Mask polarity'' specifies the polarity to mask,
In this example, '1'° means "mask to "1'", and "0"' means "mask".
0" represents a mask and .

Furthermore, "'upper/lower'" specifies whether the position to be masked is the upper bit or the lower bit, and in this embodiment, "1" indicates the "upper bit" and "0" indicates the "lower bit". represents.

In addition, "mask bit" specifies the number of digits to be masked, and in this embodiment, "" o o o o o" is "1 bit", "'
00001” is specified as “2 bits” in order, and “11
Specify ``111'' or ``32 bit.''

FIG. 3 shows an example of a mask circuit for realizing the above-described mask processing.

In the mask circuit shown in FIG. 3, when the "mask presence/absence" output of the control register 5a is 0°, that is, "no mask", the output of the decoder 6 and the "mask polarity" of the control register 5a are Regardless of the output, the input and output of the mask circuit are the same, and none of the bits are masked.

Further, when the output of "masking presence/absence" of the control register 5a is "1", that is, "masked", the output of the decoder 6 is "1", that is, for the specified bit,
Regardless of the input, the output will be the same as the "mask polarity" output of the control register 5a.In addition, for bits other than the above, regardless of the "mask polarity" output,
Input and output will be the same.

That is, the designated bit is masked to the designated polarity by the mask circuit shown in FIG.

Next, an explanation will be given of the operation when the above-mentioned sum-of-products operation is executed by the DSP according to this embodiment configured as described above.

In this case, the data format is the same as before.
It is assumed that the fixed-point two's complement representation is as shown in FIG. Also, for the sake of explanation, decimal numbers may be used virtually.

In FIG. 1, the output of multiplier 1 becomes the value shown in column A in FIG. 8, as in the conventional case.

The output of this multiplier 1 passes through a first mask circuit 4a before being input to the 32-bit ALU 2b.

The first mask circuit 4a masks specific bits of the input signal according to the contents of the control register 5a.

In this case, the designation of the control register 5a is such that the lower 16 bits are masked to 0". In other words, "
1001000”.

Therefore, the output signal of the first mask circuit 4a is masked to the lower 16 bits of 32 bits or "0", and becomes the same data as shown in the middle column of FIG.

Next, this data is arithmetic shifted by 1 bit to the right in ALU 2b, and the result becomes the data in column C of FIG.

Next, the calculation result of this ALU 2b is applied to the second mask cycle 1i.
It is once input to the second accumulation register 3b through tlj4b. Therefore, the shift result is the same as the data in column E in FIG.

Next, the ALU 2b calculates this data and the contents of the first accumulation register 3a, and accumulates it in the first accumulation register 3a, so that the accumulation result is the same as the accumulation result by the DSP I described above. becomes.

The only additional process required in conjunction with the above masking process is one process of inputting mask information to the control register 5a.

Note that in this embodiment, two accumulation registers are used to increase calculation efficiency, but it is also possible to use only one accumulation register.
In that case, the accumulated value may be saved, for example, in a data memory, so that the accumulated value is not destroyed during the shift operation.

Next, a second embodiment of the present invention will be described.

In the second embodiment, the method of controlling the first mask circuit #r4a and the second mask circuit 4b in the block diagram shown in FIG. 1 is changed.

FIG. 4 shows a block diagram of the mask circuit in this embodiment.

In the first embodiment described above, the control register specifies that the upper n bits or the lower m bits are to be masked continuously, but in the second embodiment, the presence or absence of masking is controlled bit by bit. This is what I did.

Therefore, the fil control register in the second embodiment is
It consists of 33 bits, which is the number of bits in the mask circuit plus 1. The most significant bit specifies the polarity to be masked, and the next 32 bits specify whether or not to mask each bit position.

A mask circuit for executing the control described in 2 can be realized by a circuit as shown in FIG.

In FIG. 4, the control register 5b contains, for example, ""0.
0000000000000000111111111
When "1111111" is written, the lower 16 bits of the input to the mask circuit 4c are masked to "0", so that the same calculation result as the DSP according to the first embodiment can be obtained.

Note that, as is clear from the above description, the present invention
The same effect can be obtained even with a different mask circuit control method and circuit configuration without being restricted by the mask circuit control method and circuit configuration shown in the embodiment and the second embodiment.

Further, although the ALU has been described as having 32 bits, this number of bits does not limit the scope of the claims in any way.

Furthermore, although the data format has been described as two's complement representation, it is clear that this does not limit the scope of the claims in any way.

〔Effect of the invention〕

As explained above, according to the present invention, by adding hardware that masks the input signals and output signals of the arithmetic and logic circuit to the arithmetic and logic circuit, the amount of processing can be reduced even if the data bit width increases. This has the advantage that it is possible to provide an arithmetic circuit that can maintain compatibility with conventional arithmetic and logic circuits without any increase.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a DSP according to the first embodiment of the present invention, FIG. 2 is a diagram showing the format of the mask circuit control register in the first embodiment of the present invention,
FIG. 3 is a circuit diagram showing the configuration of the mask circuit in the first embodiment of the present invention, FIG. 4 is a circuit diagram showing the configuration of the mask circuit in the second embodiment of the present invention, and FIG. , a block diagram showing the configuration of a first example of a conventional DSP, FIG. 6 is a block diagram showing the configuration of a second example of a conventional DSP, and FIG. 7 is a block diagram showing the configuration of a second example of a conventional DSP. A diagram showing the data format of expression, Figure 8, shows the conventional DS
FIG. 2 is a diagram for explaining the operation of a DSP according to an embodiment of the present invention. 1... Multiplier, 2a, 2b... Arithmetic logic operation circuit (
ALU), 3a, 3b - Accumulation register, 4a4b, 4
c. Mask circuit, 5a, 5b... Mask circuit control register, 6... Decoder.

Claims (1)

[Scope of Claims] A first mask circuit that masks an arbitrary bit of an input signal into one of two values and outputs it to an arithmetic and logic operation circuit; and an output of the first mask circuit and an accumulation register. an arithmetic and logic operation circuit that performs arithmetic and logical operations with the output; and a second mask circuit that masks any bit of the operation result of the arithmetic and logic operation circuit into one of two values and outputs it to the accumulation register. and the accumulation register that stores the output of the second mask circuit; and a register that stores mask information that specifies contents to be masked by the first and second mask circuits. circuit.