JPH07146777A - Arithmetic unit - Google Patents

Abstract

PURPOSE:To provide an arithmetic unit where power consumption is reduced by varying arithmetic accuracy and decreasing significant digit number. CONSTITUTION:This arithmetic unit is provided with a holding means 10 storing plural data, an arithmetic circuit 20 performing a calculation by the data from the holding means 10, a selection means 30 selecting the output of the arithmetic circuit 20 and a data input and outputting data, an accuracy setting means 40 designating a significant digit number for the data that the selection means 30 outputs and a correction means 50 performing an accuracy correction by the control signal of the accuracy setting means 40 and outputting the correction to the holding means 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic unit in a computer system, and more particularly to an arithmetic circuit which makes arithmetic precision variable.

[0002]

2. Description of the Related Art Conventionally, in a computer system, various arithmetic processes are performed by an arithmetic unit.
An example of a conventional arithmetic unit is shown in FIG. In this case,
A register 8 for storing data, which is a portion generally called a data path block in a microprocessor or the like.
0 and a floating point arithmetic circuit 81 that operates on the data from the register 80. The output 82 of the calculation result from the floating point calculation circuit 81 is stored in the register 80, but the calculation precision in this circuit is constant. In the case of double precision floating point data, the exponent part is 11 bits and the mantissa part is 52 bits. In normal arithmetic, the arithmetic precision of this arithmetic unit is sufficiently higher than the arithmetic precision required by application software.

In a computer system, an arithmetic logic unit (ALU) or a floating point arithmetic unit often has a fixed number of significant digits, but depending on the application, the number of significant digits may be small. When such extra calculation accuracy is not required, there is a method of switching the calculation accuracy. Floating-point arithmetic units usually have a function of switching between single precision and double precision. In addition to this, as an example of changing the operation precision, Japanese Patent Laid-Open No. 2-293928 discloses a method of using a correction circuit for correcting the number of significant digits for the input and output of an arithmetic logic operation circuit with a variable operation word length. There is.

[0004]

In a conventional arithmetic unit having a constant arithmetic precision, there is a problem that even if the effective digit number may be small, more circuits operate than the effective digit number and power consumption increases. there were. Further, the method of correcting the number of digits in the input and output units of the arithmetic unit has a problem that a plurality of correction circuits are required and the hardware scale becomes large. Furthermore, such a correction circuit acts only on the arithmetic circuit portion, and the power consumption cannot be sufficiently reduced from the viewpoint of the entire arithmetic device.

Further, in the floating point addition / subtraction device,
Even if the number of significant digits of the input data is small, the shift operation for digit alignment is performed internally, so the number of bits input to the circuit part that performs addition and subtraction is greater than the number of significant digits, resulting in unnecessary power consumption and large power consumption. There was a problem that

In order to solve the above problems, the present invention provides
An object of the present invention is to provide an arithmetic unit capable of limiting the operating portion of the arithmetic unit when the number of effective digits of arithmetic is small.

[0007]

In order to achieve the above-mentioned object, the present invention is provided with a correction means for correcting the number of significant digits of data in the arithmetic unit, and the data after the number of the significant digits is corrected outside the number of significant digits. The value of the bit is fixed.

Specifically, in the arithmetic unit according to the invention of claim 1, the selecting means for selecting and outputting the output of the arithmetic circuit and the data input, and the accuracy correction for the data output by the selecting means. And a correction means for outputting the data to a holding means for storing the data.

In the arithmetic unit according to the second aspect of the invention, the correction means masks a circuit for rounding to a significant digit designated by the precision setting means and a lower bit of the designated significant digit to 0. And a circuit.

In the arithmetic unit according to the third aspect of the present invention, the arithmetic circuit has a function of performing arithmetic logic operation on integer data, and the correction unit has a significant number of significant digits designated by the precision setting unit. The first shift left to a number
The shift circuit, the second shift circuit that shifts to the right so that the number of significant digits is the lower-order bit number, and the bypass circuit that outputs the data as it is without shifting. When selected, the data shifted by the first shift circuit is output to the holding means, and when the output of the arithmetic circuit is selected in the selecting means and the data is stored in the holding means, the data is output from the bypass circuit, and in the selecting means. When the output of the arithmetic circuit is selected and output to the outside of the arithmetic device, it has a function of outputting from the second shift circuit.

In the arithmetic unit according to the fourth aspect of the present invention, the first arithmetic circuit for taking the difference between the exponent parts of two floating point data and the mantissa part of the floating point data according to the output of the first arithmetic circuit. A shift circuit that performs digit alignment, a correction unit that corrects the output from the shift circuit with a control signal from a precision setting unit, and a second value that performs addition and subtraction on the mantissa value corrected by the correction unit. An arithmetic circuit and a third arithmetic circuit for normalizing the output of the second arithmetic circuit and the exponent part of the floating point data are provided.

According to a fifth aspect of the present invention, in the floating point addition / subtraction arithmetic device according to the fourth aspect, the correction means is a circuit for performing rounding processing to a significant digit designated by the precision setting means, and the designation means. And a circuit for masking the lower bits of the significant digit to 0.

[0013]

According to the first aspect of the present invention, the data corrected by the correction means is held, the calculation is performed on this data, and the correction means also corrects the number of calculation digits. .

According to the second aspect of the present invention, the correction is executed by the rounding circuit, and the bits outside the significant digit of the number of arithmetic digits are always fixed to 0 inside the arithmetic unit.

According to the third aspect of the present invention, when integer data is input, the data is left-shifted and stored, the operation result is stored as it is, and when the data is output to the outside, the operation result is output. Is shifted right and output.

According to the invention of claim 4, the data after the digit alignment of the mantissa when performing the floating point addition and subtraction is corrected, and the floating point operation is performed on the corrected mantissa.

According to the fifth aspect of the present invention, the correction is executed by the rounding circuit, and the significant digits of the mantissa are always fixed to 0.

[0018]

【Example】

(Embodiment 1) Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

A first embodiment of the present invention will be described with reference to FIGS. 1 to 5. FIG. 1 is a block diagram showing the configuration of the arithmetic unit of this embodiment. This arithmetic unit selects a holding means 10 for storing a plurality of data, an arithmetic circuit 20 for performing an arithmetic operation on the data output from the holding means, an output 32 of the arithmetic circuit 20 and an input data 31. Selecting means 30 for outputting the calculation accuracy, calculation accuracy setting means 40 for specifying the calculation accuracy, and correction means 50 for performing accuracy correction on the output 33 of the selection means 30 in accordance with the number of significant digits 41 output by the calculation accuracy setting means 40. Composed of and. The output data 51 of the correction means 50 is returned to the holding means 10 and is output to the outside as the output data 51.

FIG. 2 is a block diagram showing the internal structure of the correction means 50. The input 33 to the correction means 50 is rounded by the rounding circuit 52 and output as output data 34. This output data 34 is input to the mask circuit 53,
Further, it is masked by the mask circuit 53. The effective digit number 41 output from the arithmetic precision setting means 40 is input to the rounding circuit 52 and the mask circuit 53, and the designated digit number is processed.

The operation of the arithmetic unit configured as above will be described with reference to FIGS. First, the flow of data in the arithmetic unit will be described. The data 31 input from the outside is selected by the selection unit 30, the accuracy is corrected by the correction unit 50, and stored in the holding unit 10. The arithmetic operation in the arithmetic circuit 20 is executed on the data stored in the holding means 10. This calculation result 32
Is selected by the selection means 30, the accuracy is corrected by the correction means 50 and stored in the holding means 10, or output as output data 51 to the outside.

Next, according to FIGS. 3 and 4, the number of significant digits 41 is 41.
The operation of the correction means in the case of 4 bits will be described.
FIG. 3 shows an operation example of the rounding circuit 52. A rounding bit in which 1 is set to the 4th bit from the lower order is added to the 8-bit input data 33, and an operation in which the upper 4bits are the number of significant digits is performed. FIG. 4 shows an operation example of the mask circuit 53.
The lower 4 bits of the 8-bit input data are masked and fixed at 0. Upper 4 specified by the number of significant digits 41
Bits are output as is. In this way, the data is rounded at the portion having the effective digit number 41, and the portion having the effective digit number or less is masked.

As an example of data to which the above correction operation is applied, FIG. 5 shows an example of a data format in the case of floating point numerical data. The most significant bit S is a sign bit, the next is an exponent part, and the lower field is a mantissa part. The bits in the range designated by the number of significant digits 41 with respect to the mantissa among these are rounded and masked by the correction means 50 as shown in the examples of FIGS. 3 and 4. That is,
In the correction means 50, the lower bit portion shown by the diagonal lines in FIG. 5 is masked to 0 and output, and stored in the holding means 10. Therefore, in the arithmetic circuit 20, the arithmetic operation is performed on the data in which all the lower bits from the effective digit number 41 are masked to 0, and is stored in the holding means 10 as the data of the precision of the effective digit number 41, or The output data 51 is output to the outside.

As described above, in the arithmetic unit of this embodiment, the holding means 10 corrects the input data 31.
After being stored in, the data in the arithmetic unit can all have the arithmetic precision of the designated effective digit number 41. The accuracy correction for making the calculation accuracy variable only needs to include the correction means 50 at one place. Further, the holding means 10 and the arithmetic circuit 20 in the arithmetic unit are in a state in which the lower-order bits indicated by diagonal lines are fixed to 0 regardless of the value of the input data 31, and the lower-order bits are in a constant state. Become. Therefore, in the holding unit 10 and the arithmetic circuit 20, a portion where the state is constant does not turn on / off the transistor and does not consume useless power.

(Second Embodiment) A second embodiment of the present invention will be described with reference to FIGS. 1 and 6 to 9.

FIG. 1 is a block diagram showing the arrangement of the arithmetic unit of this embodiment, which is the same as that of the first embodiment. The present embodiment is different in the configuration of the correction means.

FIG. 6 is a block diagram showing the internal structure of the correction means 50. The input 33 to the correction means 50 is supplied to the right shift circuit 54, the left shift circuit 55, and the bypass circuit 56. One output of the right shift circuit 54, the left shift circuit 55, and the bypass circuit 56 is the output 5 of the correction means 50.
It is output as 1. In the right shift circuit 54 and the left shift circuit 55, the number of significant digits 4 output from the calculation precision setting means 40 is 4
1 is input, and the shift process of the designated number of digits is performed.

The operation of the arithmetic unit configured as above will be described with reference to FIGS. The data flow is the same as in the first embodiment. In this embodiment, the correction method is different. The operation of the correction means when the number of digits of the arithmetic unit is 8 bits and the number of significant digits 41 is 4 bits will be described with reference to FIGS. 7 and 8. FIG. 7 shows an operation example of the left shift circuit 54. The 8-bit input data 33 is shifted left by 4 bits and output. FIG. 8 shows an operation example of the right shift circuit 55. The 8-bit input data 33 is right-shifted by 4 bits and output. The 8-bit input is directly output to the pi-bus circuit.

The right shift circuit 54 and the left shift circuit 55.
The bypass circuit 56 and the bypass circuit 56 are selected and operate in the following cases. When the input data 31 is stored in the holding means 10, it is corrected by the left shift circuit 55 and stored. When the output of the arithmetic circuit 20 is stored in the holding means 10, the bypass circuit 56 stores the value as it is. The output of the arithmetic circuit 20 is output data 51.
When it is output to the outside as, it is corrected by the right shift circuit 54 and output.

The operation of accuracy correction and arithmetic processing will be described according to the operation of the above circuit. FIG. 9 shows an example of the data format in the case of integer data. The data 31 input from the outside has a valid digit number designated by the significant digit number 41 from the lower bit. This data is left-shifted by the correction circuit, and 0 is entered in the lower bit shown by the diagonal line after the shift. Therefore, for the corrected data, the shaded bits in FIG. 9 are always fixed during the arithmetic processing between the holding means 10 and the arithmetic circuit 20. At this time, the arithmetic circuit 20 does not need to be a variable precision arithmetic circuit, and may perform precision processing for all bits regardless of the value of the number of significant digits 41. For example, in the case of addition, since the data of 0 is input to the lower bit part other than the significant digit number, it is irrelevant to the addition process and does not affect the operation on the valid digit number data. Also, as a result of the addition, when the most significant bit of the arithmetic circuit 20 overflows, it can be seen that the number of significant digits 41 is exceeded. That is,
Even if an arbitrary precision is set in the calculation precision setting means 40, there is no need to change the control circuit for overflow or the like with respect to the number of significant digits, and one calculation circuit 20 with a fixed calculation precision.
Can be used. Further, when the calculation result is output to the outside as the output data 51, the significant digit in the upper portion of the output of the arithmetic circuit 20 is moved to the lower portion by the correction means 50 and can be output as the result of the correct number of significant digits. .

As described above, in the case where the lower bit part of the input data is valid data, it is possible to make the calculation accuracy variable by one correction means, and the calculation in the calculation device of this embodiment is performed. During this period, the calculation can be performed with the precision of the designated significant digit number 41. At this time, the arithmetic circuit 2
0 may be a fixed precision arithmetic circuit. The lower bits obtained by removing the significant digits from the total number of digits of the holding means 10 and the arithmetic circuit 20 are always fixed, and the lower bits are in a constant state. Therefore, the holding means 10
In the arithmetic circuit 20, the portion where the state is constant does not turn on / off the transistor and does not consume useless power,
It is possible to reduce power consumption.

(Embodiment 3) A third embodiment of the present invention will be described with reference to FIGS.

FIG. 10 is a block diagram showing the configuration of the arithmetic unit of this embodiment. The arithmetic unit includes a subtraction circuit 60 that calculates the difference of the exponent part and a shift circuit 61 that performs digit matching of the mantissa part.
And the calculation accuracy setting means 6 for the output of the shift circuit 61.
5, a correction unit 62 for performing accuracy correction, an addition / subtraction circuit 63 for performing addition / subtraction on the corrected data, and a normalization circuit for performing digit alignment and correction for the exponent part on the operation result of the addition / subtraction circuit 63. It is composed of 64. The correction means is composed of the rounding circuit and the mask circuit shown in FIG. 2 and operates as described in the first embodiment.

Next, the operation of this embodiment will be described.
The two floating point data are supplied to the input 70 and the input 71, respectively. Each floating point data is separated into an exponent part and a mantissa part and supplied to the subtraction circuit 60 and the shift circuit 61, respectively. The subtraction circuit 60 compares the values of the exponents and shifts the mantissa of the floating-point data 70 or 71, which is smaller by the difference, to the right in the shift circuit 61 to perform digit alignment. In this digit matching, the mantissa data to be digit matched is the calculation precision setting means 6
Since the number of significant digits of the mantissa part designated by 5 is shifted to the right, this part is corrected by the correction means 62. The correction circuit operation is as described in the first embodiment. Both of the two data of the corrected mantissa part are numerical values with the precision indicated by the number of significant digits 72, and the mantissa part is calculated by executing the calculation on these two data by the adder / subtractor circuit 63. Since a carry may occur in the case of addition and a carry may occur in the case of subtraction in the result of this addition and subtraction, the position of the most significant bit 1 of the mantissa part is detected and normalized. The normalization of the mantissa part is a shift process of the mantissa part data. Further, the normalization circuit 73 corrects the value of the exponent part by the amount of shifting the mantissa part.

As described above, in the floating point addition / subtraction arithmetic unit, the accuracy can be made variable by the correction means 62. Furthermore, it becomes possible to fix the state of the lower bits outside the effective digit number of the adder / subtractor circuit 63 and the normalization circuit 73 after this correction means, and prevent unnecessary circuit operation according to the effective digit number. Power consumption can be reduced.

[0036]

As described above, according to the first aspect of the present invention, the calculation accuracy can be made variable by the correction means at one place. At this time, the arithmetic accuracy of the arithmetic circuit may be constant. According to the invention of claim 2, the lower bits outside the effective digit number in the arithmetic unit can be fixed to a constant value, the part where the state changes can be limited, and the power consumption can be reduced. You can According to the invention of claim 3, even when the lower bit of the input data is a significant digit, the arithmetic precision is made variable in the processing in the arithmetic unit,
Furthermore, the lower bits can be kept in a constant state, and power consumption can be reduced. According to the invention of claim 4, when the addition and subtraction are performed on the floating point data, it is possible to perform the correction after the digit alignment and the arithmetic operation of the adder to make the precision variable. According to the invention of claim 5, the lower bits outside the significant digit number in the arithmetic unit can be fixed to a constant value, the part where the state changes can be limited, and the power consumption can be reduced. You can

[Brief description of drawings]

FIG. 1 is a configuration diagram of an arithmetic unit according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a correction unit in the same embodiment.

FIG. 3 is an operation diagram of a rounding circuit in the embodiment.

FIG. 4 is an operation diagram of a mask circuit according to the same embodiment.

FIG. 5 is a format diagram of floating-point data in the same embodiment.

FIG. 6 is a configuration diagram of a correction unit according to a second embodiment of the present invention.

FIG. 7 is an operation diagram of a left shift circuit in the same embodiment.

FIG. 8 is an operation diagram of a right shift circuit according to the same embodiment.

FIG. 9 is a format diagram of integer data in the same embodiment.

FIG. 10 is a block diagram of an arithmetic unit according to a third embodiment of the present invention.

FIG. 11 is a block diagram of a conventional arithmetic unit.

[Explanation of symbols]

 10 holding means 20 arithmetic circuit 30 selecting means 40 arithmetic precision setting means 50, 62 correction means 52 rounding circuit 53 mask circuit 54 right shift circuit 55 left shift circuit 56 bypass circuit 60 subtraction circuit 61 shift circuit 63 adder / subtractor circuit 64 normalization circuit

Claims (5)

[Claims] 1. An accuracy setting means for setting an operation accuracy, a holding means for storing a plurality of data, an arithmetic circuit for performing an arithmetic operation on the data from the holding means, and an output and a data input of the arithmetic circuit are selected. And a correction unit that corrects the data output from the selection unit by a control signal of the accuracy setting unit and outputs the corrected data to the holding unit. 2. The correction means includes a circuit for rounding to a significant digit designated by the precision setting means, and a circuit for masking a lower bit of the designated significant digit to 0. The arithmetic unit according to claim 1. 3. The arithmetic circuit has a function of performing arithmetic logic operation on integer data, and the correcting means shifts to the left so that the number of significant digits designated by the precision setting means becomes a higher number of bits. 1 shift circuit, a second shift circuit that shifts to the right so that the number of significant digits is a lower-order bit number, and a bypass circuit that outputs the shift digit as it is without any shift. When the data input is selected by the selecting means, the data shifted by the first shift circuit is output to the holding means, and the output of the arithmetic circuit is selected by the selecting means and the data is stored in the holding means. When the output of the arithmetic circuit is selected by the selecting means and is output to the outside of the arithmetic device, the output signal is output from the second shift circuit. The arithmetic unit according to claim 1, wherein: 4. A first arithmetic circuit for calculating a difference between exponent parts of two floating point data, and a shift circuit for performing digit alignment of a mantissa part of the floating point data according to an output of the first arithmetic circuit. Precision setting means for setting the calculation precision, correction means for correcting the output from the shift circuit with the control signal from the precision setting means, and addition and subtraction for the numerical value of the mantissa corrected by the correction means. A floating-point addition / subtraction arithmetic device comprising: a second arithmetic circuit; and a third arithmetic circuit that normalizes the output of the second arithmetic circuit and the exponent part of the floating-point data. 5. The correction means includes a circuit for rounding to a significant digit designated by the precision setting means, and a circuit for masking a lower bit of the designated significant digit to 0. The floating point addition / subtraction arithmetic unit according to claim 4.