KR200156144Y1 - A circuit of absolute value - Google Patents

Abstract

The present invention relates to an absolute value calculation circuit, and in particular, to simplify the program and reduce the processing time by adding a circuit that outputs the maximum positive number when an overflow occurs during the absolute value calculation. The present invention is a register (210) (220) for storing the input data, respectively, the arithmetic operator (230) for calculating the absolute value and determining whether or not to overflow the output data of the register (210 or 220), A multiplexer 260 for selecting one of the output value '7FFFh' of the register 250 and the output value of the arithmetic operator 230 according to the overflow signal of the arithmetic operator 230, and the output value of the multiplexer 260 And a register 24 for output.

Description

Absolute value calculation circuit

The present invention relates to a maximum negative number processing technique, and more particularly, to an absolute value calculating circuit that allows hardware to perform absolute value calculation for maximum negative number processing.

In general, a processor makes a negative integer a positive integer when processing input data.

For example, for a 16-bit processor, the absolute value (= 32768) corresponding to '8000H (= -32768)' cannot be displayed in 16-bit when the absolute value is taken from a negative integer to produce a positive integer. '

However, if you keep the negative number in the absolute value calculation, an error occurs. Therefore, the program calculates by replacing '-32768' with '+32767'.

Here, the range of integers that can be represented by 16 bits is '8000H to 7FFFH (-32768 to +32767)'.

As shown in the block diagram of FIG. 1, the prior art calculates an absolute value by subtracting registers 110 and 120 for storing two input data, respectively, and storing data of the registers 110 and 120, respectively. The arithmetic operator 130 and the register 140 which stores the output value of this arithmetic operator 130 are comprised.

The operation of the prior art will be described with reference to the signal flowchart of FIG. 2.

First, 16 bits of data are alternately stored in the registers 110 and 120.

In this case, the arithmetic operator 130 receives the stored data of the register 110 or 120 and determines whether the most significant bit is one.

Accordingly, when the most significant bit is 0, the input data is stored in the register 140 as it is and output.

If the most significant bit of the input data is 1, the arithmetic operator 130 takes a complement of all the bits of the input data, adds 1 to calculate an absolute value, and determines whether the result is '8000h'.

In the case where the input data is '8000h', even if 1 is added to the complement, it becomes '8000h'.

Therefore, when the result is not '8000h', the arithmetic operator 130 stores the result in the register 140 and outputs the result.

If the result is '8000h', the arithmetic operator 130 outputs a signal indicating the overflow occurrence.

In this case, when the overflow occurs, the arithmetic operator 130 outputs the result value as '7FFFh' by executing the following program.

A = ABS (A);

C = 7FFFh;

if overflow A = C;

Accordingly, the value '7FFFh' is stored in the register 140.

However, such a conventional technique is impossible to calculate the absolute value by hardware, so the program is complicated and the processing time is long.

Accordingly, an object of the present invention is to provide an absolute value calculation circuit for maximal negative processing, which can simplify the program and reduce processing time by adding a circuit for maximal negative processing to improve the disadvantage of the prior art. have.

1 is a block diagram according to the prior art;

2 is a signal flow diagram for the processing of the arithmetic operator in FIG.

Figure 3 is a block diagram showing an embodiment according to the present invention.

* Explanation of symbols for main parts of the drawings

210, 220, 240, 250: Register 230: Arithmetic operator

As shown in the block diagram of FIG. 3, the absolute value calculating circuit according to the present invention uses the registers 210 and 220 for storing input data and the output data of the registers 210 or 220 as inputs. And an arithmetic operator 230 for determining whether or not to overflow, and a maximum positive number ('7FFFh') of the register 250 and an output value of the arithmetic operator 230 according to the overflow signal of the arithmetic operator 230. The multiplexer 260 which selects one, and the register 240 which stores and outputs the output value of this multiplexer 260 are comprised.

Referring to the operation and effect of the embodiment of the present invention configured as described above are as follows.

First, 16 bits of data are alternately stored in the registers 210 and 220.

At this time, the arithmetic operator 230 receives the stored data of the register 210 or 220 and determines whether the most significant bit is one.

Accordingly, when the most significant bit is 0, the input data is stored in the register 240 as it is and output.

If the most significant bit of the input data is 1, the Sanur operator 230 takes a complement of all the bits of the input data, adds 1 to calculate an absolute value, and determines whether the result is '8000h'.

In the case where the input data is '8000h', the complement is added and 1 becomes '8000h'.

At this time, if the result is not '8000h', the arithmetic operator 230 outputs a result value without activating the overflow signal.

Accordingly, since the overflow signal of the arithmetic operator 230 is in an inactive state, the multiplexer 260 selects the output value of the arithmetic operator 230 and stores it in the register 240.

If the result is '8000h', the arithmetic operator 230 outputs a signal indicating the overflow to the multiplexer 260.

Accordingly, since the overflow signal of the arithmetic operator 230 becomes active, the multiplexer 260 selects the maximum positive number ('7FFFh') stored in the register 250 rather than selecting the output value of the arithmetic operator 230. To be stored in the register 240.

As described in detail above, the present invention does not perform a complicated operation processing by a program when an overflow occurs, but by configuring the hardware to output a corresponding operation value when an overflow occurs, the program for the operation processing is simplified as well as processing time. There is a shortening effect.

Claims (1)

Registers 210 and 220 for storing input data, an arithmetic operator 230 for calculating an absolute value with input of output data of the registers 210 and 220, and determining whether to overflow, and a maximum positive number A multiplexer that selects a stored value of the register 250 when the overflow signal is generated from the register 250 and the arithmetic operator 230, and selects a result value of the arithmetic operator 230 when there is no overflow. And a register (240) for storing an output value of the multiplexer (260).