JP2665067B2 - Floating point adder / subtracter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a floating point adder / subtractor, and more particularly to a floating point adder / subtracter for normalizing an operation result.

[0002]

2. Description of the Related Art Conventionally, this kind of floating-point adder / subtractor is realized by, for example, a configuration as shown in FIG. In the figure, reference numeral 21 denotes a floating point adder / subtracter, and reference numeral 22 denotes a control circuit for controlling the entire floating point adder / subtractor.

In the main adder / subtractor 7, two operands 1,
2 (referred to as operand a and operand b). In FIG. 2, when the output of the main adder / subtractor 7 is not in the normal form, the result of the normalization is stored in the result register 18 as the final result.

In this conventional example, this normalization is performed by first and second
Are performed using the normalization shifters 8 and 9. The first normalization shifter 8 is used when the addition / subtraction result can be normalized within a predetermined number of normalization digits, and the second normalization shifter 9 is used to normalize the addition / subtraction result using a predetermined normalization digit. Used when it cannot be done within the number.

[0005] The reason why the two normalization shifters are used properly is as follows. That is, the operands input to the floating-point arithmetic unit are generally in the normal form, and when both the input operands are in the normal form,
In many cases, the output of the main adder / subtractor 7 does not require normalization, or even if normalization is required, the number of normalized digits may be small.

Therefore, normalization in the case where the frequency of appearance is high, the number of normalized digits can be easily obtained from the operation result, and normalization can be performed at high speed is performed by the first normalization shifter 7,
In the case where the frequency of appearance is low, it is not easy to obtain the number of normalized digits from the result, and the normalization process takes a long time, the normalization is performed by extending the execution time and using the second normalization shifter 9.

The floating point arithmetic unit 21 is rarely used alone, but is used in synchronization with another device. However, if the arithmetic time is made variable as described above, the extension of the arithmetic time is extended to other parts. You need to be notified. However, the main adder / subtractor 7 generally has a large bit width, and if the above determination is made based on the operation result of the main adder / subtractor 7, it takes too much execution time to obtain the determination result and notify the other parts.

Therefore, the first and second normalization shifters 8 and 9
Is determined from the operation result using only the upper n bits of operand a and operand b as follows. Arithmetic units for this purpose are the first and second sub adder / subtracters 10 and 11.

The first sub adder / subtracter 10 performs the operation on the assumption that there is no carry from the lower predetermined bit for the upper predetermined n bits, while the second sub adder / subtractor 11 performs the operation from the lower predetermined bit for the upper predetermined n bits. The calculation is performed assuming that a carry has occurred.

The first and second sub adder / subtracters 10, 1
Assuming that there was no carry from each result of 1,
If normalization is not required for each of the cases, and if normalization is required, the first normalization shifter 8
, Or the second normalization shifter 9 determines whether to perform normalization using the first and second normalized digit number determination means 12,
The determination is made at step 13.

First and second normalized digit number determining means 12, 1
3 is a normalization unnecessary or a first normalization shifter 8
If it is determined that the range is a range that can be normalized, the first normalized digit number calculating means 19 obtains the number of normalized digits from the predetermined upper k bits of the main adder / subtracter 7 and outputs the output of the main adder / subtracter 7. Is normalized by using the first normalization shifter 8, the output from the first normalization shifter 8 is selected by the operation result selection means 17, the result is stored in the result register 18, and the operation result And

On the other hand, if one of the first and second normalized digit number judging means 10 and 11 judges that the normalization is performed by the second normalization shifter 9, the control circuit 22 informs the effect. To extend the operation time of the floating-point adder / subtracter, delay the execution of the operations of other parts, set the number of normalized digits of the first normalization shifter 8 to 0, and leave the output of the main adder / subtractor 7 as it is. The data that has passed through the first normalization shifter 8 is selected by the operation result selection means 17, and is temporarily stored in the result register 18. Then, the value stored in the result register 18 is sent to the second normalized shifter 9 and the second normalized digit number calculating means 20.

The second normalized digit number calculating means 20 calculates the number of normalized digits and sends it to the second normalized shifter 9. The second normalization shifter 9 performs normalization according to the normalized number of digits obtained by the second normalized number of digits calculation means 20, and inputs the result to the calculation result selection means 17 again. Then, the operation result selecting means 17 selects the output of the second normalization shifter 9 and stores it in the result register 18 to obtain the operation result.

According to the above-mentioned conventional floating point adder / subtracter, it is assumed that either one of the first and second normalized digit number determining means 12 and 13 cannot be normalized unless the second normalized shifter 9 is used. If it is determined, the normalization is performed by the second normalization shifter 9. In this case, even if the first normalization shifter 8 can actually perform normalization,
There is a possibility that the normalization may be performed by the normalization shifter 9, which may result in a longer execution time of the operation than necessary.

An example in which such a problem occurs will be described below. As a precondition, n of upper predetermined n bits is 6
It is assumed that the first and second normalization shifters 8 and 9 perform binary normalization. When the number of normalized digits is 2 or less, normalization is performed by the first normalization shifter 8, and when the number of normalized digits is 3 or more, normalization is performed by the second normalization shifter 9. I do.

Further, the operation is performed by adding the operands a and b. At this time, if the upper predetermined n bits of the operand a are 0.00011 and the upper predetermined n bits of the operand b are 0.000000, the first sub adder / subtractor 7 does not carry the upper predetermined n bits. , The first sub adder / subtracter 10
Is 0.00011, and the number of normalized digits in this case is 3.

On the other hand, in the second sub adder / subtractor 11, the operation is performed assuming that there is a carry for the upper predetermined n bits.
00, and the number of normalized digits in this case is two.

Therefore, the first normalized digit number judging means 1
2, it is determined that the second normalization shifter 9 is used.
The normalization is performed by the second shifter 9. In this case, if there is actually a carry to the upper predetermined n bits, the first normalization shifter 8 can normalize the data.
In this case, the normalization is performed by the normalization shifter 9, and the execution time of the operation becomes longer than necessary.

However, if it is determined from the operation result of the main adder / subtractor 7 which of the first and second normalization shifters 8 and 9 is used, it takes too much time until the shifter is selected. There are drawbacks.

[0020]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a floating-point adder / subtracter which can determine which of the first and second normalization shifters to use accurately and in a short time. .

[0021]

The floating-point adder / subtractor according to the present invention comprises:
An adder / subtracter that performs addition and subtraction of two operands, and is used when the number of normalized digits of the addition / subtraction result is within a predetermined number.
A first normalization shifter that can perform normalization at high speed, and a first normalization shifter that is used when the number of normalized digits is larger than the predetermined number.
Normalization is compared to normalization by the first normalization shifter.
A second normalization shifter that operates at a lower speed, and uses each of the upper n bits of the two operands to
When there is no carry from the lower part, the first and second
A first positive to determine which of the normalized shifters to use
Normalizing digit number determining means, and the upper n bits of the two operands
From the lower order for this upper n bits using
The first and second normalized shifters when there is a carry of
Of the second normalized digit number to determine which one of
Means and a digit when addition and subtraction of each of m bits consecutive to each of the upper n bits of the two operands is performed.
On the basis of the carry generation condition and the carry propagation condition,
And the second normalized digit number determining means determines
And selection means for selecting the second normalization shifter .

[0022]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a circuit block diagram of an embodiment of the present invention, and the same parts as those in FIG. 2 are denoted by the same reference numerals.
In this embodiment, using the lower predetermined m bits continuous with the higher predetermined n bits 3 and 4 of the two operands a and b, the main adder / subtracter 7 generates a carry from the lower predetermined m bits to the higher predetermined n bits. The condition and the propagation condition are obtained by the normalized digit number selection control means 14.

Then, the lower predetermined m bits to the higher predetermined n
When the condition for generating a carry to a bit is 1, the upper predetermined n
Since there is always a carry to a bit, the normalized digit number selecting means 16 selects the output from the second normalized digit number determining means 13. When the condition for generating a carry from the lower predetermined m bits to the higher predetermined n bits and the propagation condition are both 0, the carry to the upper predetermined n bits is not necessarily performed. The output from the normalized digit number determining means 12 is selected.

However, the lower predetermined m bits to the higher predetermined n bits
When the condition for carrying a bit is 0 and the propagation condition is 1, it is not possible to specify whether or not there is a carry using only this information. Therefore, in this case, processing similar to the conventional processing is performed.

From the output of the normalization digit number selecting means 16, it is determined whether or not normalization is necessary. If normalization is necessary, whether the normalization is performed by the first normalization shifter 8 or the second normalization is performed. First and second after determining whether to normalize by shifter 9
Normalization shifters 8 and 9, operation result selecting means 17, result register 18, first and second normalized digit number calculating means 1
The operations of 9, 20 are the same as those of FIG.

An example using FIG. 1 will be described below. The precondition is that n of the upper predetermined n bits is 6, and binary normalization is performed. Normalization is performed by the first normalization shifter 8 when the number of normalized digits is two or less, and when the number of normalized digits is three or more, normalization is performed by the second normalization shifter 9. .

Further, m of the lower predetermined m bits continuous with the predetermined upper n bits is set to 1, and the operation is performed by adding the operands a and b. At this time, the upper predetermined n bits of the operand a are 0.00011, the lower predetermined m bits successive thereto are 1, and the upper predetermined n bits of the operand b are n.
It is assumed that the bit is 0.000000, and the lower predetermined m bits continuous thereto are 1.

The operation result of the first sub adder / subtractor 10 is 0.0
Therefore, the normalized digit number in this case is 3, and the first normalized digit number determining means 12 determines that the second normalized shifter 9 performs normalization.

On the other hand, since the operation result of the second sub adder / subtracter 11 is 0.00100, the number of normalized digits in this case is 2
And the second normalized digit number determining means 13 determines that the first normalized shifter 8 performs normalization.

The condition for generating a carry from the lower predetermined m bits for the upper predetermined n bits becomes 1, and a carry from the lower predetermined m bits to the upper predetermined n bits is detected by the normalized digit number selection control means 14. Is done. Therefore,
Based on the result of the calculation assuming that there is a carry, the determination result of the second normalized digit number determination means 13 which has determined which of the first and second normalization shifters should perform normalization is used. Therefore, normalization is performed by the first normalization shifter.

As a result, in the conventional determination method, normalization is performed by the second normalization shifter 9 in some cases.
By using the present invention, it is not necessary to use the second normalization shifter 9, and it is possible to prevent the execution time of the operation from being unnecessarily long.

[0033]

As described above, according to the present invention, the determination of the normalized shift number of the result of addition / subtraction of two operands is as follows.
In addition to the addition and subtraction results of the upper predetermined n bits of these two operands, the addition and subtraction results of the lower m bits consecutive to the n bits are used, so that the operation can be performed accurately and in a short time. effective.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram of an embodiment of the present invention.

FIG. 2 is a circuit block diagram of a conventional floating point adder / subtractor.

[Explanation of symbols]

 1, 2 Operand 7 Main adder / subtractor 8, 9 Normalized shifter 10, 11 Secondary adder / subtractor 12, 13 Normalized digit number determination means 14 Normalized digit number selection control means 15 OR gate 16 Normalized digit number selection means 19, 20 Normal Digitized number calculation means

Claims (1)

(57) [Claims] An adder / subtracter for performing addition / subtraction of two operands, a first normalization shifter used when the number of normalized digits of the addition / subtraction result is within a predetermined number and capable of performing the normalization at high speed , Used when the number of normalized digits is larger than the predetermined number, the normalization is performed by the first normalized shifter.
A second normalization shifter which performs the processing at a lower speed than the normalization, and a method in which each of the upper n bits of the two operands is used and there is no carry from the lower bit to the n bits.
Which of the first and second normalization shifters to use
A first normalized digit number determining means for determining whether the first and second operands have a carry from the lower n bits to the upper n bits using each of the upper n bits of the two operands Second normalized digit number determining means for determining which of the shifters to use , and adjusting each of m bits continuous with each of the upper n bits of the two operands
Condition of carry and carry propagation condition when calculation is performed
And the first and second normalized digit number determining means
To make a selection between the first and second normalization shifters.
And a selection means.