JPS59226944A - Addition and subtraction system of floating point data - Google Patents

Abstract

PURPOSE:To reduce the addition/subtraction time of the floating point data by checking the presence or absence of an invalid digit in parallel to the execution of addition/subtraction and therefore the shift amount for normalization is fixed at a time point when the result of addition/subtraction is obtained. CONSTITUTION:When mantissa parts of two floating point data are given to registers OP1 and OP2, an adder 5 performs an algebraical addition of the mantissa parts. At the same time, a carry signal is produced to a specific bit position by a carry look-ahead logic mechanism CLAH4. Then valid patterns (00-0, 11- 1, 11-10) are detected for upper digits from an optional bit by a valid digit detection logic mechanism DET3. Then the carry signal obtained by the CLAH4 and the valid pattern information obtained from the DET3 are fed to a shift amount production logic mechanism. Thus a shift amount which shifts the valid digit is obtained in accordance with a logical equation. Then the arithmetic result obtained from the adder 5 is shifted in response to the obtained shift amount. Thus the addition/subtraction is carried out for the floating point data.

Description

Detailed Description of the Invention (al) Technical Field of the Invention The present invention performs addition and subtraction on two floating point data consisting of a mantissa part, an exponent part, and a sign part, and when an invalid digit occurs in the upper digit, Concerning a method for quickly determining the amount of shift necessary for normalization.

Technical background When adding or subtracting two floating point data consisting of a mantissa, an exponent, and a sign, digit alignment, addition of the mantissa parts, and normalization are performed. To do this, first, the exponent parts of the two operands are compared, and the mantissa with the smaller exponent part is shifted to the right, and each time it is shifted by one digit as a hexadecimal number, the exponent part is incremented by 1, and the exponent part is Continue shifting until they match. When shifting to the right, the last digit of the hexadecimal number shifted out is saved as a guard digit.

If the exponents of the two operands are equal and are not shifted to the right, one lower zero digit is assumed to have been added as a guard digit.

In the above digit alignment operation, when the exponent parts match, the mantissa parts are added algebraically and an intermediate sum is output. At this time, if there is a carry as a result of addition of the mantissa part, the intermediate sum is shifted to the right, the carry becomes the most significant digit, and 1 is added to the exponent part.

If there is an invalid pattern in the upper digits of this intermediate sum, the intermediate sum is shifted to the left by the amount necessary for normalization, the lowest digit is filled with zero, and the exponent part is decreased by 1 for each digit shifted to the left. It will be done.

In the above floating point data addition/subtraction method, the present invention provides an invalid pattern (for example, o for positive numbers) in the upper digits.
o------o, 11--- for negative numbers
This relates to a method for performing the above-mentioned left shift processing at high speed when 1-.-1) occurs.

(11.1 Conventional technology and problems When adding or subtracting floating point data, invalid digits may occur in the upper digits. Conventionally, it was checked whether there were invalid digits based on the result after performing addition or subtraction. Therefore, there was a problem of long execution time.

(dl Purpose of the Invention In view of the above conventional drawbacks, the present invention examines the presence or absence of invalid digits in parallel with the actual execution of addition/subtraction, and at least determines the shift amount for normalization when the addition/subtraction results are obtained.) The purpose is to provide a method that allows

According to the present invention, in a floating point addition/subtraction circuit that adds or subtracts two data and normalizes the same, the present invention provides a first means for adding/subtracting two data; 11. A second means for detecting that the specific continuous part becomes a 00-...--0 pattern as a result of addition and subtraction when carrying from a lower order is not considered; ----------- Third means for detecting 4 patterns, and 11--
--Fourth means for detecting that there are 10 patterns;
a fifth means of a carry look ahead circuit for creating a carry-in signal for a specific bit position from a carry propagation condition as a part of the first means or separately; This is achieved by providing a method for determining the shift amount necessary for normalization by the second to fifth means described above without using the addition/subtraction results created by Since the shift amount for normalization is also established, it is possible to shorten the calculation time for floating point data.

(f) Embodiments of the Invention The gist of the present invention is to detect invalid digits in the calculation result of floating point data at an early stage, but invalid digits higher than a certain digit are as follows: ■ oo--- ---------o・Ci ■ 11---
It is easy to understand that it can be determined by ----------1 ■ 1t----------1--10.Ci.

However, here it is assumed that Ci indicates a carry signal.

Therefore, in parallel with the calculation of the floating point data of the two operands, the present invention detects the invalid patterns of ■ to ■ above for digits higher than a certain digit of the calculation result, and performs the shift for normalization from the invalid pattern. It comes down to the means to find the quantity.

Embodiments of the present invention will be described in detail below with reference to the drawings.

First, we will explain the means for detecting invalid patterns.

To detect that any high-order digit is oo----1...-0/2 turns, use the two operands OPI.
and OP2, each successive 3-bit throat (An +A
n + L^n+2) and (Bn +Bn+1.Bn+2
) and two G\, as shown in Figure 1, only if any of the operations (11 to (5)) is a logical "1" tonal, but this can be changed to the specific part of the reciprocal part (n w m + 1 pits)) & Kotsumu 1 It is sufficient to detect that the operation result force shown by the logical formula in FIG. 2 (a) < 8 statement "1").

In the process of finding this logical formula)
29421, so I will omit it here, but in Japanese Patent Application No. 57-229421, the lowest bit and node of the two operand data are 00 and 11.
Since the number of special conditions (i.e., not exclusive OR) is limited, the condition number 0 shown in Figure 2 (a) is
0-・------.

or 11----------1). Therefore, if we limit the condition to such that the sum of the two operands is 00-------0, it is necessary that the least significant bit of the two operands is not an exclusive OR. This is the condition that the calculation result of the logical formula shown in FIG. 2 (b) becomes logic "1". Here, E indicates exclusive OR, and 0 indicates logical OR.

Therefore, the result of addition of the two operands is 11
---The condition for 1 is that the logic of the least significant bit in Figure 2 (b) is negated and the result of the operation of the logical formula shown in (c) is logic "1". .

Similarly, the addition result of the two operands is 11---
−−−−−−−−10. In this case, each consecutive 3 bits (An, An + 1+
For An + 2 ) and (Bn, Bn+1.Bn+2 ), only when any of the operations (1) to (5) shown in Figure 3 results in logic "l", the mantissa part of floating point data Looking at any specific part, Figure 4 (a)
It is only necessary to detect that the result of the calculation of the logical formula shown by
It is determined by using the same procedure as disclosed in No. 9421.

However, in this logical formula as well, 11
--Since pattern 4 is included, the above 11.--
・In order to obtain only the pattern that is -IO, it is necessary that the least significant bit of the two operands is not an exclusive OR, and the result of the operation of the logical formula shown in Figure 4 (b) is a logical "1". It is sufficient to detect that ”.

The above shows that the pattern of any specific part of the mantissa of floating point data is either oo------o or 11---
-------------This is a logical formula for detecting whether it is 1 or 1t---------10, but in order to determine the invalid digits of the upper digits of the mantissa, it is necessary to It is necessary to consider adding a carry bit that goes up to the least significant bit, and generally it is created using carry look ahead logic to find a carry-in signal (Ci) for a specific bit position from the carry propagation conditions, and this signal and By using the above-mentioned invalid pattern and applying the logical conditions shown in (1) to (2) above, it is possible to determine whether the upper digits are invalid.

That is, in the case of (2), since the pattern is 00-----0, all the digits become "0" and become invalid digits only when there is no carry-in signal' (Ci).

In the case of ■, the pattern is 11-・---1, so whether there is a carry-in signal (Ci) or not, 11-・--
------1 or oo-------・-〇, which becomes an invalid digit.

■When it is 11------10 patterns,
A carry-in signal (C4) is always required, and when the carry-in signal (C4) goes up, 11.
--4, which means that it is an invalid digit.

Next, the means for creating the shift amount will be explained.

When the detection means detects that an invalid digit occurs as a result of adding the mantissa parts of two floating point data, the invalid digit is determined for each digit of the 4-bit hexadecimal number that makes up the mantissa part. It is necessary to perform a left shift and normalize.

Various methods can be considered for creating the shift amount at this time as long as the shift position can be specified, so there is no need to limit it in particular, but one embodiment of the present invention will be described as follows.

In this embodiment, for example, in the case where it is necessary to shift at least 48 bits or more, the logical formula that determines the amount of shift of 48 bits, which is the first stage, is changed to the second stage.
By considering and summarizing the invalid digit determination conditions ■ to ■ while referring to Figures (B), (C), and Figure 4 (B), the logical formula shown in Figure 5 is obtained, and the calculation using this logical formula is When the result is a logic "1", a left shift of 48 points can be performed. The first half of this equation shows the case of ■, and the second half is ■
The case is shown below. In this logical formula, E and ■ are symbols indicating exclusive OR, 0 is a logical OR, A is a symbol indicating logical product, Ci is a carry-in signal, and 6 to 51 indicate each digit position of floating point data.

In this example, the mantissa part of the floating point data is 8 to 63 bits (excluding guard digits), and the target focus position of the mantissa part to be shifted by 48 bits/7 bits is 8 to 51 bits. Actually, considering the carry bit and sign bit of the most significant digit as valid bits, 48 bits from 4 to 51 are the digits to be shifted in this case.

Next is the invalid digit detection mechanism that has been explained so far.

An embodiment of the present invention using a carry look ahead logic mechanism and a shift amount creation logic mechanism will be described. FIG. 6 is its block diagram, and 1.2 is a register (OPI, 0P2) that stores the mantissa part of floating point data, respectively.
), 3 is oo for any specific part of the mantissa above
−−−−−−−−−−−o, 1i−−−−・−1
, 11 ------- 10 Invalid digit detection logic (DET) that detects patterns, 4 Carry Look Ahead logic (CLAH) that creates a carry signal for a specific bit position, 5 the mantissa part adder, 6 is an invalid digit detection logic (DET) 3 and carry look ahead logic (CLAH) 4 is a shift amount creation logic that creates a shift amount to shift invalid digits in units of 4 bits using the data of 4; , 7.8 are a plurality of shift signals S48, S32, S1 created by the shift amount creation logic mechanism 6.
6, S00 and 5S12.5SO8,5SO4,5
This is a shifter that shifts the calculation result by SOO.

The above shift signals S48, S32, S16,
SOO is activated when shifting 48 bits, 32 bits, and 16 bits to 00 bits with a difference of 16 bits, respectively.
The shift signals 5S12.5SO8, 5SO4, and 5SOO have a 4-bit difference of 12 h-, os hit 04, respectively.
It is activated when shifting bits or 00 bits. By combining these shift signals, it is possible to specify an arbitrary shift amount (in units of 4 bits).

In this drawing, register (OPI, 0P2) 1
'+2 is given the mantissa parts of two floating point data, the adder 5 performs algebraic addition of the mantissa parts, and at the same time the carry look ahead logic (CL
AH) 4 creates a carry signal for a specific bit position, and invalid digit detection logic (DET) 3 detects an invalid pattern (OO----) from an arbitrary focus to the upper digit.
--1...-0, 11-----4, 11--
-----10 patterns) are detected.

Next, carry look ahead logic (CLA)
H) The carry signal obtained in step 4 and the invalid pattern information obtained in invalid digit detection logic (DET) 3 are processed by the shift amount creation logic 6, for example, using the logical formula shown in FIG. 5 (in this case, 48 According to the bit shift example), a shift amount for shifting invalid digits is created, and by shifting the operation result obtained by the adder 5 according to this shift amount, addition and subtraction of floating point data can be performed.

The above has been explained using Figures 1 to 5 o o------
------・0, 11----------1,
11--10 The pattern detection logic and shift amount creation logic are just examples, and it goes without saying that the method is not limited to these.

(g) Effects of the Invention As explained in detail above, according to the present invention, invalid patterns in digits higher than a certain digit are detected in parallel with addition/subtraction operations using floating point data, and the invalid patterns are further normalized. Since the shift amount has been established at least when the addition/subtraction result is obtained by calculating the shift amount for the floating point data, there is an effect that the time required for addition/subtraction of floating point data can be shortened.

[Brief explanation of drawings]

Figure 1 shows 00------0 or 1 t-------
FIG. 2 is a diagram illustrating the logic for detecting the invalid pattern in FIG. 1 with respect to a specific part of the mantissa part of floating point data. Figure 3 is a diagram explaining the conditions for detecting the existence of the 11-------10 pattern, Figure 4 is a diagram for detecting a turn at the invalid node in Figure 3 for a specific part of the mantissa part of floating point data. Figure 5 is a diagram explaining an example of logic for creating a shift amount for normalizing invalid digits.
FIG. 6 is a block diagram showing one embodiment of the present invention. In the drawing, EOR, E, -V- are exclusive OR symbols, OR, O are logical sum symbols, AND, A are logical product symbols, and 1.2 is a register (OPI, 0P2).
), 3 is invalid digit detection logic (DET), 4
is carry look ahead logic (CLAH)
, 5 is an adder, 6 is a shift amount creation logic mechanism, and 7 and 8 are shifters, respectively.

Claims (1)

[Claims] In a floating point addition/subtraction circuit that adds or subtracts two data and normalizes the data, a first means for adding/subtracting two data and a carry from a lower order for a specific continuous portion of the two data are used. a second means for detecting that the specific part becomes a 00-------0 pattern as a result of addition and subtraction when not thinking;
-------A third means for detecting that the pattern becomes 4, and a fourth means for detecting that the pattern becomes 11, and as a part of the first means, Alternatively, carry-look
and a fifth means of an adend circuit, and the second to
A floating point data addition/subtraction method characterized in that a shift amount necessary for normalization is determined by the fifth means.