JPH0357019A - Floating-point data adding and subtracting circuit - Google Patents

Abstract

PURPOSE:To reduce the number of gate stages to increase the operation speed by using floating-point data or intermediate data of arithmetic processing to select arithmetic processing paths. CONSTITUTION:A path A consists of a justifying circuit 21, an adding/ subtracting circuit 22, and a normalizing circuit 23 of + or -1-bit shift, and a path B consists of a justifying circuit 24 of a maximum of 1-bit shift, an adding/ subtracting circuit 25, and normalizing circuit 26. The path A or B is selected by a control signal C to a selector circuit 27, and an output Z is obtained from the circuit 27. Thus, plural data paths A and B are provided and are selectively controlled and selected by floating-point data to simplify the circuit function of each data path system and to reduce the number of gate stages of the circuit.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to an addition/subtraction circuit for normalized floating point data, and is particularly applicable to digital signal processors (DSP) and high-level It is used in microcontrollers. (Prior Art) Normalized floating point data is widely used in signal processing LSIs that achieve high precision and a wide dynamic range, such as DSPs and high-end microcomputers. By the way, the above-mentioned signal processing LSI is required to be high-speed. One of the things that limits the speedup is the floating point data addition/subtraction circuit (FASU). First, we will explain the conventional floating point addition/subtraction circuit (FASU). Figure 29 shows a block diagram of a conventional FASU. First, the digit alignment circuit 1 compares the exponent data of input X and input Y, and performs digit alignment of the mantissa data according to the difference. At this time, if the difference in the exponent part is greater than the mantissa digit matching digit, the mantissa data with the smaller exponent part is fixed to O (O determination circuit). Next, the addition and subtraction circuit 2 performs addition and subtraction of the mantissa data, which have been digit-aligned by two people. Finally, the normalization circuit 3 estimates the amount of normalization from the result of addition and subtraction of the mantissa part, and normalizes the result of addition and subtraction according to the estimate. FIG. 30 is a circuit block diagram of a conventional 32E6 (32-bit mantissa, 6-bit exponent) FASU.

Next, we will explain this circuit. First, the subtraction circuit 4 subtracts the exponent part data XE of the input X and the exponent part data YE of the input Y. The digits are aligned by shifting the mantissa data XM or YM to the right according to the result of the subtraction. At that time, the shift is performed by X shifter 5 and Y shifter 6. The shift conditions are listed in the table below.

Next, the mantissa data XM' and YM' after the digit alignment are added or subtracted by the addition/subtraction circuit 7 according to the instruction. A normalization circuit is constituted by a normalization amount detection circuit 8, a left shift circuit 9, and a subtraction circuit IO for normalizing the output data added and subtracted by the addition and subtraction circuit 7. The above addition/subtraction result ZM' is input to the circuit 8, and the normalized amount of the mantissa data is detected. Shift the mantissa part ZM' to the left according to the normalized amount. Further, the circuit 10 subtracts the normalized amount from the exponent part ZE'. The mantissa output ZM and the exponent output ZE, which are the output results, are the outputs of the floating-point addition and subtraction circuits, respectively. Next, we will explain how to subtract X-Y by actually substituting numerical values. The data length is 32 bits for the mantissa and 6 bits for the exponent. The 1st bit of the mantissa below is the sign bit. The left side of E is the mantissa data, and the right side is the exponent data. 1) X=0. 10000・・・・・・・・・OE
IOOOOO-Y=0.11111・・・・・・・・・
IEOIIIOOWhen finding the above equation, first find XE-YE. 1000 00 -0111 00 0001 00 Above calculation result XE>YE, I XE-YE l =4
, shift YM to the right by 4 bits and perform subtraction.

XMOIOOO 00-00 E 10
0000YMOOOOO 11-=41
E 011100ZM'00111 00...O
f ZE'lOOOOOOZMOIIIO
00...010 ZE 011111, that is, detect the normalized amount from the subtraction result ZM'. The sign bit is O
Then, since O is 1 bit continuous, the normalization amount is D=1, that is, 1 bit shift.

Next, the mantissa part ZM' is shifted to the left by 1 bit according to the normalization amount. The output result ZM becomes the output of the mantissa part. Also, since the exponent part is rXE-YE>OJ, both XE and YE are adjusted to the exponent part looooo of XE by the digit alignment circuit, and ZE' is ZE'=XE=1 0000
It becomes 0. Thereafter, according to the normalization amount D=1, the mantissa data is shifted to the left by 1 bit, so that the exponent data is decreased by 1. Therefore, the exponent part data ZE is 011111
becomes. Example 2) X=OIOO 00...000
E 100000-Y=0111 10...0
00 E 011111 case XE=10000
0, YE = 01111l, and these two differ by 1 bit, so for digit alignment. YM on the right 1bi. t shift. X. =0100 0000-000 E
10 00 00-Y=0011 1100...
・000 E 10 00 000000
01.00...000 E 10 00 0
0 where ZM'=00000100...000,ZE
'=100000, and estimate the normal quantity from ZM'.
Since there are 4 O's after the code bit, D=4. That is, shift ZM' to the left by 4 bits and decrease ZE' by 4. In other words, ZM=OLOOOOOO...000, ZE=
It becomes 011100. Child I drama 3) Similarly, X = 01000 0...O E 10000
0+Y=lOO11 1...I E 011
In the case of 110, XE-YE=2, so if you match the digits, X=010000...O E 100000
-Y=111001...I E 100000
001001...I E 100000 When this is normalized (1 bit shift) Z=OIOO11
...10 E 011111. Figure 31 shows the conventional mantissa part of 31 bits and exponent part of 6 bits.
This is a block diagram of the floating point addition wt arithmetic circuit. Next, we will explain this circuit. Here, the 0 fixed circuit 12 included in the X shifter 5, Y shifter 6, subtraction circuit 4, etc.
13, O determination circuit 14, shift amount detection circuit 15, etc. are extracted and shown.

This circuit first calculates the difference between the exponent data XE of input X and the exponent data YE of input Y using the subtraction circuit 4, and shifts the mantissa data Perform the matching. Shifting at this time is performed by an X shift circuit 5 and a Y shift circuit 6. The shift amount and conditions at that time are shown in Figure 32. Next, the mantissa data XM' and YM' after digit alignment are
Addition and subtraction are performed by the 31-bit addition and subtraction circuit 7 according to instructions.

Finally, the output data is normalized according to the output result of the addition/subtraction circuit 7. First, the output result of the 31-bit addition/subtraction circuit 7 is input, and the normalization amount detection circuit 8 detects the normalization amount. Shift the mantissa to the left according to that value and set it as ZM. Further, the subtraction circuit 10 subtracts the normalized amount from the exponent part ZE', and the result is set as ZE. Let the output results ZM and ZE be the output results of the floating point addition/subtraction circuit.

(Problems to be Solved by the Invention) The floating point addition/subtraction circuit with a data length of 32E6 in FIG. Regarding the output, the input signals X and Y are subjected to addition and subtraction according to the arithmetic instructions, and the result Z is output.

As mentioned above, after the input signals X and Y are input until the calculated output Z (ZE and ZM) is output, they pass through the following circuit in series. 1) 6-bit subtraction [ii Calculate the shift amount from J path 4.

2) Based on the result of 1) above, 31 bit (5 stages) shifter 5
, 6.

3) Calculate the result of 2> above using a 32-bit addition/subtraction circuit 7.

4) The calculation result r32 bits + carry is passed through the encoder circuit 8 for calculating the positive JIL conversion amount, which outputs 5 bits. 5) According to the normalized sensitivity detected by encoder 8,
It passes through a 31-bit (5 stages) shifter 9 that shifts the mantissa data.

5) The data passes through a 6bjt subtraction circuit 10 that reduces the exponent data according to the normalization failure detected by the encoder 8.

The above floating point addition/subtraction circuits are 1) to 5), or 1
) to 4) and 5)' flow in series, which has the disadvantage of slowing down the calculation speed, which is one of the reasons for limiting the speeding up of signal processing LSIs.

In addition, in the conventional FASU shown in Fig. 31, during addition and subtraction, if the difference between the two manual exponent parts is greater than the number of digits of the mantissa data, that is, the shift amount, shifting is not possible, and the exponent of the addition/subtraction circuit human power YE' or XM' Addition and subtraction are performed with the mantissa data of the smaller number fixed at 0 (Figure 32). Therefore, the critical path of the calculation path of the floating point addition/subtraction circuit (FASU) is
a 0 determination circuit 14 for fixing M or YM to O;
Input signal xM' or YM' of 31-bit addition/subtraction circuit 7
O fixing circuit 12 . for fixing to all "O" according to the output result of O determining circuit 14 . 13 has been inserted. This means an increase in the number of gate stages in the floating-point addition/subtraction circuit, which is an obstacle to increasing commercial speed. In addition, in the floating point addition/subtraction circuit shown in FIG. 31, the normalization circuit detects the normalization amount from the output result of the mantissa addition/subtraction circuit 7, so the normalization and left shift of the mantissa part by the normalization amount are performed. Subtraction of the normalized portion of the exponent part was not performed until the result of addition/subtraction of the mantissa part was detected, making it difficult to increase speed. Therefore, an object of the present invention is to provide a floating-point data addition/subtraction circuit that can be faster than the conventional circuit.

[Structure of the Invention] (Means and Effects for Solving the Problems) The present invention has at least two arithmetic processing paths for floating-point data. The floating point data addition/subtraction circuit is characterized by comprising means for selecting the processing path using $ floating point data. The present invention also provides a digit alignment circuit that performs digit alignment of mantissa data according to a difference in exponent data, an addition/subtraction circuit that performs addition or subtraction of the mantissa data that has been digit-aligned by the circuit, and the circuit. A normalization amount detection circuit that sets a flag from a part of each bit of the mantissa data before the calculation and the multiple bits before and after it, and uses the flag as input to a normalization amount encode garden path. a normalization shifter that normalizes the mantissa data from the addition/subtraction circuit according to the output of the circuit; and means for selecting whether to shift the output data by 1 bit to the right or left from the output of the shifter. This is a floating-point data addition/subtraction circuit characterized by the following. The present invention also provides a digit alignment circuit that aligns mantissa data according to a difference in exponent data, an addition/subtraction circuit that adds or subtracts the mantissa data digit-aligned by the circuit, and a A normalization amount detection circuit that detects a normalization amount from the calculation result, a normalization shifter that normalizes the mantissa data according to the normalization value, and an output of the addition and subtraction circuit that receives the output of the addition and subtraction circuit as input. Floating point data comprising: a right shifter that performs a right shift of i bits when an overflow occurs; and means for selecting the output of the right shifter and the output of the normalization shifter according to the output of the addition/subtraction circuit. It is an addition/subtraction circuit.

That is, the present invention provides a plurality of data buses that take certain conditions into consideration with respect to the data flow of the conventional technology, and selectively controls and selects each data bus using floating point data, thereby controlling the circuits of each data bus system. The aim is to simplify the functions and reduce the number of gate stages in the circuit. Furthermore, in order to reduce the reduction in processing speed caused by the 0 judgment circuit and the O fixing circuit in the prior art, the present invention provides at least two systems of arithmetic circuits that are selected depending on the shift amount caused for digit alignment, and performs these arithmetic operations. High speed is achieved by selecting the results. That is, when the amount of shift of the mantissa part due to subtraction of the exponent part is less than the number of digits of the mantissa part, the calculation result of the addition/subtraction circuit similar to the prior art is selected.

However, this circuit does not include an O-fixing circuit.

That is, the mantissa part of the data with the smaller exponent part is shifted to the right by the result of subtraction of the exponent part, addition and subtraction are performed, and then normalization is performed. Furthermore, when the amount of shift of the mantissa by subtracting the exponent is greater than or equal to the number of digits in the mantissa, a data through or sign inversion circuit is selected. The above two systems of circuits are processed in parallel and are finally selected by the exponent input.

The present invention is also characterized in that the normalization circuit detects the normalized amount from the data after digit alignment, that is, from the manual data of the mantissa addition/subtraction circuit. Most of the processing for detecting the normalized amount and for normalization is performed in parallel with the mantissa addition/subtraction by using the input data of the mantissa addition/subtraction circuit.

In addition, in the present invention, when the output of the adder/subtractor circuit for mantissa data overflows, a circuit for shifting the mantissa data to the right by 1 bit is extracted from the normalization shifter, and these circuits are selectively used in parallel to reduce the number of gate stages and increase speed. I'm measuring.

(Embodiment) An embodiment of the present invention will be described below with reference to the drawings.6 Fig. 1 is a diagram showing the configuration of the embodiment, and path A is the digit matching circuit 21.
, an addition/subtraction circuit 22, and a ±1 bit shift normalization circuit 23. Path B consists of a digit alignment circuit 24 with a maximum of 1 bit shift, an addition/subtraction circuit 25, and a normalization circuit 26. Paths A and B are control signals C to the selector circuit 27,
One of them is selected and becomes the output Z.

The mantissa condition of two normalized floating point signals is 010000...OOO≦XM≦0111...
...ill...■010000...00
0≦YM≦0111...111...■. For simplicity, we will explain the case where both XM and YM are positive, but considering that XM and YM are two's complement representations. The same explanation can be given when one or both of XM and YM is negative. Here, the weight of the most significant bit on the left and right sides of XM (when XM>O) is ``1'', the weight of the next digit is rl/2'', and the R value of the next digit is rl/4''
,..., and the same is true for YM. Therefore (
1) The left side of XM in the formula and the left side of YM in the formula ■ are both r
It represents 1/2J. Also, the right side of XM and YM
The right sides of both represent numbers smaller than "1" by the least significant bit.

From formula 1 bit shift,
If "O", there is no shift. Also from type 0, XM
to the right by more than 2 bits, or the normalization amount is at most 1
The following is the result. From the above results, the condition that requires a normalization shift of 2 bits or more is that the amount of digit alignment (the amount of digit alignment between mantissa parts based on the value of the exponent part) is 1 bit or less, that is, if X. E
− Y E When l≦1. In this embodiment, two addition/subtraction paths A and B are provided, and A has a conventional digit alignment circuit, but the normalized amount is at most 1 bit, and B has a digit alignment of less than 1 bit. , has a conventional normalization circuit. The output of this signal path A and the output of B are determined separately, and finally the output of A or the output of B is selected using signal C.
As the selection condition for the signal C at that time, the difference between the two human power signals, IXE-YEI≦1, is used. Due to the above characteristics,
We will discuss later how speedup can be achieved. Figure 2 is a concrete example of Figure 1. 1) Regarding signal path A, ? i) Calculate the difference rXE-YEJ between the exponent parts of the two human input signals using the subtraction circuit 3l. According to the difference, X shifter 21,,Y
Shift XM or YM to the right with shifter 2l■'! Perform digit alignment using 1t. However, as a condition, r
When “X E − Y E > 31”, Y M. = 0
shall be. When rXE-YE<-31J, XM=0. These are the times when the well exceeds the shift range. (ii) According to (i) above, the mantissa data XM'l and YM'l after digit alignment are added or subtracted by the addition or subtraction circuit 22 by an addition or subtraction instruction. Also, the selector 32 selects the larger exponent data and outputs it to the subtraction circuit 34 as ZE'.

(iii) Addition/subtraction circuit 22 output result ZM'l is +1
It is input to the bit normalization encoder 33 and outputs a 1-bit shift control signal to the left or right from the upper few bits of ZM'l. Normalization is performed by the left/right bit shifter 23 according to the shift control signal. Let the output of this shifter 23 be the mantissa output Z M 1 of the signal path A. ? Here, there is a possibility that the normalized amount of ZM'l becomes more than ±1 bit, but in that case, the output selector 27 selects route B, so it is not a concern.2 ) Next, for signal path B, (i) the lower 2 bits of the exponent part of the 2-person signal are XEI,
Using XEO, YEI, YEO as input, according to Figure 3,
lbit shifter 24. Or shift XM or YM to the right by lbit in 24■. In Fig. 3, rXJ has an indefinite meaning. Fig. 6 shows the signal XS (X shift) designed based on the Carnaugh map in Fig. 5. , YS (Y shift) generation circuit.

(1i) According to (i) above, the mantissa data X after digit alignment
M'2 and YM'2 are added or subtracted by an addition/subtraction circuit 25 using an addition or subtraction instruction. (iii) For the output result ZM'2 of the addition/subtraction circuit 25, the normalization amount is detected by the normalization amount detection circuit 35. According to the detection result, normalization is performed by shifting using a 31-bit left shifter 26. The output of the shifter 26 is assumed to be the mantissa data ZM2 of the signal path B.

3) Next, selector 27 and selector 3 select mantissa output results ZMI, ZM2 and normalized amount result M1 or -M2.
The selection conditions for the control signal No. 6 are determined from FIG. Input signal XM. A selection signal C is generated as shown in FIG. 7 by the sign bit of YM, the addition/subtraction instruction, and the subtraction results of the exponent parts XE and YE, and output results are selected and outputted by the selector 27 and the selector 36 according to the selection signal C as shown in FIG.

The above embodiment has the following advantages.

That is, as shown in FIG. 30, in the conventional 32E6 floating point addition/subtraction, the signal path first calculates the difference in the exponent part using the 6-bit subtraction circuit 4, and then calculates the difference in the exponent part according to the difference in the exponent part.
Digit alignment is performed using shifter 5 or Y shifter 6 (31-bit shifter). The data is added and subtracted by a 32-bit addition/subtraction circuit 7, a normalized amount is detected using the result of the addition/subtraction, and a shifter 9 performs a shift according to this normalized amount. The circuit delay of data at that time is: (1) 6-bit subtraction circuit 4 → 5-stage shift circuit 5 or? →32-bit addition/subtraction circuit 7 →-1 bit, +31
The bit encoder 8 becomes the 5-stage shift circuit 9.

On the other hand, in the circuit shown in FIG. 2, (2) 6-bit subtraction circuit 31→5-stage shift circuit 21.
Or 21■→32bit addition/subtraction circuit 22→±1 bi
t encoder 33 → 1st stage shift circuit 23 → select circuit 27 or (3) 4-man power control circuit (Fig. 6) → 1st stage shift circuit 2
41 or 24■→32bit addition/subtraction circuit 25→+31
bit encoder 25 → 5-stage shift circuit 26 → select circuit 27 The circuit delay is the slower one of the signal paths (2) and (3).
Obviously, ■ and ■ have fewer gate stages than (1), and can achieve high speed. FIG. 8 shows a different embodiment of the present invention, which is an improvement over the conventional FIG.
This is applied to ASU. Fig. 9(a) is a block diagram of a general 1-bit subtracter, Fig. 9(b) is its truth table, Fig. 9(c) is the same circuit diagram, and Fig. 1O is the same as that of Fig. 9. The circuit diagrams of the subtraction circuit 4 and the 0 judgment circuit 14 using a bit subtracter, FIGS. 11(a) and 12, are the circuit diagrams of the conventional X
Shift circuit, Y shift circuit diagram, FIG. 11(b) is a block diagram of the interrogation unit 51, FIG. 11(c) is a detailed circuit diagram of the same, FIGS. 13 and 14 are the X shift circuit of FIG. 8. 5, Y shift circuit 6 is shown.

In Fig. 8, 41 to 44 are selectors, and when the selection input (Cz+C2) is ``1'', the inputs on the A0 to A side are selected, and when the selection input is ``O'', the other input is selected. 45 is I) M through or one PM circuit, P
The M through circuit 45 is used when the mantissa part XM side of X is selected or addition (X+Y), and the -PM circuit 45 is used when the mantissa part YM side of Y is selected and subtraction (x-y) It is an inversion circuit. In this Fig. 8, ( ]) the absolute value of the difference in the exponent part of the input data I
1 is detected by the subtraction circuit 4, and when this is less than 31, the following circuit is finally selected.

First, for digit alignment. Mantissa part X depending on the value of XE-YE
M. Perform the shift shown in Figure 15 on YM. In other words, O fixation is not performed, and data does not need to be guaranteed in the range of IXE-YE≧3l. Next, for the mantissa parts XM' and YM' obtained by the above shifter, 3lbft
Calculations are performed by the addition/subtraction circuit 7. Next, the mantissa part ZM obtained by the above-mentioned addition/subtraction circuit 7
In order to normalize ', the normalization amount is detected by the normalization amount detection circuit 8. Here, the normalization amount detection circuit 8 is a priority encoder that receives the mantissa part ZM' as an input and gives priority to the upper bits.

The mantissa part ZM' is left-shifted using the above normalized amount and is used as the mantissa output. The subtraction circuit 10 subtracts the normalized amount from the larger of the exponent part data XE and YE, and sets this as the exponent part output B. ■ When the output IXE-YEl of the subtraction circuit 4 is 31 or more, the following circuit is finally selected. This circuit is
It consists of a selector 41, a through circuit, and a sign inversion circuit 45, and outputs the calculation result shown in FIG. 16. In FIG. 16, "instructions" refer to X+Y, X-Y, and "addition and subtraction" mean both addition and subtraction.

(3) As described above, finally, the outputs of (1) and (2) above are selected by the O determination circuit 14 from the calculation results of the subtraction circuit 4, and are used as the outputs ZM and ZE.

In this example, the calculation results of two systems processed in parallel are
The final selection is made by the O determination circuit l4. That is, in the floating point addition/subtraction circuit according to this embodiment, the O judgment time ml4 is not included in the critical bus. Also, the 31st
In the prior art shown in the figure, the O fixed circuits 12 and 13 which input the operation result of the O determination circuit 14 do not exist in the floating point addition/subtraction circuit according to this embodiment. In the conventional technology, the processing speed was significantly reduced due to the O judgment circuit and the O fixing circuit, but the present invention achieves high speed by avoiding this. Is Figure 17 to Figure 19 the mantissa data before addition and subtraction? In Figure 6, which is an embodiment of detecting the normalized amount from the data and increasing the speed, numeral 51 is a through or sign inverting circuit, which inverts the sign of the mantissa part YM in the case of subtraction. 8■ is the encoder of the normalization amount detection circuit 8, 52 to 54 are the subtraction circuits, 55 is the 1-bit correction detection circuit, 56 is the left 1 bit shifter, and 57 is the right 1 bit shifter.
bit shifter, 58. 59 is a selector. The shifter 56 shifts 1 bit to the left when 1 bit is insufficient, and the shifter 57 shifts 1 bit too much.
This returns l bits to the right. When it is desired to pass the normalized data as is, the path 60 is used.

(1) First, an example of normalization amount detection, which is a feature of the present invention, will be explained. Here, it is assumed that the mantissa data is a correction number representation of 2 without hidden bits, and only the addition instruction is considered.

First, if XM' and YM' of the mantissa data after digit alignment have the same sign, the addition result is not shifted to the left by normalization. In other words, in the addition result,
XM'. We only need to consider the case where YM' has different signs. Here, X. Consider a square that directly detects the normalized amount from M' and YM'. For the following explanation, XM', YM
11 Q
I+, if one side is ↓, it will be expressed as "'1"', and if both are 1, it will be expressed as "'2".Normalization occurs at the MSB, which is the sign 1 bit, in the addition result.
The same data as (most significant bit) is traced from MSB to 3bj. There are only two cases shown in FIG. 20.

That is, in the case of ■, the addition result is negative, and in the addition result, 1 continues up to the normalization position.

Looking at this as pre-addition data, t follows first, followed by 1 bit of 0. If a value other than 2 comes next, 1 will not continue below this in the addition result. If 2 comes after 0 in the pre-addition data, 1 continues in the addition result as long as 2 continues.

On the other hand, in the case of ■, the addition result is positive, and in the addition result, O continues up to the normalization position. Similarly to the case of ■, if we look at the data before addition, the digit follows first, followed by 1 bit of 2. If something other than O comes next, no O will follow in the addition result, and if O comes after 2 in the pre-addition data, O will continue in the addition result as long as 0 continues. From the above, by verifying the three adjacent bits in the pre-addition data, it can be determined whether the center bit can be the normalization position, so for each bit of the pre-addition data,
Perform the above verification with 3 bits including 1 bit on the left and right,
Set a flag on the corresponding bit, that is, set a flag on the part that becomes MSB when normalized after addition, and set this b
By passing the it sequence through the priority encoders 8, 8, a vehicle that detects the normalized amount is created. In order to explain in detail, the above cases (1) and (2) are divided into cases as shown in Fig. 21, and the flag positions obtained by normalized detection are also shown. Here, as noted in the remarks column in Figure 21, two types of normalization may be expected depending on the addition result. These are caused by carry from the lower bits, but the normalization amount differs by at most 1 bit.
Since it is easy to modify lbit, 1 bit is modified after addition.

By the way, in FIG. 21, if the above 1 bit needs to be corrected, enter "...011.X..." in the flag column.
A flag (indicated by "l") is set on the 2 bits where normalization can occur, but after addition, tbi
If it is assumed that t is to be corrected, it is sufficient to set a flag in either of these two bits. Taking this point into consideration, we will show an example of designing a logic circuit for normalization amount detection. Here, S and C are data before addition, and when "O", sc=oo. When “1”, SC=10. When it is "2", SC=OL. Also, for the 3 bits, SOCO. S1. C1, S 2G2.

a) When correcting the right 1 bit after addition.

In this case, of the 2-bit flag that takes into account the above 1-bit correction, the lower bit is flagged, and the upper bit is not flagged. Fig. 22 shows a Karnaugh diagram, and Fig. 23 shows a normalized claw detection circuit obtained from this Karnaugh diagram.
In Fig. 22, the part surrounded by nine frames in the top and bottom or left and right columns shows the method for converting the circuit into a mat obtained from the Karnaugh diagram, and the circuit in Fig. 23 is
Obtain it from a total of 6 Germans: o, SL, Cl, S2, and S2.

b) When correcting the left L bit after addition.

In this case, the upper bit of the 2-bit flag considering the above 1-bit correction may be set, and the lower bit flag may be either 11 Q'' or LL L''. FIG. 24 shows a Karnaugh diagram, and FIG. 25 shows a normalized residual detection concave path obtained from this Karnaugh diagram. This can be realized with a smaller circuit than when modifying the right 1 bit above.

C) When correcting 1 bit on the left or right after addition.

In this case, the lower bit of the 2-bit flag considering the 1-bit correction described above may be set, and the upper bit flag may be either "O'" or "{". Figure 27 shows a normalization amount detection circuit obtained from this Karnaugh diagram.It can be realized with a smaller circuit than the case of correcting the left 1 bit described above.

(2) Next, an embodiment of a 'tf dynamic decimal number ijH addition/subtraction l/I path with a mantissa part of 31 bits and an exponent part of 6 bits to which the present invention is applied will be described.

FIG. 17 is a block diagram of this embodiment considering correction of 1 bit on the left and right sides.

First, the subtraction circuit 4 extracts the exponent data X E of the input X.
and the exponent part data YE of Rokuryoku Y, and according to the result, the mantissa part data XM or YM is shifted to the right by the X shift circuit 5 and the Y shift circuit 6.
The digits are aligned by shifting YEI. Also,
Selector selects XE. Select the larger of YE and call it ZE'.

Next, in order to correct the normalization amount detection circuit described in (1), in the case of subtraction, the sign of the mantissa part of Y is inverted in the circuit 5l.

Next, the mantissa data XM' and YM' are added, and at the same time, the normalization amount NE is detected by the normalization amount detection circuit (1), and its output is encoded.

Next, the subtraction circuits 52 to 54 subtract the normalized amount NEfi from the exponent part ZE'. At this time, the extinction circuit 52~
54 takes into account the correction of 1 bit on the left and right sides in the normalization of the exponent part, and calculates ZE'-NE-1, ZE'-NE. Z
Calculate E'-NE ten. At the same time as the above subtraction, according to the normalized amount, ,! l
:． A shifter 9 normalizes the mantissa part zM'. After that, the detection circuit 55 selects the left 1 bit shifter 56 or the right 1 bit shifter 56.
．． The left and right 1-bit correction values by the bit shifter 57 are detected.

Finally, in accordance with the correction amount detected from the output of the left 31-bit shifter 9 at the same time as the normalization, the mantissa part ZM and the exponent part ZE are selected by the selector, and these are used as the output results of the floating point addition/subtraction circuit.

FIG. 18 is a block diagram of an embodiment that takes into account modification of the right 1 bit. As mentioned above in (1), the normalization amount detection circuit is more complex than the case of left and right 1-bit correction, but it requires a subtraction circuit for exponent normalization and an l for mantissa normalization.
One less bit shifter is required for ZE and ZM
selector 58. 59 is also small.

FIG. 19 is a block diagram of an embodiment that takes into account the modification of the left 1 bit. As described above in (1), the normalization amount detection circuit is simpler in the case of left 1-bit correction, but is more complex than in the case of left and right 1-bit correction.

However, the circuit scale of the subtraction circuit and 1-bit shifter for normalization is the same as in the case of right 1-bit correction.

In conventional floating-point addition/subtraction circuits, the normalization circuit detects the normalized amount from the output result of the mantissa addition/subtraction circuit, so normalization is not performed until the mantissa addition/subtraction results are detected. In this embodiment, in order to detect the normalized amount from the mantissa data before addition/subtraction, normalization is performed before outputting the result of addition/subtraction of the mantissa, and a high-speed floating point 4'(!)+addition/subtraction circuit is implemented. can be designed. In particular, since the subtraction of the exponent part occupies a large proportion of the time spent on normalization, the fact that this is performed prior to the addition/subtraction calculation of the mantissa part contributes to speeding up.

FIG. 28 shows a different tip embodiment for increasing the speed of FASU. That is, a normal normalization circuit (for example, see shifter 9 in FIG. 31) has an addition/subtraction circuit in the front stage. In case of force overflow. A shifter is provided to shift the data to the right by lbit. This 1-bit right shifter 91 may be made independent from the shifter 9, so these shifters 9,
9■ are arranged in parallel, for example, the top two outputs of the adder/subtractor 7
The selector l6 is controlled by the control signal formed using the bit.
If the configuration is such that the output is selected, the number of gate stages after the addition/subtraction M path 7 is reduced, and the speed can be increased accordingly. Further, by making only the critical bus independent from the shifter 9 instead of making all the right 1-bit shifters independent, the speed can be similarly increased.

Note that the present invention is not limited to the embodiments, and can be applied in various ways. For example, in the embodiment, there are two mantissa calculation paths and these are selected, but more than two paths may be used. [Effects of the Invention] As explained above, according to the present invention, the number of gate stages can be reduced, a plurality of calculation paths can be made to operate together, and only the desired output can be selected; The selection signal is also sent in parallel. Therefore, a high-speed 7l dynamic point data addition/subtraction circuit can be provided.

4. Figure 1 is a composition diagram of an embodiment of the present invention, Figure 2 is a configuration diagram showing a specific example of the same configuration, Figures 3 to 5 are diagrams showing the operation of the same configuration, Figures 6 and 7 are partially detailed circuit diagrams of the same configuration, Figure 8 is a configuration diagram of a different embodiment of the present invention, Figure 9 is a partially detailed explanatory diagram of the same configuration, and Figure 10 is a subtraction circuit. and O judgment circuit partial diagrams, FIGS. 11 and 12 are conventional (l!1 road diagrams,
The figure is a circuit diagram showing an improved example of the conventional i(tI path), Figures 15 and 16 are diagrams showing the effect of the configuration of Figure 8, and Figures 17 to 19 are diagrams of different embodiments of the present invention. Configuration diagram, 2nd
0 through 27 are partial explanatory diagrams of the same configuration, FIG. 28 is a configuration diagram of a different embodiment of the present invention, and FIGS. 29 through 31.
The figure is a configuration diagram of a conventional circuit, and FIG. 32 is a diagram showing the operation of FIG. 31.

4, 10. 31... Subtraction circuit, 5, 6...
Right 30bit? 7...Addition/subtraction circuit, 8...Normalization amount detection circuit, 81...Encoder, 9...Left 30
Bit shifter, 91...Right 1 bit shifter, 15...
・Shift amount detection circuit, 16...Selector, 21■・
...X shifter, 211...Y shifter, 21.24...
Digit alignment circuit, 22. 25...addition/subtraction circuit, 23.
26...Normalization times R6, 24,, 24■...lbi
t shifter, 27... selector, 33. 35... encoder, 41. 43...Selector, 45...PM
Through or one PM circuit, 5l... Through or inversion circuit, 55... Correction amount detection circuit, 56... Left 1 bit
Shifter, 57...Right 1 bit shifter, 59...Selector.

Output 2 No. 1 figure No. 3 figure No. 4 figure (b) (C) No. 9 figure Figure 15 Figure 16 XE YE XM YM Figure 18 Chest 19 Figure 20 Figure 21 (a) (c) (b) (d) Figure 22 Figure 24 (a) (c) (b) (d) Figure 26 Figure 27 Figure 29 ZE Figure 30 ZM Figure 32

Claims (5)

[Claims] (1) Floating point data characterized by having at least two arithmetic processing paths for floating point data, and comprising means for selecting the processing path using floating point data or intermediate data of arithmetic processing. Addition/subtraction circuit. (2) It has at least first and second mantissa data calculation paths, and the first mantissa data calculation path calculates the number of bits corresponding to the number of bits of the first and second mantissa data. A digit alignment circuit that aligns the digits of the mantissa data according to the difference in the exponent data, a first addition/subtraction circuit that performs addition/subtraction of the mantissa data whose digits have been aligned in the circuit, and the results of the addition/subtraction in the circuit. The first step detects the shift amount of 1 bit to the left or right from , and shifts 1 bit to the left or right according to the detection result.
shifter, and the second mantissa data calculation path shifts one of the first and second mantissa data according to the exponent data.
A digit alignment shift circuit that performs bit shifting, a second addition/subtraction circuit that performs addition or subtraction of the outputs of these shift circuits, and a normalization amount that is detected from the addition/subtraction results of the circuit and a normalization shift performed in accordance with the detection result. 1. A floating point data addition/subtraction circuit, comprising: a second shifter for adding and subtracting data; and selecting outputs of the first and second shifters according to a difference in exponent part data. (3) It has at least first and second mantissa data calculation paths, and the first mantissa data calculation path is a digit alignment circuit that performs digit alignment of mantissa data according to the difference in exponent data. , an addition/subtraction circuit that adds or subtracts mantissa data whose digits have been aligned by the circuit, a normalization amount detection circuit that detects a normalized amount from the calculation result of the circuit, and a the second mantissa data operation path has an input operand through path and an input operand sign inversion circuit, and the second mantissa data operation path has an input operand through path and an input operand sign inversion circuit, When the difference in the exponent part is larger than the number of digits in the mantissa part, the through data of the operand with the larger exponent part is used as the addition/subtraction result, and in the subtraction instruction for floating point data, the difference in the exponent part is greater than the number of digits in the mantissa part digit adjustment. When the number is larger than the number, if the minuend in the two operands is large, the through data on the minutand side is used as the addition/subtraction result, and when the subtrahend is large, the sign-inverted data on the subtrahend side is used as the addition/subtraction result, and the exponent part data The first and second
A floating-point data addition/subtraction circuit characterized in that the output of a mantissa data calculation path is selected. (4) A digit alignment circuit that aligns the mantissa data according to the difference in the exponent data, an addition/subtraction circuit that adds or subtracts the mantissa data digit-aligned by the circuit, and a pre-operation circuit in the circuit. a normalization amount detection circuit which sets a flag from a part of each bit of the mantissa data and a plurality of bits before and after it and inputs the flag to a normalization amount encoding circuit; A floating point system comprising: a normalization shifter for normalizing mantissa data; and means for selecting whether to shift the output data by 1 bit to the right or left from the output of the shifter. Data addition/subtraction circuit. (5) A digit alignment circuit that aligns the mantissa data according to the difference in the exponent data, an addition/subtraction circuit that adds or subtracts the mantissa data digit-aligned by the circuit, and the calculation results of the circuit. a normalization amount detection circuit that detects the normalization amount from the normalization amount; a normalization shifter that normalizes the mantissa data according to the normalization amount; 1. A floating point data addition/subtraction circuit comprising: a right shifter for performing a 1-bit right shift; and means for performing overflow detection and normalization amount detection in parallel using the output data of the addition/subtraction circuit.