JP2931632B2 - Digit shifter and floating point arithmetic unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a digit shifter in a floating point arithmetic unit mounted on various computer systems, and relates to a digit shift operation performed by a barrel shifter based on a shift value output from an adder / subtractor. An adder / subtracter that calculates the difference between the operand and the operand and outputs the difference as a binary shift value, with the aim of reducing the delay time and performing digit shifting at a higher speed. While inputting, each bit of the shift value output from the adder / subtractor or a plurality of continuous bit strings is input, and the input binary number is shifted by the number of bits corresponding to the weight of the bit or the bit string. In a digit shifter comprising a plurality of multiplexers capable of outputting, and a barrel shifter in which the plurality of multiplexers are connected in series. A plurality of multiplexers constituting the barrel shifter are provided in a stage preceding the multiplexer to which the lower-order bit or bit string of the output of the adder / subtractor is input.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a floating point arithmetic unit mounted on various computer systems and a digit shift unit in the same.

With the recent demand for faster computer systems, there is a strong demand for faster floating point arithmetic units. The operation of moving the mantissa by the exponent matching is indispensable for the arithmetic processing of the floating point, and the speed of the operation of the barrel shifter performed after the operation of subtracting the exponent can speed up the floating point operation.

[Prior Art] FIG. 7 shows a conventional floating point arithmetic unit. In this floating-point arithmetic unit, for example, the operands Fa2 ^ea and Fb2
^When adding or subtracting ^eb , the exponent adder / subtracter 1 subtracts the exponent ea of n bits and the exponent eb, and the exponent difference (= eb−ea)
Is used as a shift value, and exponent selector 2,
Output to the mantissa selector 3, barrel shifter 4 and floating point normalizer 6. The exponent selector 2 inputs the exponent ea and the exponent eb, and selects the larger exponent (ea> eb) based on the exponent difference.

On the other hand, the mantissa selector 3 inputs a mantissa Fa and a mantissa Fb each having l (≫n) bits, and based on the exponent difference, outputs a mantissa having a small exponent (in this case, Fb) to the barrel shifter 4 and a mantissa having a large exponent. (In this case, Fa) is converted to a mantissa adder / subtracter 5
Output to The barrel shifter 4 calculates the mantissa Fb by the index difference (=
eb-ea), and shifts it to an equal value to output it to the mantissa adder / subtracter 5. The mantissa adder-subtracter 5 equalization mantissa Fa, addition or subtraction of ^{Fb fa (= Fa ± Fb2Z (} eb-ea) = Fa2 -ec) to. Then, the exponent ea selected by the exponent selector 2 and the mantissa fa from the mantissa adder / subtracter 5 are output to the floating-point normalizer 6 where they are normalized and output as the exponent er and the mantissa Fr.

The barrel shifter 4 used in this floating-point arithmetic unit includes n multiplexers MP provided corresponding to the n output lines of the exponent adder / subtracter 1 as shown in FIG.
The multiplexers MP0 to MPn-1 are formed without regularity in the order of easy circuit design, and are connected in series. Each of the multiplexers MP0 to MPn-1 receives a numerical value of 1 bit, inputs each bit of the shift value of the exponent adder / subtracter 1, and converts the input numerical value into a bit corresponding to the weight of the bit. It can be shifted by several minutes and output to the next-stage multiplexer. For example, the multiplexer MP0 determines that there is no shift when bit 0 of the shift value is “0”,
Is "1", the input numerical value is shifted by one bit. The multiplexer MPn-1 has a bit n-1.
Is “0”, no shift is performed, and if bit n−1 is “1”, the input numerical value is shifted by 2 ⁿ⁻¹ bits.

[Problems to be Solved by the Invention] However, since the value of each bit of the shift value of the exponent adder / subtractor 1 has a carry output from a lower bit to an upper bit, the lower bit has a smaller delay time and the upper bit has a delay time. Time increases. Therefore, when the multiplexers MP0 to MPn-1 of the barrel shifter 4 are provided in descending order as shown in FIG. 8, the value of the most significant bit of the exponent adder / subtractor 1 is determined as shown in FIG. Thereafter, the output is determined in order from the foremost-stage multiplexer, and accordingly, the output of the next-stage multiplexer is determined sequentially. Therefore, the delay time t0 at which the output of the barrel shifter 4 is determined is the delay time required for determining the value of the most significant bit of the exponent adder / subtractor 1, and the delay time from the first-stage multiplexer MPn-1 to the last-stage multiplexer MP0 of the barrel shifter 4. And the processing speed becomes slow.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and an object of the present invention is to reduce a delay time of a digit shift operation of a numerical value performed by a barrel shifter based on a shift value output from an adder / subtracter, thereby achieving a higher speed. To provide a digit moving device capable of performing digit shifting.

Further, in the above-mentioned conventional floating-point arithmetic unit, as processing until obtaining both mantissas inputted to the mantissa adder / subtractor 5,
First, the exponent difference is obtained by the exponent adder / subtracter 1, and the mantissa having the larger exponent is output to the mantissa adder / subtractor 5 as it is by the mantissa selector 3 in accordance with the exponent difference, and the mantissa having the smaller exponent is selected and the barrel shifter is selected. 4, the delay is delayed until both mantissas input to the mantissa adder / subtracter 5 are determined, which is a problem in increasing the speed of floating-point arithmetic.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and an object of the present invention is to increase the mantissa processing speed before inputting to a mantissa adder / subtracter to increase the calculation processing speed as a whole device. It is an object of the present invention to provide a floating-point arithmetic device capable of performing such operations.

[Means for Solving the Problems] FIG. 1 shows a girder moving device of the present invention.

The adder / subtractor 1 calculates the difference between the operand and the operand, and outputs the difference as a binary shift value.

The barrel shifter 11 inputs a binary number, inputs each bit of the shift value output from the adder / subtractor 1 or a plurality of continuous bit strings, and inputs the bits by the number of bits corresponding to the weight of the bits or the bit strings. It is composed of a plurality of multiplexers MP0 to MPn-1 capable of shifting and outputting an inputted binary number. The plurality of multiplexers MP0 to MPn-1 are connected in series such that the multiplexer to which the lower-order bit or the bit string of the output of the adder / subtractor 1 is input is at a preceding stage.

Further, as shown in FIG. 2, the second invention calculates an exponent difference between both exponents of the operand and the operand and outputs the difference as a binary shift value. An exponent selector 2 for selecting a larger exponent based on the exponent difference calculated by the exponent unit 1, and input each mantissa expressed as a binary number of the operand and the operand, and output from the exponent adder / subtracter 1. A plurality of multiplexers MP0 to MPn− capable of inputting each bit or a plurality of continuous bit strings of the shift value to be shifted and shifting and outputting each input mantissa by the number of bits corresponding to the weight of the bit or the bit string.
1 and the plurality of multiplexers MP0 to MPn-1.
And the first and second barrel shifters 11 and 1 connected in series such that the lower bit or bit string of the output of the exponent adder / subtractor 1 is input so that the lower the bit or bit string is, the earlier it is.
A first mantissa selector 13 for selecting an output corresponding to a smaller exponent based on the exponent difference calculated by the exponent adder / subtractor 1 among outputs of the first and second barrel shifters 11 and 12; A second mantissa selector 14 for selecting a mantissa corresponding to a larger exponent based on the exponent difference calculated by the exponent adder / subtractor 1 among the mantissas of the operand and the operand.
A mantissa adder / subtracter 5 for calculating a difference between the two mantissas selected by the first and second mantissa selectors 13 and 14, an exponent selected by the exponent selector 2 and a mantissa obtained by the mantissa adder / subtractor 5. And a floating-point normalizer 6 for calculating a mantissa and an exponent normalized based on

[Operation] In the digit shifter according to the present invention, the lower-order bit of the output of the adder / subtractor 1 with the smaller delay time is input to the multiplexer preceding the barrel shifter 11, so that the output of the most significant bit of the shift value of the adder / subtractor 1 is output. Is determined, the input signal of the last-stage multiplexer of the barrel shifter 11 is determined, and after the output of the most significant bit of the adder / subtractor 1 is determined, the output is determined after a delay time in the last-stage multiplexer of the barrel shifter 11 has passed. Accordingly, the delay time in which the output of the barrel shifter 11 is determined is the sum of the delay time required for determining the most significant bit of the shift value of the adder / subtractor 1 and the delay time of the last-stage multiplexer of the barrel shifter 11, thereby improving the processing speed. Is done.

In the floating-point arithmetic device of the present invention, the mantissa adder / subtracter 5
As a process up to obtaining the both mantissas input to the arithmetic unit, an exponent difference is obtained from both exponents of the operand and the operand by the exponent adder / subtractor 1 to obtain a shift value, and based on the shift value, the first and second barrel shifters. Since the mantissas of the operand and the operand are shifted by 11, 12 and output to the first mantissa selector 13, the output corresponding to the smaller exponent is selected based on the shift value. , Barrel shifter 11,1
In each of the multiplexers MP0 to MPn-1, the shift operation is sequentially performed if the output of each bit of the shift value is determined. The delay time at which the outputs of the barrel shifters 11 and 12 are determined is the delay time of the shift value of the exponent adder / subtractor 1. The sum of the delay time required to determine the most significant bit and the delay time of the last-stage multiplexers of the barrel shifters 11 and 12 shortens the delay time and speeds up floating-point arithmetic.

[Embodiment] An embodiment in which the present invention is embodied in a floating-point arithmetic unit will be described below with reference to FIGS.

For the sake of convenience, the same components as those in FIGS. 7 and 8 are denoted by the same reference numerals, and the description thereof will be partially omitted.

As shown in FIG. 2, in the floating-point arithmetic device according to the present embodiment, a pair of barrel shifters 11 and 12 are provided, and each mantissa Fa, ^ea of the operands Fa2 ^ea and Fb2 ^eb is provided in each of the barrel shifters 11, 12. Fb is input respectively. Each barrel shifter 11,
12 has the same configuration, and is constructed by connecting n multiplexers MP0 to MPn-1 in series in this order as shown in FIG. Each of the multiplexers MP0 to MPn-1 has l (≫
n) Enter a numerical value (mantissa) consisting of bits,
The corresponding bits 0 to (n-1) of the n-bit shift value output from the exponent adder / subtracter 1 are input,
The input numerical value is shifted and output by the number of bits corresponding to the weight of the bit.

The mantissa selector 13 inputs each output (shifted mantissa) of each of the barrel shifters 11 and 12, and outputs the exponent adder / subtracter 1
, An output corresponding to the smaller exponent is selected and output to the mantissa adder / subtracter 5.
Further, the mantissa selector 14 calculates the operands Fa2 ^ea and Fb2 ^eb
, The mantissa corresponding to the larger exponent is selected based on the shift value of the exponent adder / subtracter 1, and is output to the mantissa adder / subtracter 5.

The mantissa adder / subtracter 5 performs addition / subtraction of both mantissas selected by the mantissa selectors 13 and 14, and outputs the result fa to the floating-point normalizer 6. The floating-point normalizer 6 calculates an exponent er and a mantissa normalized based on the exponent selected by the exponent selector 2 and the mantissa obtained by the mantissa adder / subtracter 5.
Calculate and output Fr.

Next, the configuration of each of the multiplexers MP0 to MPn-1 will be described. Since the multiplexers MP0 to MPn-1 have substantially the same configuration, the multiplexer MP1
Will be described with reference to FIG.

The multiplexer MP1 is composed of one element E0 to El-1. Each element E0 to El-1 is connected to OR circuits 15 and 16 and both OR circuits.
An AND circuit 17 receives the outputs of the circuits 15 and 16 as inputs. each
Output data lines DO0 to DOl-1 of the AND circuit 17 are connected to respective input data lines of the next-stage multiplexer (in this case, MP2). Data is input to one input terminal of the OR circuit 15 in each of the elements E0 to El-1 via input data lines DI0 to DIl-1, and data of bit 1 of the exponent adder / subtracter 1 is input to the other input terminal. Is entered.
The data obtained by inverting the data of the bit 1 is input to one input terminal of each OR circuit 16 via the inverter 18. The other input terminal of the OR circuit 16 of the elements E0 to El-3 is connected to the input data line. Data are input by being connected to DI2 to DIl-1. In addition, element El-2, El-1
The other input terminal of the OR circuit 16 is grounded and data "0" is input.

Therefore, when the bit 1 of the shift value of the exponent adder / subtracter 1 is “0”, the inverted data “1” is input to each OR circuit 16 via the inverter 18, so that each OR circuit 16
Is "1", and the output of each element E0 to El-1 is determined by the output of each OR circuit 15. At this time,
Since data "0" is input to one input terminal of the OR circuit 15, the output of each OR circuit 15 is connected to each of the input data lines DI0 to DI0.
It will be determined by the data of Il-1. That is,
When bit 1 is “0”, each element E0 to El−1
Appearing on the output data lines DO0-DOl-1 are the data of the input data lines DI0-DIl-1, and the shift operation is not performed.

Conversely, when the bit 1 is "1", each OR circuit 15
, The output of each OR circuit 15 is “1”, and the output of each element E0 to El−1 is
Determined by the output of circuit 16. At this time, each OR circuit
Since the inverted data "0" is input to one input terminal of the element 16 through the inverter 18, the element El-
2, each OR circuit 16 of elements E0 to El-3 other than El-1
Will be determined by the data on each of the input data lines DI2 to DIl-1. That is, when the bit 1 is "1", the output data lines DOl-2, D1 of the elements El-2, El-1 are output.
The data appearing on Ol-1 is "0", "0" regardless of the data on the input data lines DIl-2 and DIl-1.
The data appearing on the output data lines DO0 to DOl-3 of E0 to El-3 become the data of the input data lines DI2 to DIl-1 and are shifted by 2 bits.

The other multiplexers MP0, MP2 to MPn-1 are each composed of one element E0 to El-1 similarly to the multiplexer MP1, and one input terminal of the OR circuit 16 of each element E0 to El-1 is the same as that of the multiplexer MP1. The difference is that the number of bits corresponding to the weight of each bit of the shift value of the exponent adder / subtracter 1 is connected to the upper input data line by the number of bits.
When each bit is "1", the input numerical value is shifted by the number of bits corresponding to the weight of the bit. For example, when the bit i of the shift value is “1”, the multiplexer MPi shifts the input numerical value by ²ⁱ bits.

Therefore, when the arithmetic processing is performed in the floating-point arithmetic device configured as described above, after the exponents ea and eb and the mantissa F (Fa or Fb) are determined as shown in FIG. When the output of each bit of the output shift value is sequentially determined, the input signal of each multiplexer of the barrel shifters 11 and 12 corresponding to the bit is determined.
That is, when the output of the bit n-1 is sequentially determined, the input signal of the last-stage multiplexer MPn-1 of the barrel shifters 11 and 12 is determined, so that the output of each barrel shifter 11 and 12 is the most significant bit of the exponent adder / subtractor 1. And the delay time of the final stage multiplexer of the barrel shifter 11, which is the sum t1 of the delay time required to determine the output of the barrel shifter 11. Thus, the shift processing speed can be improved as compared with the delay time t0 of the conventional barrel shifter shown in FIG. it can.

In the floating-point arithmetic device of the present embodiment, both mantissas Fa and Fb
Is shifted in advance, and the output corresponding to the smaller exponent is selected by the mantissa selector 13 and output to the mantissa adder / subtractor 5, so that the capability of the barrel shifters 11 and 12 can be utilized without deteriorating. It is possible to speed up floating-point operations.

Another Embodiment Next, another embodiment will be described with reference to FIGS.

FIG. 5 shows the barrel shifter 20 and the multiplexer MP0.
MPMPk (K = n / 2; n is an even number) connected in this order in series. Each of the multiplexers MP0 to MPk inputs a bit string composed of two consecutive bits among the bits of the shift value composed of n bits output from the exponent adder / subtracter 1, and converts the inputted numerical value into the number of bits corresponding to the weight of the bit string. The output can be shifted by minutes. For example, if the bit string of the shift value is bit i, bit i +
When it is 1, the input numerical value can be shifted by (2 ⁱ +2 ^{i + 1} ) bits.

Next, the configuration of each of the multiplexers MP0 to MPk will be described. However, since each of the multiplexers MP0 to MPk has substantially the same configuration,
Description will be made with reference to the drawings.

The multiplexer MP0 includes one element E0 to El-1 similarly to the multiplexer in the barrel shifter 11,
Bit 0 and Bit 1 of the shift value of the exponent adder / subtracter 1
And a control circuit section 21 for inputting the The control circuit 21 is 4
N NAND circuits 27 to 30 and inverters 31 and 32, and N
Data obtained by inverting the data of bit 0 and bit 1 is input to the AND circuit 27 via the inverters 31 and 32. NA
The ND circuit 28 receives the data of bit 0 and the data obtained by inverting the data of bit 1 via the inverter 32.
The data of bit 0 and the data of bit 1 are input to the circuit 29 via the inverter 31, and the data of bit 0 and bit 1 are input to the NAND circuit 30.

Each element E0 to El-1 has an OR circuit 22 to 25 and an OR circuit 22
And an AND circuit 26 to which the outputs of .about.25 are input. The output signal of each of the NAND circuits 27 to 30 is input to one input terminal of each of the OR circuits 22 to 25 in each of the elements E0 to El-1.

Data is input to the other input terminal of each OR circuit 22 via input data lines DI0 to DIl-1, respectively. The other input terminals of the OR circuits 23 of the elements E0 to El-2 are connected to input data lines DI1 to DIl-1, respectively, so that data is input. The other input terminals of the OR circuits 24 of the elements E0 to El-3 are input data lines DI2 to DIl, respectively.
-1 to input data. Further, the other input terminals of the OR circuits 25 of the respective elements E0 to El-4 are connected to input data lines DI3 to DIl-1, respectively, so that data is input. The other input terminals of the OR circuits 23 to 25 of the element El-1, the OR circuits 24 and 25 of the element El-2, and the OR circuit 25 of the element El-3 are grounded, and data of "0" is input. ing.

Therefore, when the bit 0 and bit 1 of the shift value of the exponent adder / subtracter 1 are “0” and “0”, only the output of the NAND circuit 27 becomes “0”. The output is the output of each OR circuit 22, that is, each input data line DI0 to DIl-
1 and no shift operation is performed.

When the bit 0 and bit 1 of the shift value of the exponent adder / subtracter 1 are "1" and "0", only the output of the NAND circuit 28 becomes "0". Is each
The output of the OR circuit 23, that is, the data of the input data lines DI1 to DIl-1 and the output data line DO
Data appearing at 0 to DOl-1 is shifted by one bit. Further, when the bit 0 and bit 1 of the shift value of the exponent adder / subtracter 1 are “0” and “1”, only the output of the NAND circuit 29 becomes “0”. Is the output of each OR circuit 24, that is, each of the input data lines DI2 to DIl-1.
Output data line determined by the data and ground
Data appearing on DO0-DOl-1 is shifted by two bits. When the bit 0 and bit 1 of the shift value of the exponent adder / subtracter 1 are “1” and “1”, only the output of the NAND circuit 30 becomes “0”. Is the output of each OR circuit 25, that is, each of the input data lines DI3 to DIl−
1 and the data determined by the ground and appearing on the output data lines DO0 to DOl-1 are shifted by 3 bits.

The other multiplexers MP1 to MPK in this example also have one element E0 to E like the multiplexer MP0.
l-1. One input terminal of each of the OR circuits 23 to 25 is connected to each input data line so that the shift value of the exponent adder / subtracter 1 can be shifted by the number of bits corresponding to the weight of the bit string.
It is different in that it is connected to DI0 to DIl-1.

In the above embodiment, the barrel shifter constituted by a multiplexer for inputting each bit of the shift value of the exponent adder / subtracter 1 is used.
This was implemented in the barrel shifter 20 composed of a multiplexer that inputs a bit string consisting of 11 and two consecutive bits.
The present invention may be implemented in a barrel shifter in which a multiplexer for inputting bits and a multiplexer for inputting a bit string are mixed.

[Effects of the Invention] As described above in detail, according to the girder moving device of the present invention,
There is an excellent effect that the delay time of the digit shift operation performed by the barrel shifter based on the shift value output from the adder / subtracter can be reduced, and the digit shift can be performed at a higher speed.

Further, according to the floating-point arithmetic device of the present invention, there is an excellent effect that the arithmetic processing speed of the mantissa before input to the mantissa adder / subtracter can be increased and the arithmetic processing as a whole can be speeded up.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a digit shift device according to one embodiment of the present invention, FIG. 2 is an electric block circuit diagram showing a floating point arithmetic unit according to one embodiment, and FIG. 3 is an example of a multiplexer. FIG. 4 is a waveform diagram showing the operation of one embodiment, FIG. 5 is a block diagram showing another example of a digit shifter, FIG. 6 is a logic circuit diagram showing another example of a multiplexer, FIG. FIG. 1 is an electric block circuit diagram showing a conventional floating point arithmetic unit, FIG. 8 is a block diagram showing a conventional digit shift unit, and FIG. 9 is a waveform diagram showing the operation of the conventional example. In the figure, 1 is an exponent adder / subtracter, 2 is an exponent selector, 5 is a mantissa adder / subtractor, 6 is a floating-point normalizer, 11 and 12 are barrel shifters, 13 is a first mantissa selector, 14 is a second mantissa selector, MP0 to MPn-1 are multiplexers.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 7/38-7/54 G06F 7/00 G06F 5/01

Claims (2)

(57) [Claims] An adder / subtractor (1) for obtaining a difference between an operand and an operand and outputting the difference as a binary shift value, and a binary numerical value input and the adder / subtracter (1)
A plurality of multiplexers capable of inputting each bit of the output shift value or a plurality of continuous bit strings, shifting the input binary number by the number of bits corresponding to the weight of the bits or the bit string, and outputting the result. MP0 to MPn−
1), and the plurality of multiplexers (MP0 to MPn)
-1) and a barrel shifter (11) connected in series. A plurality of multiplexers (MP0 to MPn-1) constituting the barrel shifter (11) are connected to the output of the adder / subtracter (1). The digit shift device characterized in that a multiplexer to which a lower-order bit or a bit string is input is provided at a preceding stage. 2. An exponent adder / subtracter (1) for obtaining an exponent difference between exponents of an operand and an operand and outputting the difference as a binary shift value, and an exponent operated by the exponent adder / subtracter (1). An exponent selector (2) for selecting a larger exponent based on the difference; inputting each mantissa expressed as a binary number of an operand and an operand, and output from the exponent adder / subtracter (1) A plurality of multiplexers (MP0 to MPn-1) capable of inputting each bit of the shift value or a plurality of continuous bit strings and shifting and outputting each input mantissa by the number of bits corresponding to the weight of the bits or the bit strings. Consisting of
First and second multiplexers (MP0 to MPn-1) connected in series such that the multiplexer to which the lower-order bit or bit string of the output of the exponent adder / subtractor (1) is input is at a preceding stage as the multiplexer is input. Barrel shifter (11,1
2) and a first selecting an output corresponding to a smaller exponent based on the exponent difference calculated by the exponent adder / subtractor (1), from the outputs of the first and second barrel shifters (11, 12). And a second mantissa that selects a mantissa corresponding to a larger exponent based on the exponent difference calculated by the exponent adder / subtracter (1) among the mantissas of the operand and the operand. A selector (14), a mantissa adder / subtracter (5) for calculating a difference between the two mantissas selected by the first and second mantissa selectors (13, 14), and an exponent selected by the exponent selector (2). A floating-point arithmetic device comprising: a floating-point normalizer (6) for calculating a mantissa and a normalized exponent based on the mantissa obtained by the mantissa adder / subtracter (5).