JP2001092639A - Division and square root arithmetic unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quickly operate division and following square root calculation. SOLUTION: At the time of the division, the division is started by inputting a divided through a register 21, and a divider through a register 31 to a carry preservation type adder, and a next quotient is repeatedly predicted by a quotient selecting circuit from obtained sum components and carry components, and the positive components and negative components of the quotient in a redundant format being a divided result are preserved in registers 36 and 37. At the time of the following square root calculation, the positive components and negative components of the quotient in the redundant format are directly inputted through aligners 23 and 24 to the carry preservation type adder, and the negative components are subtracted from the positive components of the quotient so that an intermediate result can be calculated, and the square root calculation is started to this, and the next quotient is predicted by the quotient selecting circuit from the obtained sum components and carry components, and a route multiple generated by a root multiple generating circuit by using the negative components from the positive components of the quotient is inputted to the carry preservation type adder, and the square root calculation is repeatedly operated. Thus, it is not necessary to convert the divided result into a non-redundant format to normalize it, and it is possible to quickly operate the square root calculation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a division / square root operation unit for a floating-point arithmetic unit, and more particularly to a high-speed division / square root operation unit.

[0002]

2. Description of the Related Art In recent years, with the increase in software for handling three-dimensional graphics, calculations such as sqrt (y / x) are often used in coordinate calculation and the like, and actual calculations using a division / square root calculation device. Is performed.

FIG. 2 is a block diagram showing a configuration example of a conventional division / square root operation unit. Here, an example is shown in which a radix-2 quotient digit set {-1, 0, +1} is used, and a carry-save-type adder is used as a partial remainder operation means.
For example, in this division / square root operation device, sqrt (y /
In calculating x), first, a division of y / x is performed, and then a two-stage operation of square rooting the result is performed.

The selector 1 is a selector for selecting, as an input operand, one of mantissa data of a floating-point operand y input from the outside and mantissa data of a preceding operation result. This operand y corresponds to the dividend in the case of division, and the square root in the case of square root.

The register 2 is a register for storing the output of the selector 1.

The aligner 3 adds a hidden bit to the most significant bit at the time of division and adds a hidden bit to the most significant bit at the time of square root, and then performs digit matching by the even / odd number of the exponent part.

The selector 4 selects one of the output of the aligner 3 and the output of the register 6 for storing the sum component of the output of the carry save type adder 5 and inputs the sum to the sum input of the carry save type adder 5. It is.

The selector 12 selects one of all0 and the output of the register 7 for storing the carry component of the output of the carry save type adder 5, and inputs the result to the carry input of the carry save type adder 5. is there.

The register 13 is a register for storing a mantissa of an input operand x in a floating-point format from the outside. This operand x corresponds to a divisor in the case of division.
Not used in Kaiping.

The inverter 14 is an inverter for inverting the output of the selector 16.

The selector 15 is a selector which outputs the output of the selector 16 and its inversion, and one of the three inputs of all0 in accordance with the predicted quotient digit output from the quotient selection circuit 8. When the predicted quotient is -1, the output of the selector 16 is provided.
The inversion of the output of 6, and if 0, all0 is selected.

The selector 16 outputs the output of the register 13 at the time of division and the output of the route multiple generation circuit 11 at the time of square root, depending on whether the operation to be performed is division or square root.

The outputs of the selector 4, selector 12, and selector 15 are input to the carry-save-type adder 5, and by adding them, a partial remainder is output in the form of a sum component and a carry component. The reason why the quotient digit predicted by the quotient selection circuit 8 is input is that when the quotient digit is +1, 1 is input to the lowest carry input to perform subtraction.

Registers 6 and 7 are registers for storing the sum component output and the carry component output of the carry save type adder, respectively.

The quotient selection circuit 8 is a circuit which receives, from the output of the carry-save type adder 5, upper bits having a fixed width determined by a radix as input and predicts a quotient digit from the quotient digit set.

Registers 9 and 10 are registers for storing a quotient in a redundant binary format in accordance with the output of quotient selection circuit 8. The register 9 stores the positive component of the quotient, and the register 10 stores the negative component of the quotient.

When the output of the quotient selection circuit 8 is +1, the corresponding bit of the register 9 is 1 and the corresponding bit of the register 10 is 0.
Is 0, the corresponding bit of the register 9 is 0, and the corresponding bit of the register 10 is 1.
0 is stored in each corresponding bit of 0.

The route multiple generation circuit 11 is a circuit for generating a route multiple corresponding to a divisor at the time of the square root operation from the outputs of the registers 9 and 10.

The carry adder 17 calculates the value of the register 10 which is the negative component of the quotient from the output of the register 9 which is the positive component of the quotient.
Is an adder for converting the quotient of the redundant binary format into the quotient of the non-redundant binary format by subtracting the output of.

The normalizing circuit 18 is a circuit for normalizing the output of the carry propagation type adder 17.

The register 19 is a register for storing the output of the normalizing circuit 18.

The register 20 is a register for temporarily storing the quotient digit output from the quotient selection circuit 8.

First, in the preceding division, the mantissa data of the dividend y is input to the register 2 through the selector 1 and the mantissa data of the divisor x is input to the register 13. The mantissa data of the dividend y is input to the aligner 3, and after adding hidden bits, the selector 4
, And is input to the carry save type adder 5.

In the first operation, the quotient selection circuit 8 predicts +1 as a quotient, so that the selector 15
The divisor x whose polarity is inverted is selected by 4 and is input to the carry save type adder 5 through the selector 16. or,
Carry 1 is input from the bottom.

Thereafter, the carry save type adder 5 performs the first addition based on the input data, stores the sum component and the carry component obtained from the result in the registers 6 and 7, And carry components are input through selectors 4 and 12.

At the same time, the quotient selection circuit 8 predicts the next quotient digit from the sum component and the carry component of the carry save type adder 5, and controls switching of the selector 15 accordingly.

The quotient predicted by the quotient selection circuit 8 is +1 if the corresponding bit of the register 9 is 1, 0 if the corresponding bit of the register 10 is -1, and 0 if the corresponding bit of the register 9 is -1. , 1 is stored in the corresponding bit of the register 10, and 0 is stored in the corresponding bit of the registers 9 and 10, respectively.

When the quotient predicted by the quotient selection circuit 8 is -1, the selector 15 selects the divisor x as it is, and when +1, selects the selector whose polarity is inverted by the inverter 14;
If 0, select all0. The data selected by the selector 15 is input to the carry save type adder 5.

Thereafter, the carry save type adder 5 performs a second addition based on the input data, stores the sum component and the carry component obtained from the result in the registers 6 and 7, The component and the carry component are input through selectors 4 and 12.

At the same time, the quotient selection circuit 8 predicts the next quotient digit from the sum component and the carry component of the carry save type adder 5, and controls switching of the selector 15 accordingly.

The quotient predicted by the quotient selection circuit 8 is +1, -1,
The value described above is stored in the corresponding bit of the register 9 or the register 10 by one of 0.

The above division operation is performed cyclically,
When a quotient having a predetermined number of digits is obtained, the arithmetic operation of the carry save type adder 5 ends, and the positive and negative components of the quotient, which are the final division results, are stored in the registers 9 and 10 in a redundant binary number format. Saved in.

The carry propagation adder 17 calculates the positive component and the negative component of the quotient in the redundant binary format to obtain a quotient in the non-redundant binary format. The quotient in the non-redundant binary format is normalized by the normalizing circuit 18 and is stored in the register 2 through the selector 1 and used for the next square root operation.

In the next square root operation, the normalized non-redundant binary format y / x mantissa data stored in the register 2 is input to the aligner 3. After adding the hidden bit, the aligner 3 performs an operation of adjusting the digits of the mantissa of y / x depending on whether the separately obtained exponent of y / x is odd or even, and obtains the obtained result (mantissa Data) selector 4
Is input to the carry save type adder 5 through. When the carry-preserving adder 5 performs addition for the first time, the first square root operation is advanced by selecting +1 as a quotient and performing addition.
The resulting sum and carry components are stored in registers 6 and 7 and then input to carry-save adder 5 through selectors 4 and 12.

The quotient selection circuit 8 predicts the next quotient digit from the sum component and the carry component of the carry save type adder 5.

If the quotient predicted by the quotient selection circuit 8 is +1, the corresponding bit of the register 9 is 1; the corresponding bit of the register 10 is 0; If 1 is 0 in the corresponding bit of 10 and 0 is stored in the corresponding bit of the registers 9 and 10, respectively.

Thereafter, the positive and negative components of the quotient written in the registers 9 and 10 are input to the route multiple generation circuit 11. The route multiple generation circuit 11 creates an intermediate result from the input positive and negative components of these quotients,
The route multiple is obtained from the intermediate result, and is input to the selector 15 via the selector 16.

The carry save type adder 5 performs the next addition using the input sum component, carry component and root multiple, and stores the resulting sum component and carry component in the registers 6 and 7. , Through the selectors 4 and 12 to the carry save type adder 5.

The quotient selection circuit 8 predicts the next quotient based on the sum component and the carry component of the carry save type adder 5, and determines whether the predicted quotient is +1, −1, or 0, and stores the quotient in the register 9 or 10. The above value is stored in the corresponding bit. The positive and negative components of the quotient stored in the registers 9 and 10 are input to the route multiple generation circuit 11.

The route multiple generation circuit 11 creates an intermediate result from the input positive and negative components of the quotient, obtains a route multiple from the intermediate result, and inputs this to the selector 15 via the selector 16. Thereafter, the carry save type adder 5 performs the following square root operation.

When such a square root operation is performed cyclically to obtain a quotient of a predetermined number of digits, the carry-save adder 5
Is completed, and the positive and negative components of the quotient, which are the final square root operation results, are stored in the registers 9 and 10 in a redundant binary number format.

The carry propagation adder 17 calculates a positive component and a negative component of the quotient in the redundant binary format to obtain a quotient in the non-redundant binary format.

The normalization circuit 16 normalizes the quotient in the non-redundant binary format. Since the normalized quotient is a mantissa part, it is combined with a separately calculated exponent part, stored in the register 19, and output as a result of sqrt (y / x) calculation.

[0044]

SUMMARY OF THE INVENTION The above-described conventional division
In the square root arithmetic unit, a desired result can be obtained by continuously performing the square root calculation using the result of the division of y / x as an input. However, in such a division / square root arithmetic device adopting a method of storing such a quotient in a redundant binary format, the quotient is stored in registers 9 and 10 in the form of a signed redundant binary number, and after the operation is completed, the carry propagation type is stored. In general, the data is converted into ordinary non-redundant binary format data by the adder 17 and then normalized by a normalization circuit 18 to obtain a quotient or a square root.

Therefore, even when the result of y / x is used as an input for the next square root operation as described above, once, the carry-propagating adder 17 uses the non-redundant binary number representation and the normalization circuit 18 Since the result of the normalization is taken again as input data into the carry-save-type adder 5, there is a problem that it takes time to start the next square root operation, which hinders an increase in the speed of the operation. There was a problem.

The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a division / square root operation device capable of performing division and a square root operation performed subsequently thereto at high speed. It is to be.

[0047]

In order to achieve the above object, a feature of the present invention is to provide an arithmetic unit for calculating a partial remainder for performing floating-point division and floating-point square root operation. In a division / square root operation device for storing the quotient and square root obtained by the division and square root operations in a signed redundant binary format, the division is performed in advance using a divisor and a dividend input from outside, and the result is obtained. The next square root operation is started immediately using the positive and negative components of the quotient stored in the signed redundant binary format as input data of the partial remainder operation means.

A feature of the invention according to claim 2 is that an inverted portion obtained by inverting a positive component of a quotient and a negative component of the same quotient stored in a signed redundant binary format, which is the result of the division, is represented by an exponent of the result of the division. After shifting by the shift amount obtained from the division and the input divisor and the input dividend, the quotient and the carry data to the lowest order are input to the partial remainder calculation means, so that the negative component from the positive component of the quotient is obtained. The square root operation is performed on the result of the subtraction.

A feature of the present invention is that a carry-save adder is used as the partial remainder calculating means.

A feature of the present invention resides in that a redundant binary adder is used as the partial remainder operation means.

According to the fifth aspect of the present invention, the dividend is one.

According to the above invention, for example, y / x
Is obtained, the positive and negative parts of the quotient resulting from the operation are obtained in a redundant binary number format. Without converting the positive and negative parts of the quotient in this redundant binary format to the non-redundant binary format, the following sqrt
It is used as an input for square root calculation for obtaining (y / x). As a result, it is possible to omit the time required for converting the preceding division result into the non-redundant binary format and normalizing the result, which is conventionally required, and to start the square root operation earlier by that much.

[0053]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the division / square root operation device of the present invention.

Here, a radix-2 quotient digit set ｛−
An example in which 1,0, + 1} is used and a carry-save-type adder is used as a partial remainder operation means will be described.

The register 43 temporarily stores the input operand (y), and the register 44 temporarily stores the input operand (x).

The register 21 temporarily stores the mantissa of the input operand (y), and the register 45 temporarily stores the exponent of the input operand (y).

The register 31 temporarily stores the mantissa of the input operand (x), and the register 46 temporarily stores the exponent of the input operand (x). This operand x is
This is the divisor in the case of division. Not used in Kaiping.

The selector 22 selects one of the mantissa of the operand input from the outside and the mantissa of the preceding operation result as the operand 1. This operand 1 (y)
Is the dividend in the case of division and the square root in the case of square root.

The aligners 23 and 24 are provided with a shift amount detector 32.
Is a circuit that shifts the input operand mantissa in accordance with the output of, adds hidden bits, and outputs the result.

The selector 25 selects one of the output of the aligner 23 and the output of the register 28 for storing the sum component of the output of the carry save type adder 27 and inputs the sum to the sum input of the carry save type adder 27. .

The selector 26 outputs all0 in the case of the input at the time of the start of the preceding division, the output of the aligner 24 in the case of the input in the start of the subsequent square root operation, and the output of the register 29 in the case of the loop operation. Select each.

The inverter 33 is an inverter for inverting the output of the register 31.

The selector 35 selects the output of the register 31 at the time of division and the output of the route multiple generation circuit 38 at the time of square root, depending on whether the operation to be performed is division or square root.

The selector 34 outputs the output of the selector 35, its inversion, and one of the three inputs all0 in accordance with the predicted quotient digit output from the quotient selection circuit 30. Here, when the predicted quotient is −1, the output of the selector 35 is obtained, when the predicted quotient is +1, the output of the selector 35 is inverted, and when the predicted quotient is 0, al is output.
10 are respectively selected.

The outputs of the selectors 25, 26 and 34 are input to the carry save type adder 27, and a partial remainder is output in the form of a sum component and a carry component by adding them. The quotient digit predicted by the quotient selection circuit 30 is input to the carry save type adder 27. When the quotient digit is +1, 1 is input to the least significant carry input to perform subtraction. It is for.

Registers 28 and 29 are registers for storing the sum component output and the carry component output of the carry save type adder 27, respectively.

The quotient selection circuit 30 includes a carry save type adder 27
Is a circuit that receives upper bits of a constant width determined by a radix as inputs and predicts a quotient digit from the quotient digit set.

The registers 36 and 37 are registers for storing the quotient in a redundant binary format in accordance with the output of the quotient selection circuit 30. The positive component of the quotient is stored in the register 36 and the register 3
7 stores the negative components of the quotient.

When the output of the quotient selection circuit 30 is +1, the corresponding bit of the register 36 is 1; when the output is 1, the corresponding bit of the register 36 is 0;
If the corresponding bit of the register 37 is “1”, and if it is “0”, “0” is stored in the corresponding bit of the registers 36 and 37.

The shift amount detector 32 receives the exponent part and the mantissa part of the divisor data x and the dividend data y in the preceding division and compares the two mantissa parts with each other, thereby obtaining the shift necessary for normalizing the division result. This is a circuit for calculating the amount and calculating the shift amount of the redundant binary division result fed back from the quotient registers 36 and 37 from the exponent part of the division result calculated from both exponent parts and the shift amount.

The root multiple generation circuit 38 is a circuit for generating a root multiple corresponding to a divisor at the time of the square root operation from the outputs of the registers 36 and 37.

The carry propagation type adder 39 subtracts the output of the register 37, which is the negative component of the quotient, from the output of the register 36, which is the positive component of the quotient, to convert the quotient in the redundant binary form into the non-redundant binary. It is an adder for converting to a quotient in hexadecimal format.

The normalizing circuit 40 is a circuit for normalizing the output of the carry propagation type adder 39.

The register 41 is a register for storing the output of the normalization circuit 40. The register 47 is a register for temporarily storing the quotient digit predicted by the quotient selection circuit 30.

Next, the operation of this embodiment will be described. This example is a division / square root operation device for calculating sqrt (y / x). When calculating sqrt (y / x), first, a division y / x is performed, and a two-stage operation of performing a square root operation on the result is performed.

First, in the division performed in advance, the dividend y is input to the register 43 in a floating-point format, and the divisor x is input to the register 44 in a floating-point format.

First, division is performed first. At this time, the selector 26 is switched to predict all0, and all0 is input to the carry-save adder 27 through the selector 26.

Initially, since the selector 22 is switched to the external input side, the mantissa of the dividend y is input to the aligner 23 through the selector 22, adds a hidden bit, and then carries through the selector 25 and stores the carry. It is input to the type adder 27. Note that initially, the selector 25 is switched to select the output of the aligner 23.

In the first operation, the quotient selection circuit 30
In order to predict +1 as the quotient, the selector 34 selects the divisor x whose polarity is inverted by the inverter 33, and this is input to the carry-save adder 27 through the selector 35. At the time of division, the selector 35 is switched so as to select the output of the register 31.

Next, the carry save type adder 27 performs the first addition based on the input data described above, and stores the sum component and the carry component obtained from the result in the registers 28 and 29.

At the same time, the quotient selection circuit 30 predicts the next quotient digit from the upper bits of the sum component and the carry component output from the carry save type adder 27, thereby controlling the switching of the selector 34 and When the quotient predicted by the quotient selection circuit 30 is +1, the corresponding bit of the register 36 is 1, the corresponding bit of the register 37 is 0, and when the quotient is -1, the corresponding bit of the register 36 is 0, and the corresponding bit of the register 37 is 0. When 1 is 0, 0 is stored in the corresponding bit of the registers 36 and 37, respectively.

Thereafter, the selectors 25 and 26 are switched to the inner loop side, and the above-mentioned sum component and carry component are input to the carry save type adder 27 through the selectors 25 and 26.

The selector 34 sets the divisor x if the predicted quotient digit is -1 and the inverter 33 if the predicted quotient digit is +1.
Is selected, and if it is divisible, switching is made to select all0, and the output data is input to the carry save type adder 27.

As a result, the carry save type adder 27
A second addition is performed based on the input data, and the sum component and carry component obtained from the result are stored in a register 28.
Is stored in the register 29.

At the same time, the quotient selection circuit 30 predicts the next quotient digit from the sum component and the carry component of the output of the carry save type adder 27, and thereby controls the selection of the selector 34.

The quotients predicted by the quotient selection circuit 30 are +1 and −
The register 36 or the register 37 is set by one of 1 and 0.
The above value is stored in the corresponding bit of.

After that, the sum component and the carry component are input to the carry save type adder 27 through the selectors 25 and 26.

The above division operation is performed cyclically,
When a quotient of a predetermined number of digits is obtained, the carry save type adder 27
Is completed, and the positive and negative components of the quotient, which are the final division results, are stored in the registers 36 and 37 in the redundant binary format.

In the next square root operation, the selector 22 is switched to select the inner loop side, and the register 35
Switching is performed so as to select the output of the route multiple generation circuit 38.

Thus, the positive component of the redundant binary number quotient stored in the register 36 is input to the aligner 23 through the selector 22, and the negative component of the redundant binary number quotient stored in the register 37. The components are converted in polarity by the inverter 42 and input to the aligner 24.

Before that, the shift amount detector 32 receives the exponent part and the mantissa part of the divisor data x and the dividend data y in the preceding division and performs a magnitude comparison of the two mantissa parts, thereby normalizing the division result. Is obtained, and from the exponent part of the division result calculated from both exponent parts and the shift amount, the shift amount of the redundant binary division result fed back from the quotient registers 36 and 37 is obtained.
The calculated shift amount is output to the aligners 23 and 24.

The aligners 23 and 24 are provided with the shift amount detector 3
In accordance with the shift amount of 2, the digit of the quotient positive component and the negative component of the quotient whose polarity is inverted are aligned, and the positive and negative components of the quotient whose digits are matched are input to the carry save adder 27. Is done.

The carry save adder 27 subtracts the negative component of the quotient from the positive component of the quotient to produce an intermediate result.
The first square root operation is advanced by selecting +1 as the quotient and performing the first addition, and the resulting sum and carry components are stored in registers 28 and 29.

Thereafter, the selectors 25 and 26 are switched to the inner loop side, and the sum component and the carry component stored in the registers 28 and 29 are input to the carry save type adder 27.

At this time, the quotient selection circuit 30 predicts the next partial quotient from the upper bits of the sum component and the carry component of the carry save type adder 27.

The quotient selection circuit 30 determines that the predicted quotient is +1 or −
The register 36 or the register 37 is set by one of 1 and 0.
The above value is stored in the corresponding bit of.

Thereafter, the positive and negative components of the quotient written in the registers 36 and 37 are converted into a route multiple generation circuit 38.
Is input to The root multiple generation circuit 38 creates an intermediate result from the input positive and negative components of the quotient, obtains a root multiple from the intermediate result, and inputs this to the selector 34 via the selector 35.

The carry save type adder 27 performs the next addition using the input sum component, carry component, and root multiple, and stores the resulting sum component and carry component in the registers 28 and 29. , Selector 2
The data is input to the carry save type adder 27 through 5 and 26.

The quotient selection circuit 30 includes a carry save type adder 27
The next quotient is predicted by the sum component and the carry component of
6. The above value is stored in the corresponding bit of the register 37. The positive and negative components of the quotient written in the registers 36 and 37 are input to the route multiple generation circuit 38.

The route multiple generation circuit 38 generates an intermediate result from the input positive and negative components of these quotients,
The route multiple is obtained from the intermediate result, and is input to the selector 34 via the selector 35. Thereafter, the carry save type adder 27 performs the following square root operation.

When such a square root operation is performed cyclically and a quotient of a predetermined number of digits is obtained, the operation of the carry save type adder 27 is terminated, and the final quotient is stored in the registers 36 and 37. The positive and negative components of are stored in redundant binary format.

The carry propagation adder 39 subtracts the negative component of the redundant binary quotient from the positive component of the redundant binary quotient to obtain a non-redundant binary quotient.

The normalizing circuit 40 normalizes the quotient in the non-redundant binary format. Since the normalized quotient is a mantissa part, the normalized quotient is combined with a separately calculated exponent part, stored in the output register 41, and output as a result of the sqrt (y / x) calculation.

According to the present embodiment, the positive and negative components of the quotient in the redundant binary format, which are the results of the division performed in advance, are converted to the non-redundant binary format and are not normalized. By immediately starting the next square root operation as input data of the carry-save-type adder 27 in the form of the hexadecimal form, it saves time for converting the preceding division result to the non-redundant binary form and normalizing it. Since the square root operation can be started earlier by this amount, the division / square root operation for obtaining sqrt (y / x) can be speeded up.

[0105]

As described above in detail, according to the division / square root arithmetic unit of the present invention, the previously performed division result is directly input to the carry-save-save adder in the redundant binary format. By performing the next square root calculation, the start of the next square root calculation can be accelerated, and the entire calculation time can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a division / square root operation device of the present invention.

FIG. 2 is a block diagram showing a configuration example of a conventional division / square root operation device.

[Explanation of symbols]

21, 28, 29, 31, 36, 37, 41, 43-4
7 Registers 22, 25, 26, 34, 35 Selector 23, 24 Aligner 27 Carry-Save Type Adder 30 Quotient Selector 32 Shift Amount Detector 33, 42 Inverter 38 Route Multiple Generation Circuit 39 Carry Propagation Type Adder 40 Normal Conversion circuit

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Nobuhiro Ide 1 Tokoba, Komukai Toshiba-cho, Saisaki-ku, Kawasaki-shi, Kanagawa F-term (Reference) 5B016 AA01 BA07 CA01 CB04 CD01 EA13 FA05

Claims (5)

[Claims] An arithmetic unit for calculating a partial remainder for performing a floating-point division and a floating-point square root operation, and stores a quotient and a square root obtained by the division and the square root operation in a signed redundant binary format. In the division / square root arithmetic device, the division is performed in advance using the divisor and the dividend input from the outside, and the positive part and the same negative component of the resulting quotient stored in the signed redundant binary format are obtained. A division / square root arithmetic device which immediately starts the next square root operation as input data of the partial remainder arithmetic means. 2. An inverted part obtained by inverting a positive component of a quotient and a negative component of the same quotient stored in a signed redundant binary format, which is the result of the division, is converted into an exponent part of the result of the division, the input divisor, and the After shifting by the shift amount obtained from the input dividend, the quotient and the carry data to the lowest order are input to the partial remainder calculating means, so that the result of subtracting the negative component from the positive component of the quotient is squared. 2. The division / square root operation device according to claim 1, wherein the operation is performed. 3. The division / square root operation device according to claim 1, wherein a carry-save type adder is used as said partial remainder operation means. 4. The division / square root operation device according to claim 1, wherein a redundant binary adder is used as said partial remainder operation means. 5. The division / square root device according to claim 1, wherein the dividend is one.