JP3460780B2 - Numerical arithmetic unit - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a BCD (Bina).
RY Coded Decimal) The present invention relates to a numerical operation device using coded data, and more particularly to a numerical operation device employed in a graphic scientific calculator or the like.

[0002]

2. Description of the Related Art FIG. 8 shows an example of BCD coded data. The data to be calculated is composed of an exponent part 100 and a mantissa part 101. In the illustrated example, the mantissa part 101 has 10 digits and the exponent part 100 has 2 digits. Each digit of the mantissa part 101 is represented by a BCD code, and the decimal point position is between the second digit and the third digit from the higher digit. In the normalized mantissa part 101, the most significant digit is a decimal number 0, 2
The digit is a decimal number other than 0. In the example shown in the figure, it is represented by 1.234456789 × (10 to the third power).

That is, the mantissa part 101 fixes the decimal point position and holds data for the number of significant digits, and the exponent part 100 represents the actual decimal point position. Therefore, in order to add / subtract two data in such a format, it is necessary to match the decimal point position, and the mantissa part 101 needs to be shifted in units of digits, that is, in units of 4 bits. Further, at the time of calculation, it is necessary to calculate one digit at a time, taking into account carry from the lower digit.

In general, the number of digits in the mantissa 101 is a factor that determines the accuracy of the calculation, and therefore the number of digits is considerably larger than the number of digits in the exponent 100. Therefore, it takes a lot of time to perform these processes by a calculation means such as a CPU.

Under these circumstances, recently, a dedicated device for calculating the mantissa has been devised and used for the purpose of improving the calculation speed.

As a conventional example of a numerical operation device (hereinafter referred to as a BCD operation device) for performing this kind of BCD operation,
For example, there is one disclosed in Japanese Patent Laid-Open No. 4-316128. FIG. 9 shows this BCD arithmetic unit. This BCD
The mantissa part of the arithmetic unit has 10 digits. Operation target 2
Let the mantissa parts of the two data be A and B, respectively, and let X be the storage means for storing A for each digit, and X0,
Let Y be the storage means for storing X1 ... X9, B for each digit, and Y0, Y1 ... Y9 in order from the lowest digit. X0
.. to X9 and Y0 to Y9 are connected to adjacent digits, respectively, and can be shifted in digit units.

Data is input by data input / output control means (neither shown) connected to an external data bus. Also, a BCD for calculating the values of the storage means X and Y
Arithmetic means is provided for each digit, which are designated as W0, W1, ... W9 in order from the least significant digit. Then, the storage means for storing the calculation result of each of the BCD calculation means W9 to W0 is set to Z, and Z0, Z1 ... Z9 in order from the least significant digit. Z0 to Z9 are connected to adjacent digits, respectively, and can be shifted in digit units. The carry generated by the calculation in the BCD calculation means W0 to W8 is input to W1 to W9, respectively.

The procedure for performing calculations using this BCD arithmetic unit will be described below. Now, as an example, 998
Consider the case of trying to calculate 7.654 + 23.456789.

9987654 = 9.987654 ×
(10 to the third power) 23.456789 = 2.3456789 × (1 of 10)
Therefore, inputting the respective mantissa parts to the storage means X and Y results in X = 0998765400 Y = 02334567890.

Next, in order to make the values of both exponents uniform, the data of the mantissa having the smaller exponent is downshifted.
In the case of this example, the values of the exponent part are aligned by shifting down Y by two digits. Then, X = 00998765400 Y = 0002345678, so when the calculation is executed, Z = X + Y = 1001111078. Since the most significant digit of the normalized mantissa must be 0 in decimal and the second digit must be a decimal number other than 0, Z is normalized by shifting down by one digit. I do. Then, Z = 01001111107. At this time, the value of the exponent part is 4. The X, Y, and Z data are output to the external data bus by the data input / output control device.

Next, an example of subtraction will be shown. Now, as an example,
Consider the case of calculating 3333.33-3332.33. At this time, when the respective mantissa parts are input to the storage means X and Y, X = 03333333000 Y = 03332333000. At this time, since the values of the exponent parts are both 3, there is no need to shift, so that if the calculation is executed as it is, Z = XY = 0000100000. To normalize this, Z needs to be shifted up by three digits. When the normalization is executed, Z = 0100000000 and the value of the exponent part becomes 0.

[0012]

However, the BCD arithmetic unit disclosed in Japanese Patent Laid-Open No. 4-316128 has the following problems. That is, since this BCD arithmetic unit attempts to speed up the arithmetic by preparing all the digits at the same time by preparing the BCD arithmetic means for each digit, first of all, the circuit scale is Since it is large and complicated, the cost of the BCD arithmetic unit increases.

Secondly, since the calculation result of the BCD calculating means of each digit is not determined until the carry from the lower digit is decided, in order to perform the 2-digit calculation, the calculation time of the 1-digit BCD calculating means is 2 times. Since the calculation time increases in proportion to the number of digits to be calculated, that is, three times as long as the calculation time of the one-digit BCD calculation means in order to perform the calculation of three times and three digits. Even if the BCD calculation is performed, the speedup cannot be expected so much.

The present invention has been made in view of the above circumstances, and has a system configuration with a small circuit scale, and a numerical operation device using BCD coded data capable of speeding up the operation time. The purpose is to provide.

Another object of the present invention is to provide a numerical operation device which enables a significant cost reduction.

[0016]

According to the numerical operation device of the present invention, a first digit is shifted to the right by one digit in synchronization with a predetermined first right shift clock, and the corresponding digit values represent the BCD code. Storage means, a second storage means that shifts to the right by one digit in synchronization with a predetermined second right shift clock, each corresponding digit value representing a BCD code, and a predetermined third right. The value of the corresponding digit shifts to the right by one digit in synchronization with the shift clock and shifts by one digit to the left in synchronization with the predetermined left shift clock.
Third storage means representing a code, data input / output control means connected to an external data bus, a one-digit BCD code input from the data input / output control means, the lowest of the first storage means 1 selected from the digit BCD code or the value of 0 and inputting the selected signal to the most significant digit of the first storage means, and 1 input from the data input / output control means Second selection for selecting either the digit BCD code, the least significant digit BCD code of the second storage means or a value of 0 and inputting the selected signal to the most significant digit of the second storage means Means, a carry storage means for storing a carry generated by the previous calculation, a BCD code represented by the least significant digit of the first storage means, and a least significant digit of the second storage means. The BCD code and the value of the carry storage means are determined in advance. BCD operation is performed in synchronism with the operation clock, and the carry generated by the operation is stored in the carry storage means, and either the operation result of the BCD operation means or the value of 0 is selected and selected. The input signal to the most significant digit of the third storage means
Selecting means for generating the first right shift clock, the second right shift clock, the third right shift clock, the left shift clock, and the operation clock, and the first selecting means, The data input / output control unit includes a second selection unit and an arithmetic control unit for controlling the third selection unit, and the data input / output control unit selects data to be input to the first selection unit and the second selection unit. Together with the first storage means,
It is configured to select the data stored in the second storage means and the third storage means and output the data to the data bus, whereby the above object is achieved.

Preferably, the third storage means does not have a function of shifting to the left by one digit, and the third selection means stores the calculation result of the BCD calculation means and the maximum value of the third storage means. Either the BCD code represented by the lower digit or the value of 0 is selected, and the selected signal is input to the most significant digit of the third storage means.

In the numerical operation device of the present invention, the first digit shifts to the right by one digit in synchronization with the predetermined first right shift clock, and the corresponding digit values represent the BCD code.
And a storage means for shifting a digit to the right by synchronizing with a predetermined second right shift clock and inputting a value of 0 to the least significant digit by synchronizing with a predetermined left shift clock and shifting the digit by one digit to the left. Shift to, and the value of the corresponding digit is B
Second storage means representing a CD code, data input / output control means connected to an external data bus, a one-digit BCD code input from the data input / output control means, and the first storage means, respectively. One-digit BCD represented by the least significant digit of
First selecting means for selecting either a code or a value of 0 and inputting the selected signal to the most significant digit of the first storing means, and a carry storage for storing a carry generated by the previous calculation. Means, the BCD code represented by the least significant digit of the first storage means, the BCD code represented by the least significant digit of the second storage means, and the value of the carry storage means, by a predetermined operation. A BCD calculation means for performing a BCD calculation in synchronization with a clock and for storing a carry generated by the calculation in the carry storage means, a one-digit BCD code input from the data input / output control means, and the BCD calculation means. Of the calculation result or the value of 0, and second selecting means for inputting the selected signal to the most significant digit of the second storing means, the first right shift clock, and the second Right shift clock, left shift clock And a calculation control unit that generates the calculation clock and controls the first selection unit and the second selection unit, and the data input / output control unit includes the first selection unit and the first selection unit. In addition to selecting the data to be input to the second selecting means, the data stored in the first storing means and the second storing means are selected and output to the data bus. The above object is achieved.

Preferably, the second storage means does not have a function of shifting to the left by one digit, and the second selection means is a one-digit B input from the data input / output control means.
A CD code, a calculation result of the BCD calculation means, a BCD code represented by the least significant digit of the second storage means or a value of 0 is selected, and the selected signal is stored in the second storage means. It is configured to input in the upper digit.

The operation of the present invention will be described below.

According to the system configuration and the operation contents described above, the calculation can be performed by the BCD computing means repeatedly performing the digit-by-digit operation.
Unlike the BCD calculation device disclosed in Japanese Patent No. 6128, it is not necessary to provide a BCD calculation means for each digit.

Further, according to the present invention, the time required to calculate all digits can be one cycle time of the operation clock, which is the time required for one-digit BCD operation. BCD disclosed in Japanese Patent No. 316128
Almost no different from a computing device.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be specifically described below with reference to the drawings.

(Embodiment 1) FIGS. 1 to 4 show Embodiment 1 of the numerical value arithmetic device according to the present invention. First, the system configuration of the numerical calculation device (BCD calculation device) of Embodiment 1 will be described with reference to FIG. This numerical operation device includes a first storage unit 1, a second storage unit 2, a BCD calculation unit 3, a first selection unit 4, a second selection unit 5, a third storage unit 6, and a third selection unit. A means 7, a data input / output control means 8 and an arithmetic control means 9 are provided, which are a bus (data bus) 18
Connected by ~ 28. The configuration and function of each unit will be described below.

The first storage means 1 is configured by arranging four sets of shift registers having the same number of digits as the number of digits that can be right-shifted, that is, downshifted. Similarly, the second storage means 2 is also configured by arranging four sets of shift registers having the same number of digits as the number of operation digits that can be shifted down. On the other hand, the third storage means 6 has four shift registers capable of left-right shift, that is, both up-shift and down-shift.
They are arranged in pairs.

The BCD calculation means 3 calculates the value of the least significant digit of the first storage means 1 and the value of the least significant digit of the second storage means 2. The first selection means 4 selects the data to be input to the most significant digit when the first storage means 1 shifts to the right. The second selection means 5 selects the data to be input to the most significant digit when the second storage means 2 shifts to the right. The third selection means 7 selects the data to be input to the most significant digit when the third storage means 6 shifts to the right.

The data input / output control means 8 controls the exchange of data with an external data bus (not shown). The arithmetic control unit 9 also generates a signal for controlling the shift operation of the first storage unit 1, the second storage unit 2, and the third storage unit 6, and the BCD calculation unit 3 and the first selection unit. 4, controlling the second selecting means 5 and the third selecting means 6.

More specifically, the shift operation of the first storage means 1 to the right by one digit is performed by the first right shift clock 10 provided from the arithmetic control means 9. Similarly,
The shift operation to the right by one digit in the second storage unit 2 is performed by the second right shift clock 11. Further, the BCD calculation means 3 is controlled by the calculation clock 12 given from the calculation control means 9.

The selection operation of the first selection means 4 is controlled by the first selection signal 13 provided from the arithmetic control means 9. Similarly, the selection operation of the second selection means 5 is controlled by the second selection signal 14.

The shift operation to the right by one digit in the third storage means 6 is performed by the third right shift clock 15, and the shift operation to the left by one digit is performed by the left shift clock 16. The selection operation of the third selection means 7 is performed by the third selection signal 17 provided from the arithmetic control means 9.

The bus 18 is a bus for outputting the values of all digits of the first storage means 1 to the data input / output control means 8. Further, the bus 19 outputs the values of all the digits of the second storage means 2 to the data input / output control means 8, and the bus 20 outputs the values of all the digits of the third storage means 6 to the data input / output control means. 8, a bus 21 is a 4-bit bus for transmitting the value of the least significant digit of the first storage means 1, and a bus 22 is a second bus.
A 4-bit bus for transmitting the value of the least significant digit of the memory means 2, a bus 23 for a 4-bit bus for transmitting the value of the operation result of the BCD operation means 3, and a bus 24 for the output of the first selecting means 4. A 4-bit bus for transmission, a bus 25 is a 4-bit bus for transmitting the output of the second selection means 5, a bus 26 is a 4-bit bus for transmitting the output of the third selection means 7, and a bus 27 is data. A 4-bit bus for transmitting BCD data from the input / output control means 8 to the first selection means 4, a bus 28 is a BC from the data input / output control means 8 to the second selection means 5.
It is a 4-bit bus for transmitting D data.

Next, the operation of the numerical operation device of this embodiment will be described by taking the case where the mantissa part is composed of 10 digits as an example. Now, let us say that two data to be operated are data A: mantissa part = 0987654321, exponent part 3 data B: mantissa part = 0123456789, exponent part 5. The decimal point position of the mantissa is between the second and third digits from the higher order.

In the present invention, the calculation of the exponent part has little relation to the essence of the present invention, so it will be briefly described. For comparison of the values of the exponent part, the CP outside the numerical operation device of the present invention is used.
The data is input by writing data to the data input / output control means 8 from an external CPU or the like, and the numerical value of the present invention is given by giving an instruction to the arithmetic control means 9 from the external CPU or the like. It is assumed that the calculation of the calculation device is performed.

First, the procedure for inputting the data to be calculated into the first storage means 1 and the second storage means 2 will be described. Upon receiving the first selection signal 13 under the control of the arithmetic control means 9, the first selection means 4 selects the data input from the data input / output control means 8. The data input / output control means 8 outputs the value "1" of the least significant digit of the mantissa part of the data A to the first selection means 4, and the arithmetic control means 9 makes the first value.
The right shift clock 10 is generated by one shift.
Then, "1" is input to the most significant digit of the first storage means 1.

Next, the data input / output control means 8 outputs the value "2" in the second lowest digit of the data A to the first selection means 4, and the arithmetic control means 9 causes the first right shift clock. 10 is generated for one shift. Then, the value of the most significant digit of the first storage means 1 becomes "2", and the value of the second digit from the high order of the first storage means 1 becomes "1".
Similarly, the value of the mantissa part of the data A is stored in the first storage means 1 by repeating this input operation digit by digit by the number of calculated digits.

Similarly, under the control of the arithmetic control means 9, the second selecting means 5 selects the data from the data input / output control means 8. The data input / output control means 8 outputs the value "9" of the least significant digit of the data B to the second selection means 5, and the operation control means 9 causes the second right shift clock 1 to operate.
1 is generated for one shift. Then, the value "9" of the least significant digit of the data B is input to the most significant digit of the second storage means 2.

Next, the data input / output control means 8 outputs the second lowest digit value "8" of the data B to the second selection means 5, and the arithmetic control means 9 causes the second right shift clock. 11 is generated for one shift. Then, the value of the most significant digit of the second storage means 2 becomes "8", and the value of the second digit from the higher order of the second storage means 2 becomes "9".
By repeating the same operation for the number of calculation digits, the data to be calculated is stored in the second storage means 2. First at this time
The states of the storage means 1 and the second storage means 2 of FIG.
It becomes like FIG.

Next, a procedure for aligning the digits in the first storage means 1 and the second storage means 2 will be described. If the exponent values are not the same, digit alignment must be performed before the operation. In the example of the first embodiment, it is necessary to shift the value of the first storage unit 1 to the right by two digits and adjust the value of the exponent part to 5 digits. The first selection means 4 selects the value "0", and the operation control means 9 selects the first right shift clock 10
Is generated for 2 shifts. By doing so, the value of the first storage means 1 is shifted to the right by two digits. The states of the first storage means 1 and the second storage means 2 at this time are shown in FIG.
It becomes like (b). Similarly, when the value of the second storage means 2 is right-shifted, the second selection means 5 is "
The value "0" is selected, and the arithmetic control means 9 generates the second right shift clock 11 by the number of digits to be shifted.

Finally, the procedure for calculating the first storage means 1 and the second storage means 2 will be described. Here, the case of addition will be described as an example. The same applies when subtraction is performed.

First, the details of the BCD calculation means 3 will be described. As shown in FIG. 3, the BCD calculation means 3 is a BCD addition / subtraction means 30 for adding / subtracting one-digit BCD codes.
And a carry storage means 31 for storing a carry generated by the calculation of the BCD addition / subtraction means 30.
The BCD addition / subtraction means 30 adds / subtracts the two input BCD codes together with the carry signal from the carry storage means 31, outputs the operation result, and stores the carry signal generated during the operation in the carry storage means 31. Output.

The carry storage means 31 is the arithmetic control means 9
The current value is held until the operation clock 12 is output. Then, the arithmetic control means 9 to the arithmetic clock 12
Is output, the BCD adding / subtracting means 30 is synchronized with it.
The carry signal from is stored.

Next, the calculation procedure will be described. Under the control of the arithmetic control unit 9, the first selection unit 4 receives the first selection signal 13 and selects the value “3” of the least significant digit of the first storage unit 1. The second selection means 5 receives the second selection signal 14, and receives the value of the least significant digit of the second storage means 2.
9 "is selected. The third selection means 7 outputs the third selection signal 1
In response to 7, the value of the calculation result of the BCD calculation means 3 is selected. At this time, the BCD calculation means 3 has the value of the least significant digit “3” of the first storage means 1 and the value of the least significant digit of the second storage means 2.
9 "is BCD added with the carry signal" 0 "of the carry storage means 31, the addition result" 2 "is output to the third selecting means 7, and the carry signal" 1 "is carried to the carry storage means 31. At this time, since the carry storage means 31 does not receive the operation clock 12, the initial value "
It remains 0 ”.

In this state, the arithmetic control means 9 has the first right shift clock 10, the second right shift clock 11, and the third right shift clock 10.
The right shift clock 15 and the operation clock 12 are simultaneously output. Then, the first storage means 1 and the second storage means 2 are shifted to the right by one digit, the addition result “2” is input to the most significant digit of the third storage means 6, and the carry storage means 31 is entered. The previous carry value "1" is input.

The states of the first storage means 1, the second storage means and the third storage means 6 at this time are shown in FIG.
It becomes like (a). At this time, the BCD calculation means 3 sets the value "4" of the least significant digit of the first storage means 1 and the value "8" of the least significant digit of the second storage means 2 to the carry signal of the carry storage means 31. BCD addition with "1" and the addition result "
3 "is output to the third selecting means 7, and the carry signal" 1 "is output to the carry storing means 31.

In this state, the arithmetic control means 9 outputs the first right shift clock 10, the second right shift clock 11, the third right shift clock 15 and the arithmetic clock 12 at the same time as in the first digit. . Then, like the first digit, the first storage means 1 and the second storage means 2 shift right by one digit,
The addition result "3" is input to the most significant digit of the third storage means 6 and the carry storage means 31 shifts to the right by one digit.
The previous carry value "1" is input to.

The states of the first storage means 1, the second storage means and the third storage means 6 at this time are shown in FIG.
It becomes like (b). Then, when the above operation is executed for 10 digits, the result is as shown in FIG. As can be seen from this figure, the values of the first storage means 1 and the second storage means 2 are stored, and the calculation results are stored in the third storage means 6.

In the first embodiment, since the operation result stored in the third storage means 6 is in the same state as that in the normalized state, it can be used for other operations as it is. For example, the third storage means 6 is used. If the value of the most significant digit is other than "0" such as 1234567890, it is necessary to shift the value to the right by one digit for normalization. At that time, the value of the exponent part must be incremented by 1. On the other hand, when the value of the third storage means when the subtraction is performed is such that the value of the upper two digits is 0 as in the case of 0000123456, it is necessary to shift to the left to normalize. In this example, it is normalized by shifting left by 3 digits. Then the value of the exponent must be reduced by 3.

According to the numerical operation device of the first embodiment, B
The calculation can be performed by the CD computing means 3 repeatedly performing digit-by-digit calculations.
Unlike the BCD calculation device disclosed in Japanese Patent No. 16128, it is not necessary to provide a BCD calculation means for each digit.

As for the time required to calculate all the digits, the time required for 1-digit BCD calculation is 1 of the operation clock.
Since it is possible to set the cycle time, it is possible to use
It is almost the same as the BCD arithmetic device disclosed in Japanese Patent No. 316128.

(Embodiment 2) FIG. 5 shows Embodiment 2 of the numerical operation device of the invention. The numerical operation device according to the second embodiment is
The numerical calculation device of the first embodiment is different in the following points. That is, as is apparent from a comparison between FIG. 5 and FIG. 1, in the numerical calculation device according to the second embodiment, the third storage unit 6 does not have the function of shifting to the left (from the calculation control unit 9 to the left. (The shift clock 16 is not given), and not only the output of the BCD calculation means 3 and the value of "0" but also the value 29 of the least significant digit of the third storage means 6 is input to the third selection means 7. There are points. The parts corresponding to those of the first embodiment are designated by the same reference numerals, and the detailed description will be omitted.

As described above, in the numerical operation device according to the second embodiment, since the third storage means 6 does not have the function of shifting to the left, it is necessary to shift to the left when performing the normalization after the subtraction. To do this, do the following: For example, 0000
In the case of shifting 123456 to the left by three digits, first, the third selecting means 7 receives the third selecting signal 17 under the control of the arithmetic control means 9, and the value of the least significant digit of the third storing means 6 "
6 ". And the third right shift clock 15
In response to this, the third storage means 6 shifts to the right by one digit.

Then, the value of the third storage means 6 is 6000.
It becomes 012345. When this is repeated for (10-3) digits, that is, for 7 digits, the value of the third storage means 6 is 01234.
It becomes 56000, which is the same result as shifting by 3 digits to the left. The operations other than the left shift of the third storage means 6 are all the same as in the first embodiment.

With such a configuration, it is possible to deal with the case where the shift register having the function of shifting to the left cannot be used or the circuit scale is reduced. That is, according to the second embodiment, with a simpler system configuration,
There is an advantage that a numerical operation device capable of high-speed operation can be realized.

(Embodiment 3) FIG. 6 shows Embodiment 3 of the numerical value arithmetic device of the present invention. The numerical operation device according to the third embodiment is
The numerical calculation device of the first embodiment is different in the following points. That is, as is clear from a comparison between FIG. 6 and FIG. 1, the numerical operation device of the third embodiment does not include the third selecting means 7 and the third storing means 6, and That the second storage means 2 of the second selection means 5 has the function of shifting to the left by receiving the left shift clock 16.
The point is to input the calculation result of the BCD calculation means 3 instead of the least significant digit. The parts corresponding to those of the first embodiment are designated by the same reference numerals, and the detailed description will be omitted.

In the second embodiment, when the calculation is performed,
The second selection means 5 selects the calculation result of the BCD calculation means 3. By doing so, after the calculation is performed, the calculation result is stored instead of the data stored in the second storage unit 2 before the calculation. When it is not necessary to save the data stored in the second storage means 2, the circuit scale can be reduced as compared with the first embodiment by adopting such a configuration. That is, the third embodiment also has an advantage that a numerical operation device capable of high-speed operation can be realized with a simpler system configuration.

(Fourth Embodiment) FIG. 7 shows a fourth embodiment of the numerical operation device of the present invention. The numerical operation device according to the fourth embodiment is
It differs from the numerical operation device of the third embodiment in the following points. That is, as apparent from a comparison between FIG. 7 and FIG. 6, in the numerical operation device according to the fourth embodiment, the second storage unit 2 does not have the function of shifting to the left, and the second selection. One digit B input to the means 5 from the data input / output control means 9
The point is that not only the CD code, the output of the BCD calculation means 3 and the value of "0" but also the value of the least significant digit of the second storage means 2 is input. The parts corresponding to those in the third embodiment are designated by the same reference numerals, and the detailed description will be omitted.

In the numerical operation device according to the fourth embodiment, the second storage means 2 does not have the function of shifting to the left. Therefore, when performing the normalization after the subtraction, as in the second embodiment, the operation control means 9 operates. Under the control, the second selection means 5 receives the second selection signal 14 to select the value of the least significant digit of the second storage means 2 and receives the second right shift clock 12 to receive the second Storage means 2 shifts by (the number of calculated digits-the number of left shifts).

The fourth embodiment also has an advantage that a numerical arithmetic unit capable of high-speed arithmetic can be realized with a simpler system configuration.

[0059]

In the numerical operation device of the present invention, since the BCD operation means can perform the operation by performing the iterative operation for each digit, the BCD operation device disclosed in Japanese Patent Laid-Open No. 4-316128 is disclosed. Is different, BCD for each digit
There is no need to provide a calculation means. Therefore, according to the present invention, there is an advantage that it can be realized with a simple system configuration having a small circuit scale.

Further, in the numerical operation device of the present invention, the time required to calculate all the digits can be the time required for one-digit BCD operation to be one cycle time of the operation clock. It is almost the same as the BCD arithmetic unit disclosed in Japanese Patent Laid-Open No. 4-316128.

Therefore, according to the present invention, it is possible to achieve an effect that it is possible to realize a BCD arithmetic unit capable of speeding up an arithmetic time with a system configuration having a small circuit scale.

Further, in particular, according to the numerical operation device described in claims 2 to 4, there is an advantage that a numerical operation device capable of high-speed operation can be realized with a more simple system configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing a system configuration showing a first embodiment of a numerical operation device of the present invention.

FIG. 2 shows Embodiment 1 of the numerical operation device of the present invention,
(A), (b) is explanatory drawing for demonstrating a digit alignment operation.

FIG. 3 is a BC diagram showing the first embodiment of the numerical operation device of the present invention.
The block diagram which shows the detail of D calculating means.

FIG. 4 shows the first embodiment of the numerical operation device of the present invention,
(A)-(c) is explanatory drawing for demonstrating arithmetic operation.

FIG. 5 is a block diagram showing a system configuration showing a second embodiment of the numerical calculation device of the present invention.

FIG. 6 is a block diagram showing a system configuration showing a third embodiment of a numerical operation device of the present invention.

FIG. 7 is a block diagram showing a system configuration showing a fourth embodiment of the numerical calculation device of the invention.

FIG. 8 is a diagram showing an example of BCD-coded data.

FIG. 9 is a block diagram showing a system configuration showing a conventional example of a numerical operation device.

[Explanation of symbols]

1 First storage means 2 Second storage means 3 BCD calculation means 30 BCD addition / subtraction means 31 Carry memory 4 First selection means 5 Second selection means 6 Third storage means 7 Third selection means 8 Data input / output control means 9 Arithmetic control means 10 First right shift clock 11 Second right shift clock 12 Arithmetic clock 15 Third right shift clock 16 Left shift clock 18-28 bus

Claims (4)

(57) [Claims] 1. A first storage means for shifting a digit to the right by one digit in synchronization with a predetermined first right shift clock, each storing digit representing a BCD code, and a predetermined second right. Shifting to the right by one digit in synchronization with the shift clock, second storage means in which the corresponding digit values represent the BCD code, and shifting to the right by one digit in synchronization with a predetermined third right shift clock , And shift to the left by one digit in synchronization with a predetermined left shift clock.
A third storage means representing the D code, a data input / output control means connected to an external data bus, a one-digit BCD code input from the data input / output control means, and a maximum of the first storage means. It is input from the data input / output control means and first selection means for selecting either the BCD code of the lower digit or the value of 0 and inputting the selected signal to the most significant digit of the first storage means. A second digit which selects either the one-digit BCD code, the least significant digit BCD code of the second storage means or a value of 0 and inputs the selected signal to the most significant digit of the second storage means. A selection means, a carry storage means for storing a carry generated by the previous calculation, and a BCD code represented by the least significant digit of the first storage means,
The BCD code represented by the least significant digit of the second storage means and the value of the carry storage means are BCD operated in synchronization with a predetermined operation clock, and the carry generated by the operation is carried up. BCD calculation means to be stored in the storage means, and third selection means for selecting either the calculation result of the BCD calculation means or the value of 0 and inputting the selected signal to the most significant digit of the third storage means. Generating the first right shift clock, the second right shift clock, the third right shift clock, the left shift clock and the operation clock, and the first selecting means and the second selecting clock. The data input / output control means selects data to be input to the first selection means and the second selection means, and an arithmetic control means for controlling the selection means and the third selection means. First memorizer Math unit to the Detabasuhe selects and outputs the data to the second storage means and third storage means is storing. 2. The third storage means does not have the function of shifting to the left by one digit, and the third selection means is the B
As the calculation result of the CD calculating means, either the BCD code represented by the least significant digit of the third storing means or the value of 0 is selected, and the selected signal is input to the most significant digit of the third storing means. The numerical operation device according to claim 1. 3. A first storage means for shifting a digit to the right by one digit in synchronization with a predetermined first right shift clock, each corresponding digit value representing a BCD code, and a predetermined second right. The value shifts to the right by one digit in synchronization with the shift clock, and the value of 0 is input to the least significant digit and shifts to the left by one digit in synchronization with the predetermined left shift clock. Second storage means for representing a code, data input / output control means connected to an external data bus, a one-digit BCD code input from the data input / output control means, and each of the first storage means First selecting means for selecting either one digit BCD code represented by the least significant digit or a value of 0 and inputting the selected signal to the most significant digit of the first storing means; Remember carry caused by And up storage unit, BCD code represented by the least significant digit of the first storage means,
The BCD code represented by the least significant digit of the second storage means and the value of the carry storage means are BCD operated in synchronization with a predetermined operation clock, and the carry generated by the operation is carried up. The BCD calculation means to be stored in the storage means, the one-digit BCD code input from the data input / output control means, the calculation result of the BCD calculation means, or the value of 0 are selected, and the selected signal is set to the first signal. Second selection means for inputting to the most significant digit of the second storage means, the first right shift clock, the second right shift clock, the left shift clock and the operation clock, and the first selection means. And a calculation control means for controlling the second selection means, the data input / output control means selects data to be input to the first selection means and the second selection means, and The Numerical calculation unit for the Detabasuhe outputs first storage means and second storage means selects the stored data. 4. The second storage means does not have a function of shifting to the left by one digit, and the second selection means is a one-digit BCD code input from the data input / output control means. The calculation result of the BCD calculation means is selected, either the BCD code represented by the least significant digit of the second storage means or the value of 0, and the selected signal is input to the most significant digit of the second storage means. The numerical operation device according to claim 3.