JPS62214435A - Digital dividing circuit - Google Patents

Abstract

PURPOSE:To perform digital division with a simple hardware constitution by giving error data based on a divisor to perform the division of an optional divider with only bit operation, multiplication, and addition. CONSTITUTION:x-bit registers 1a, 1b, 1c... are connected selectively to an x-bit X register 3 by switches 2a, 2b, 2c.... y-bit registers 4a, 4b, 4c... are connected selectively to a y-bit Y register 6 by switches 5a, 5b, 5c.... Outputs of the X register 3 and the Y register 6 are inputted to a multiplier 7 of a z-bit output. The output of the multiplier 7 is given to one input of an adder 10, and the output of a z-bit Z register 9 is given to the other input. All z-number of bits of the output of the adder 10 are fed back to the Z register 9, and upper x- number of bits and y-number of bits are fed back to registers 1a and 4a respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to h) a highly versatile digital division circuit having a single circuit configuration and capable of performing division with respect to any divisor;

[Technical background of the invention and its problems] Generally, in a system that applies a microcomputer,
・When performing division like -, the divisor is 2k (k=1.2
．． 3. ), division can be performed extremely easily by shifting the dividend data to the right by . However, if the divisor cannot be expressed as an integer power of 2. The process is extremely complex. With the conventional method of using dedicated division hardware that has functions for bit shifting and addition of dividend data, in order to handle various divisors, it is necessary to prepare an extremely large amount of hardware for each divisor. I don't get it.

On the other hand, by using a ROM dedicated to division, etc., this RO
A method of using a division table stored in M has also been adopted, but in this method as well, the answer must be registered for each set of dividend and divisor, and the answer for each set of dividend and divisor must be registered. cannot be divided. Therefore, in order to perform division n for various divisors and dividends, there is a problem in that the scale of the circuit inevitably increases.

[Objective of the Invention] The present invention was made based on the above problem, and provides a highly flexible digital division circuit that can perform division on five-color divisors and dividends without complicating the hardware configuration. The purpose is to

[Summary of the invention] In the present invention, the dividend data Xi is an arbitrary divisor de1.

When dividing by a factor N (where N is an integer that satisfies 0≦≦1), first, a positive integer given together with the dividend data This multiplication result and x-1- are added together in an adder with appropriate decimal point positions, and the final value of R is obtained.

[Effects of the Invention] According to the present invention, by providing error data obtained based on the divisor N instead of the divisor N, it is possible to perform division of an arbitrary divisor N using only pit operations, multiplication, and addition. becomes. Therefore, digital division can be performed with an extremely simple hardware configuration like an existing product-sum circuit. In addition, since the minus number is converted into an integer, there is an effect that a small number of calculation pits can be used effectively.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

'FIG. 1 shows an example in which a sum-of-products calculation unit incorporated in a part of a digital computer system is used as a digital division circuit according to the present invention.

X-bit register 1 that constitutes the first register group *
#1 b, 1 c * ”' means switch 2 &
, 2b.

2a, . . . selectively select the X bits of the X register 3 by
connected to. On the other hand, the y-bit registers 4m, 4b, 4e, . . . forming the second register group are selectively connected to the y-pit Y register 6 by switches 5**5b, 5ce, . The outputs of the X register 3 and Y register 4 are given as two inputs to a multiplier 7 with a 2-bit output. The output of the multiplier 7 is sent to an adder 10 via a selector 8 that performs digit alignment by pit shifting.
is given as one input. The other input of the adder 10 is given the output of the 2-pit 2-register 9. Then, the output of the adder 10 is such that all two pits are 2
The configuration is such that the upper X and 7 bits are fed back to register 9 and to register Jam4m, respectively. In addition, in FIG. 1, X, 7. An example is shown in which Z is given as 15 and 15.30, respectively.

In this embodiment, division of an arbitrary dividend A-B by an arbitrary divisor N is performed using the sum-of-products calculation section configured as described above. The procedure for this division will be explained below with reference to FIGS. 2 and 3.

First, the dividends A and B, the divisor N, and the number of digits to be approximated, 8, are set outside the product-sum calculation section.

Given these calculation parameters, 1-1-2
Since the value of m (positive integer) that gives the minimum value of m greater than or equal to 0 is uniquely determined, the error data represented by is also determined. This error data may be calculated in another calculation section of the system, or N
, s may be stored in a ROM table with addresses as addresses. The above is the processing at the stage before starting the processing in the product-sum calculation section.

Next, the product-sum calculation unit inputs the number of digits to be approximated, 8 (step 21), and sets the decimal point tV to the third bit of the multiplier 7 (step 22). On the other hand, outside the product-sum calculation section, from m and 1, s=m+a-)-b...
A and b (positive integers, but not limited to one) that satisfy (2) are found. X multiplied by 21 in register a
Store the bit multiplicand A・21 and write 2 in register 4a.
The multiplier B·2tlt of the multiplied y bits is stored (step 23). By selecting the switches 2m and 5h, these data are set in the X register 3 and Y register 6, respectively, and multiplied by the multiplier 7, as shown in FIG. 3-') and (b). In this multiplication, as shown in (c),
It can be obtained as a 2-bit A-B-2"bt multiplication result, but as mentioned above, the output of the multiplier 7
Since the decimal point is fixed in the first step, the result obtained by the 1 multiplier 7 is automatically shifted to the right by 3 bits, and (d)
It is added to A.Contents as shown in . Now, assuming that O is stored in register 2 9 as shown in (e),
The 2-bit output A-B of the adder 7 is stored in the 2 register 9 as 7 as shown in (f) (step 25
).

9. The upper X bits of this value are stored in register a, and the upper y pits of this value are stored in register 4a (step 26). The value of the upper X bits is 2 as shown in ω).
The decimal point of the output of the bit adder 10 is d = z - a
- It is nothing but the integer part of the value shifted to the left by X bits. In other words, register 1a contains A-B-7-・2□-
8-D will be stored.

Next, the aforementioned error data is set in register 4bK. Here, this error r-time will be explained. From the definitions of 1 and 3, 1 is N as shown in (h)
If we assume that there is a decimal point in the top bit, then the 1st to (m-1) bits from the top are all 0, the mth bit is 1, and then (m+1) from the top.
) ~ (m+a) bit is either 0 or 1, (m
+s+1) bit and all subsequent bits are expressed as a binary number O. By the way, the 1 standing at the m-th bit from the top corresponds to the top when considering the position of the decimal point. Therefore, (1-up)
is zm N zmm
Since it is a number obtained by changing the number 1 of the pit to 0, it can be expressed as (1). Now, if we move the decimal point to the right from the top to the (m+a)th bit, <1 + 1> becomes an integer 2
m and becomes (1-±)・2m+11 (j). moreover,
0) and 2m, move the decimal point to the left K (z − a − )・2 Z+m-
X 2m is obtained (g). This value is determined at the preprocessing stage as described above. This value is stored in the register 4bK as error data (step 27). Furthermore, as is clear from No. 39), Hatake is y≧($-X)≧l
...It is necessary to fully satisfy the condition (3). Next, the switches 2a and 5bi are selected and stored in the register 1a (step 28). As a result, A-B・c 1-1-)・ than shown in − is obtained, but as mentioned above, N 2rn In this system, the decimal point is set at the S bit of the output of the multiplier 7. Therefore, the obtained result is automatically shifted to the right of the S pit and added as shown in 0), and by the calculation =h-B-H...(4), as shown in φ) , A-B-H are obtained (step 29). The above procedure completes the calculation of A''B'N in the product-sum calculation section of this system.

It goes without saying that if O is stored in the register 4b, the final result will be XY-earth.

In FIG. 4, N=60. x=15. y=15. z=30
, m=6 * m=8 , m=1 t b=1 The specific processing flow is shown in correspondence with FIG. 3.

In this example, the approximation is as follows: nh-Bf.

Previous #0.016667 -g (1+H (1+H) ) #o, o 16663 upper (1+ hC1+ 16 > ), ·, ±A-B = -! −A −B +4A·B(π(1+T)) 1±A−B The error due to this approximation is about 0.02%. To match this value directly with 64 A ” B, it is extremely difficult to match (
60-])" Shift to the left by 14 bits and convert it into an integer. That is, ■ (1 + 爾) = 0.00010001 - (1 + 工) x 28 = (劃-4) x 2 = 10001
...(6) Then, add πA to this integer value.
Multiply B and match. Thereafter, by shifting the obtained product to the right by 8 bits, upper A-B (U(1+L)) is obtained.

In the actual calculation, as mentioned above, Fig. 4 (g)
In order to cancel the shadow jl' shifted to the right by 7 bits, (60-64)×2 is stored in the register 4b as error data, as shown in FIG.

If the calculation is performed according to the above-mentioned procedure, the calculation for one person/B is possible.

For reference, error data for some divisors N are shown in the following table. Well, for all these N, m =
It is 6.

In this way, according to this embodiment, by changing the value of the error data variously, division by an arbitrary divisor N becomes possible through extremely simple processing such as bit shifting, multiplication, and addition. This has the advantage that the sum-of-products calculation section can be used as is.

Note that the present invention is not limited to the hardware configuration of the product-sum calculation unit as described above. For example, the minimum number of registers is sufficient. Further, although there is no patent that specifically features the selector 8 in the above-mentioned next side, the bit shift processing in the multiplier 7 may be performed by the selector 8.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a sum-of-products calculation section used as a digital division circuit according to an embodiment of the present invention, and FIG. 2 is a flowchart showing the flow of processing in the sum-of-products calculation section.
FIG. 3 is a diagram for explaining the contents of various registers in the same product-sum calculation section, and FIG. 8g4 is a diagram for explaining the contents of various registers in the same product-sum calculation section using all specific numerical values. 1 m, 1 b, 1 e, 4 m, 4
b, 4 e = - register, 2 m * 2 b
#2 C#5 a g 5 b * 5 c ・
...Switch, 3...X register, 6...Y register, 2...multiplier, 8...selector, 9...2 register, 10...adder. Applicant's representative Patent attorney Takehiko Suzue Figure 1

Claims (6)

[Claims] (1) In a digital division circuit that divides dividend data X by arbitrary divisor data N (where N is an integer satisfying 0<1/N≦1), the dividend data
Error data expressed as 1/(2^m))・2^c (where m is a positive integer that gives the minimum value of {1/N-1/(2^m)} greater than or equal to 0, and c is 0 or a positive integer) and bit-manipulate the dividend data X to obtain X・1/(2
^m) and X・1/(2
＾m) by the above error data, and the value obtained by this multiplier and the above-mentioned X・1/(2＾m) are added together with appropriate decimal point positions to obtain X/N.
What is claimed is: 1. A digital division circuit characterized by comprising: an adder for obtaining . (2) The dividend X is expressed as the product of A and B, and these A
2. The digital division circuit according to claim 1, wherein the digital divider circuit and B are individually stored. (3) The digital division circuit according to claim 1, wherein c is m+s (s is a positive integer determined by the number of significant digits of 1/N). (4) c is m+s+d (s is a positive integer determined by the number of significant digits of 1/N, d is the bit that is truncated when temporarily storing X・1/(2^m) to be multiplied with error data 2. The digital division circuit according to claim 1, wherein the digital division circuit is: (5) When the input bits of the multiplier are x and y, and the output bit is z, d is characterized in that z-s-x s satisfies y≧z-x≧s≧m. A digital division circuit according to claim 4. (6) The digital division circuit according to claim 1, wherein s is m+2.