KR100223738B1 - Floating arithmetic apparatus of processing division and square root with a data path - Google Patents

Abstract

The present invention relates to a floating computing device capable of economically constructing a circuit by allowing an adder and a data path to be shared so that square root and division can be separately calculated. The structure of the present invention is a Robertson algorithm table for division calculation. A PLA, a shifter for shifting the output signal of the adder by 2 bits, and outputting the register, a register for storing the shifter output signal and inputting the PLA to the PLA, and a quotient output 2 bits each time from the PLA. A positive register and a negative register, and a division controller configured to output a control signal for controlling the division operation, performing a division operation, and outputting a signal shifted by two bits according to a square root command signal, and the positive register. Depending on the signal input from A second input signal generator for outputting to the adder; a second input signal generator for judging a sign signal and outputting the two's complement of the dividend if positive, and outputting the dividend to an adder if negative; The input register is updated every clock by the code signal generated by the signal, and the square root controller for outputting a control signal for controlling the square root operation is characterized by performing a square root operation.

Description

Floating computing unit that can handle division and square root with one data path

The present invention relates to a floating computing device capable of processing division and square roots in one data path. In particular, the circuit can be economically constructed by allowing an adder and a data path to be shared so that square roots and division can be separately calculated. A floating computing device capable of processing division and square roots in one data path.

In the scientific specialty, numbers of very large or small sizes are often used that do not require precision of significant figures. For example, using the decimal system, astronomers must deal with large numbers greater than 10 ³⁰ and chemists must use small numbers less than 10 ^-30 . In addition, physicists need both the number of areas that astronomers and chemists need. Such extremely small or large numbers cannot be accurately calculated to the last digit, but it is often sufficient to calculate only any significant digits and obtain a result. For example, decimal numbers (2, 637, 485, 968, 463, 425, 463, 774, 856, 308, 291) are very large numbers. However, it is extremely rare for anyone to require this level of precision. If the decimal number has five significant digits, the decimal number may be represented as (2, 637, 500, 000,000,000,000,000,000,000,000). However, it is very foolish to express it as it is. This is because such a decimal number can be simply expressed as 2.6375 × 10 ³⁰ if it is represented using a floating point format, and it is very easy to recognize.

In general, a computer performs calculation using this floating point format. As described above, a binary operation of a floating point number performed by a computer is very simple. In the conventional computer, the floating computing device for floating calculations has a structure using separate data paths because the division and square roots are calculated separately.

Therefore, in the related art, each data path is required to calculate the division and the square root, which requires many hardware components, thereby increasing the chip size.

The present invention is to solve the problems of the prior art as described above, divide and square root into a single data path that can be economically configured circuit by adding the adder and the data path so that the square root and the division can be calculated separately An object of the present invention is to provide a floating computing device capable of processing.

1 is a circuit diagram of a floating computing device capable of processing division and square roots in one data path according to an embodiment of the present invention;

FIG. 2 is a Robertson diagram of a floating computing device capable of processing division and square roots in one data path in accordance with an embodiment of the present invention. FIG.

* Explanation of symbols on the main parts of the drawings

1: division controller 2: square root controller

3: PLA 4: input register

5: first input signal generator 6: adder

7, 10, 12: shifters 8, 9, 11: registers

13: sticky bit generator 14: second input signal generator

15: square root input generator

The present invention as a means for achieving the above object, the PLA is a table of Robertson algorithm for the division operation, a shifter for shifting the output signal of the adder by two bits, and the output signal of the shifter to store the PLA And a divider controller for outputting a control signal for controlling the divide operation, and a divider controller. A positive register for outputting a signal shifted by two bits according to the command signal, a second input signal generator for generating a signal according to the signal input from the positive register, and outputting the signal to an adder; Outputs 2's complement to adder, if negative The first input signal generator for outputting the number to the adder, the input register is updated every clock by the code signal generated by the adder, and the square root controller for outputting a control signal for controlling the square root operation to perform the square root operation It is characterized by performing.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram of a floating computing device capable of processing division and square roots in one data path according to an embodiment of the present invention. As shown in FIG. 1, a configuration of a floating computing device capable of processing division and square roots in one data path according to an embodiment of the present invention includes an input register 4 and an input register 4. A first input signal generator 5 connected to an output terminal, an adder 6 connected to an output terminal of the first input signal generator 5, and a shifter connected to an output terminal of the adder 6; 7), a register for storing the value of the shifter 7, a second input signal generator 14 connected to the output terminal of the register 8 to feed back the signal to the adder 6, and the register 8; PLA (3) is connected to the output terminal of the, the positive register (9) and negative register (11) connected to the output terminal of the PLA (3), the positive register (9) and negative register (11) Connected to the shifters 10 and 12 and the registers 8, 9 and 11, respectively. Made of a sticky bit generating section 13, a root input generation unit 15, a division controller (1) and the square root of the controller 2 for controlling the division and square root operations.

The operation of the floating computing device capable of processing the division and the square root in one data path according to the embodiment of the present invention by the above configuration is performed as follows.

In the embodiment of the present invention, the division controller 1 or the square root controller 2 is selected and operated according to the operation selection signal Div / Sqrt, thereby performing a division operation or a square root operation. Here, the division process and the square root operation described above will be described separately, and in the case of an extended presentation, it has a 64-bit fractional bit, a 15-bit exponential bit, and a 1-bit sign bit. Assume

1. Division operation

The basic algorithm of the division operation uses the SRT (Sweeny, Robertson, Tocher) algorithm, which calculates the positive and negative quotients by two bits and then divides the positive values by the negative values in the last cycle. This is how you decide. Therefore, in order to obtain an output of 68 bits, 34 operations are required. After that, the difference between the positive value and the negative value can be obtained to obtain a value.

The code signal Qi is stored in the 64-bit input register 4 and then output to the first input signal generator 5.

A code signal input from the input register 4 and a divisor signal for dividing an input signal from the first bus ABUS are input to the first input signal generator 5. At this time, the output signal of the first input signal generator 5 is determined by a 3-bit signal (Adder_Abus selection) output from the PLA (3).

The adder 6 adds a signal input from the first input signal generator 5 and a signal input from the second input signal generator 14 and outputs it as a code signal Qi.

The output signal Adder_out of the adder 6 is stored in the register 8 after being shifted two bits by the shifter 7, and thus the upper four bits of the signal Rem_register stored in the register 8 are PLA (3). Will be printed).

The PLA 3 compares the upper four bits of the divisor signal with the upper four bits of the signal Rem_register inputted from the register 8, where a Robertson diagram as shown in FIG. Table is used. That is, PLA 3 is a logical table of the Robertson diagram of FIG. The PLA 3 compares the upper four bits of the divisor signal Divisor with the upper four bits of the signal Rem_register input from the register 8 to determine the quotient, and then divides the divisor in the first input signal generator 5. Generate a value that is multiplied by -2, -1, 0, 1, or 2 to the divisor.

When the above process is repeated 34 times, the positive register 9 and the negative register 11 are 68-bit positive values (Pos_req) by the 2-bit signals pos_Q and neg_Q output from the PLA 3 each time. ) And the negative value (Neg_req) are stored.

In the sticky bit generator 13, the value (Rem_register) stored in the register 8, the least significant bit value of the positive register 9, the least significant bit value of the negative register 11, and the sign bit After receiving the input signal, the 4-bit sticky signal is made and then replaced by the least significant 2 bits of the positive register 9 and the least significant 2 bits of the negative register 11 and outputs it to the third bus (RBUS).

2. Square Root Operations

The algorithm used to find the square root is First, suppose the relationship between two binary numbers A and Q is as follows.

Q = √A = 0. q1 q2 q3 q4 q5 ........................ qn

A = Q ² = 0. a1 a2 a3 a4 a5 ........................ a2n-1 a2n

First, we start by subtracting 01 from the two-digit paired A value a1 a2. So when the result is positive, we take quotient q1 as 1 and subtract q1 01 from a1 a2 a3 a4. However, if the result is negative, the quotient q1 is zero, and q1 11 is added. Therefore, 66 cycles are required to obtain the 66-bit quotient.

First, when the square root start signal start_sqrt is generated by the square root controller 2, a 68-bit signal (0, A_bus [63) from the first bus ABUS as the square root input signal sqrt_input is input to the square root input generator 15. : 0], 000) is input to the positive register 9. In this case, if the square root input generator 15 determines the exponential input signal Exp_LSB, and if the value of the exponent is odd, the square root input signal sqrt_input is shifted by one bit and input to the positive register 9. When the exponent value is even, the square root input signal sqrt_input is input to the positive register 9 without being shifted.

Next, when the square root command signal Sqrt_op is pulsed high in the square root controller 2, the positive register 9 shifts the stored value Pos_reg by two bits, and the most significant two bits into the register 8 are applied. Is outputted, so that the least significant two bits of the register 8 are replaced. The value stored in the register 8 is output to the second input signal generator 14 and stored. Therefore, the most significant two bit value (Pose_reg [67:66]) of the positive register 9 is stored in the least significant two bits of the second input signal generator 14, and the upper 65 of the second input signal generator 14 is stored. The upper 65 bit value (Rem_register [67: 2]) of the register 8 is stored in the bit. The least significant two bits of the register 8 are replaced with zeros. The 68-bit signal Adder_Bbus stored in the second input signal generator 14 is input to the adder 6, and the other input of the adder 6 is 68 from the first input signal generator 5. The bit signal Adder_Abus is input. At this time, the first input signal generator 5 outputs two's complement of the stored value when the square root start signal start_sqrt is output from the square root controller 2. Next, the input signal generator 5 determines the sign signal Qi. If the sign signal Qi is positive, the value of combining the value Sqrt_Q_Reg of the input register 4 with 01 as the least significant two bits is set to two. If the sign signal Qi is negative, the output is taken with a complement, and the value Sqrt_Q_Reg of the input register 4 is combined with 11 as the least significant two bits. The input register 4 is updated with the combined value of the 65 bits and the sign signal Qi each time the operation of the clock is completed. After this process 64 times, the square root value is generated in the input register (4).

The present invention described above is capable of various substitutions, modifications, and changes within the scope without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains, and thus is limited to the above-described embodiments and drawings. It is not.

The present invention has the advantage that the circuit can be economically constructed, the chip size can be reduced, and the processing speed can be increased by allowing the adder and the data path to be shared so that square root and division can be separately calculated.

Claims (5)

PLA, where Robertson algorithm for division operation is tabled, a shifter for shifting the output signal of the adder by 2 bits, and a register for storing the shifter output signal and being input to the PLA, and 2 each time from the PLA. It consists of a positive register and a negative register which store the quotient output bit by bit, and a division controller which outputs a control signal for controlling the division operation to perform a division operation and output a signal shifted by 2 bits according to the square root command signal. A positive register, a second input signal generator for generating a signal according to a signal input from the positive register, and outputting the signal to an adder, and if the sign signal is positive, a two's complement of the dividend is output to the adder. A first input signal generator for outputting the dividend as it is; Division and square root in one data path, comprising a square root controller for outputting a control signal for controlling the square root operation and an input register updated every clock by a sign signal generated from the signal. Floating computing device that can handle. The data path of claim 1, wherein the operation unit performs a division operation by obtaining a positive quotient and a negative quotient by 2 bits, and then, by setting the quotient of the negative value minus the negative value in the last cycle as the quotient. Floating operation unit that can handle division and square roots. The floating computing device of claim 1, wherein the output signal of the first input signal generator is determined by a 3-bit signal output from the PLA. The first input signal generator generates a negative signal of -2, -1, 0, by determining the quotient by comparing the upper 4 bits of the divisor signal with the upper 4 bits of the signal input from the register. A floating computing device capable of processing division and square roots in one data path, characterized in that the value is multiplied by one or two times. The method of claim 1, wherein the square root input generation unit determines an exponent input signal, and if the value of the exponent is odd, the square root input signal is shifted by one bit to be input to the positive register. A floating computing device capable of processing division and square roots in one data path, characterized in that the signal is input to a positive register without being shifted.