JP2607759B2 - Divider - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a divider, and more particularly, to a divider having a division circuit configuration suitable for vector processing and floating point coprocessor processing.

[0002]

2. Description of the Related Art Conventionally, in the case of a divider, the number of operation cycles is extra than that of another operation unit, for example, an adder or a multiplier. Had become. Conventional methods of division include, for example, restoring division, non-restoring division or a high radix restoring division that applies them, high radix non-restoring division,
Further, various methods are known, such as iterative approximate division using a multiplier.

[0003] In recent years, with respect to various types of operations, high-speed operations have been increasingly demanded, and thus there is an increasing need to perform division operations at high speed and accurately. However, as described above, the division operation needs to execute a fairly complicated operation, and is required to output an accurate operation result without any error. And it is very difficult to achieve it at high speed. Therefore, in the related art, such a dividing circuit is considerably large in terms of hardware, so that it is usually configured separately from other arithmetic circuits. There was a drawback to say.

For example, conventionally known divisors and non-divisors are divided into a plurality of bit units (radix), a division operation is performed for each predetermined bit unit, and a sign of a remainder value is determined to determine a predicted quotient value. In the high-radix non-restoring division method that employs an arithmetic method for correcting, if it is desired to operate at high speed and accurately, it is conceivable to increase the radix and reduce the number of division loops. Accordingly, an increase in the number of multiple generation circuits, an increase in the complexity of the quotient prediction circuit, and an increase in the quotient prediction circuit are inevitable. Furthermore, if the divider is one computing unit in the vector processor, the space on the chip that the divider can occupy is limited.

[0005] For this reason, it is necessary to reduce the area of the circuit for performing the division operation processing at high speed and accurately and the division operation circuit to a certain extent and realize the division operation on a one-chip vector processor. It is necessary to consider the points and to consider each trade-off.

[0006]

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned problems and disadvantages of the prior art and to provide a divider capable of executing a high-speed and accurate division operation. It is an object of the present invention to provide a divider as hardware which is small enough to be mounted in a chip composed of circuits.

[0007]

The present invention employs the following technical configuration to achieve the above object. That is, the present invention basically provides an input register for receiving operation data of a predetermined length composed of a divisor and a dividend, a plurality of division operation circuits for performing a division operation on the input operation data, and the division operation. In a divider composed of an output register that outputs the operation result of the operation circuit,
The divider is configured to continuously receive the operation data, execute a predetermined operation in the division operation circuit, and continuously output the operation result data after the operation processing. More specifically, an input register for receiving operation data of a predetermined length composed of a divisor and a dividend, a plurality of division operation circuits for performing a division operation on the input operation data, and the division An input operation data latch circuit for storing a part of operation data between the input register and the division operation circuit, the input operation data latch circuit comprising an output register for outputting the operation result of the operation circuit; A divider provided with an output data latch circuit for storing data of a part of the operation processing result between the circuit and the output register; and a predetermined length comprising a divisor and a dividend. Sano An input register that can continuously receive a plurality of division data, a plurality of division operation circuits for performing a division operation on input operation data, and an output register that continuously outputs a plurality of operation results of the division operation circuit. And an input operation data latch circuit for storing a part of operation data between the input register and the division operation circuit, and a part between the division operation circuit and the output register. And an output data latch circuit for storing data of the result of the arithmetic processing. Furthermore, the divider according to the invention is particularly suitable as a hardware divider in a vector processor and as a divider as a floating point coprocessor.

[0008]

According to the present invention, like a vector processor, a plurality of operation data are continuously input, the operation data is subjected to a continuous division operation, and the result is output continuously. In the required system, after receiving a predetermined number of operation data at the same time, or in a method of processing the operation data one by one like a floating point coprocessor, While the operation data is partially executed by the division operation circuit of the divider, the operation data of the remaining portion is temporarily stored in the input side latch circuit, and the division of the operation data is performed. When the arithmetic processing is completed in the arithmetic circuit, the arithmetic processing result data for which the arithmetic processing has been completed is temporarily stored in the output-side latch circuit, and during the time, the remaining arithmetic data is stored in the division arithmetic circuit. Performed in Processing to perform the one in which was set to be output in the order calculation result and said output-side operation result stored in the latch circuits are simultaneously and input of the operational data of the portion of the 該残Ri.

[0009]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a divider according to the present invention. FIG. 1 is a diagram illustrating the principle of a divider according to the present invention, and a diagram illustrating a specific example of the divider according to the present invention. That is, a divider 2 provided on a part of a chip 1 constituting a semiconductor integrated circuit. The divider 2 successively outputs operation data of a predetermined length composed of a divisor and a dividend one by one. Alternatively, a plurality of input registers 3 can be collectively received, and a plurality of division operation circuits 4 (4─1, 4─2...) For performing division operation of inputted operation data.
4─n) and the division operation circuit 4 (4─1, 4─2...
(4─n) is composed of an output register 5 for sequentially or collectively outputting a plurality of operation results, and is input between the input register 3 and each of the division operation circuits 4. Of the operation data, an input operation data latch circuit 6 (6 #) for storing a part of operation data
.., 6} n) and an output data latch circuit 7 for storing data of a result of a part of the arithmetic processing between each of the division operation circuits 4 and the output register 5. (7
{1, 7 # 2,..., 7 # n). Further, in the divider of the present invention shown in FIG. 1, a part of the plurality of operation data sequentially or collectively input to the input register 3 is supplied to the division operation circuit 4 or the input operation Selection means 8 (8 # 1, 8 # 2...) For selecting whether to temporarily store data in data latch circuit 6.
(8─n) is provided between the input register 3 and each of the division operation circuits 4, and between each of the division operation circuits 4 and the output register 5, the division operation circuit 4 is output directly to the output register 5 or the operation result data stored in the output data latch circuit 7 is output to the output register 5.
There is provided a selection means 9 for selecting whether or not to output the data.

The division operation circuit in the present invention is not particularly limited, but is preferably a high radix non-restoring divider. The high radix non-restoring division method used in the present invention is conventionally known, in which a divisor and a non-divisor are divided into a plurality of bit units (radix) and a division operation is performed for each predetermined bit unit. There is, therefore, a calculation method for obtaining a quotient of n bits, for example, 4 bits, in one cycle time, and correcting the predicted quotient value by judging the sign of the surplus value. FIG. 2 shows a specific example of the configuration of the division operation circuit 4 of the high radix non-restoring divider used in the present invention. For example, as shown in FIG. 2, a divisor register 21 receiving operation data from the divisor input register 3 # 1, a partial remainder register 24 receiving operation data from the dividend input register 3 # 2, a multiple generator 22, an adder / subtractor 25, A partial quotient predictor 23 composed of a partial quotient predictor 231 and a partial quotient generator 232, a surplus register (RMD) 26, a surplus correction circuit (RMDC) 27, a quotient correction unit (QG), and a quotient register (QR) 29; The output value of the partial quotient prediction means 23 is used to predict the bit of the partial quotient from the upper bits of the output of the adder / subtractor 25 and the upper bits of the divisor register 21. An example of a specific method of the above division operation method will be described. The value of the partial remainder register (PR) 24 and k times the divisor (for example, ─ (r─1), ─ (r─2), ..., $ 1, +
1,..., R─2, r─1 times (where r is a radix) and a divisor register (DPA)
When calculating the predicted partial quotient from the value of (SR) 21, it is noted that the upper bits of the predicted partial quotient are determined by the upper bits of the addition / subtraction result (CPA) and the upper bits of the divisor register (DSR). And the above addition / subtraction result (CP
A), the predicted partial quotient (P) from the divisor register (DSR) 21
PQ) is obtained by using a suitable search means such as a search table to obtain a predicted partial quotient (PPQ). In the above-described division operation circuit, when actually performing the operation, the divisor D is stored in the divisor register (DSR) 21 in FIG. 2 and is input to the multiple generation circuit (MDG) 22 first. The multiple generation circuit (MDG) 22 receives the partial quotient prediction number (m) from the partial quotient prediction register (QP) 28 and, for example, when the radix r is 16, $ 15, $ 14, $ 1
3, ..., $ 2, $ 1, 0, +1, +2, ..., +
This is a circuit for creating a divisor of 14, +15 times. After the dividend N is set in the partial remainder register (PR) 24 at the beginning of the operation, a new partial remainder is set every operation cycle. Next, the output of the partial remainder register (PR) 24 and the divisor m × D (−15 ≦ m)
≤ + 15; m is an integer), and the result is added to the partial remainder register (PR) 24 and the partial quotient prediction circuit (QP) 2
3. Output to the remainder register (RMD) 26 and the like. A remainder register (RMD) 26 is a register for holding a final prediction remainder of the repetition operation, and outputs a correct remainder through a residue corrector (RMDC) 27 after completion of the addition / subtraction repetition operation. A specific correction method in the residue corrector (RMDC) 27 is that, for example, when the sign bit of the residue register (RMD) 26 indicates a negative number, the value obtained by subtracting 1 from the value of the multiple m is input again to calculate. Performs processing and remainder register 2
The arithmetic processing is performed until the value of 6 becomes positive. When the sign bit is a positive number, the operation is performed so that the value as it is is remainder. The partial quotient correction unit (QG) 28 determines an accurate partial quotient by referring to the output of the partial quotient prediction register (QP) 23 and the sign bit of the output of the adder / subtracter 25, and
R) Store in 29. Prediction quotient register (QP) 233
Is the output of the adder / subtractor 25 and the divisor register (DSR) 21
Is a circuit for calculating the value of m of m × DSR to be added or subtracted next from the output of. Further, the division operation circuit 4 according to the present invention may include a subtraction unit for a floating-point exponent part, an invalid operation, and an exception detection unit in addition to the above configuration example. In addition, the divider according to the present invention is provided with the division operation circuit 4 and includes a pre-division processing unit 10 for performing a floating-point operation type determination according to the IEEE standard, and a rounding unit for correcting output operation result data. 11 may be provided.

The pre-division processing unit 10 used in the present invention is provided between the input register 3 and the division operation circuit 4 as described above. In the present invention, the input register 3 is a register (OPD) 3 # 1 for inputting a divisor D and a register (OPD) for inputting a dividend N.
D) 3─2, and each of the registers simultaneously receives a plurality of continuous arithmetic data composed of a predetermined number of bits, or the arithmetic data is It may be accepted.

In the division pre-processing unit 10 used in the present invention, the type of input data is determined based on the IEEE standard, and the sign of floating point, exponent, and mantissa are cut out.
And a block for restoring the hidden bits of the mantissa and determining the magnitude of the mantissa. The type determination of the input data is defined in the IEEE standard,
For example, an inappropriate division format is previously registered as a division operation, such as N divided by 0 or infinity divided by infinity.
This is a circuit for detecting whether or not the combination of the divisor and the dividend to be calculated corresponds to the division format.

The operation data used in the division operation circuit according to the present invention has a data structure of 64 bits in the double precision processing, and has 32 bits in the single precision processing. Therefore, FIG. 3 shows an example of a data configuration format in the case of performing double precision processing in the present invention. That is, the format including the sign bit S is composed of 64 bits, the next 11 bits after one sign bit represent the exponent part, and the next 52 bits represent the mantissa part. However, the hidden bits are restored at the head of the mantissa and used for division of the mantissa described later.

In the present invention, the divisor D and the dividend N
The division operation is performed such that the mantissa part of the divisor D is always larger than the mantissa part of the dividend N by comparing the magnitudes of the mantissa parts. Therefore, if the mantissa part of the dividend N is larger than the mantissa part of the divisor D in the comparison process between the two, the dividend N is shifted right by one bit, and 1 is added to the exponent part on the dividend side.
Will be added.

FIG. 4 shows a flowchart of such preprocessing. That is, the divisor register 3 # 1 and the dividend register 3 # 2
In step (a), only the mantissa of each operation data is extracted from the operation data input to each of them. Here, the fact that 1 is provided before the mantissa data means that a hidden bit has appeared. ) Then, the magnitudes of the mantissa parts of both operation data are compared (step (b)).
If the dividend N is smaller than the divisor D, (step (c))
The operation data of the dividend N is directly stored in the partial remainder register 24.
If the dividend N is larger than the divisor D, the data of the dividend N is shifted right by one bit in step (d), and the data of the dividend N is forcibly reduced by one digit, and N <D The following condition is realized. Therefore, the balance between the divisor and the dividend is lost, so that the balance is restored by adding 1 to the exponent of the dividend.

FIG. 5 shows an example of a circuit configuration of the exponent operation section 104 provided in the division operation circuit 100 used in the present invention. The exponent of the divisor D and the exponent of the dividend N are appropriately bias-added. Is performed, and an exponent value after division is determined. Further, the pre-processing unit used in the present invention is provided with a circuit for executing exception detection and invalid operation detection for detecting an inappropriate type of division in the division operation as described above, After input operation data (also referred to as an input operand) of a divisor and a dividend configured with a predetermined number of bits are input to each of the divisor register 3 # 1 and the dividend register 3 # 2, an appropriate input type determination circuit ( (Not shown), and is output to a rounding circuit unit 11 to be described later via an appropriate register.

FIG. 6 shows a specific example of the configuration of the rounding section 11 used in the division operation circuit of the present invention. FIG. 6 is a known block for performing a rounding process based on the IEEE standard. This block has a guard bit (Guard bit
), Round bit (Round bit), sticky bit (Sticky bit), to determine whether to add 1 to the quotient or round down, and in the case of invalid operation, the corresponding pattern is generated Yes, for example, sign data D1 and exception data D input from the division operation circuit
2, a predetermined arithmetic process is executed using each data such as the exponent data D3, the remainder data D4, and the quotient data D5. When an exception occurs, a pattern corresponding to the exception is generated to control the output value. Furthermore, I
An exception flag according to the EEE standard is also generated.

In the present invention, as described above, the divider is suitable for performing high-speed and continuous arithmetic processing on a large amount of operation data, and is particularly suitable for use in a vector processor. is there. Further, the divider according to the present invention is also suitable as a divider used in a floating-point coprocessor adopting a method of sequentially taking a large number of operation data, executing a division operation, and sequentially outputting the operation result. Things. Therefore, in the former method, in particular, a plurality of operation data composed of a predetermined number of bits are simultaneously inputted to the divider serially, and the plurality of operation And the plurality of operation data relating to the dividend are serially stored in a divisor input register 3 # 1.
And the dividend input register 3 # 2, respectively.

Therefore, in the divider according to the present invention,
The serially input plural serial operation data is taken into the divider every predetermined number of operation data, and the division operation processing is executed in the set unit, and the result is continuously output in the set unit. It is configured so as to output in a targeted manner.

In the present invention, a predetermined number of calculation data P
Is not particularly limited, but four may be taken as an example. That is, under such conditions, four serially consecutive operation data relating to the divisor are simultaneously input to the divisor input register 3 # 1, and four serially consecutive operation data relating to the dividend are referred to as the dividend. The data is continuously and simultaneously input to the input register 3 # 2.

In the present invention, in order to execute the above-mentioned division operation processing, a plurality of division operation circuits 4 which are the main components of the divider according to the present invention are provided in parallel. An input operation data latch circuit 6 for storing a part of operation data between the register group 3 and the division operation circuit 4
However, an output data latch circuit 7 for storing data of a part of the result of the arithmetic processing is provided between the division operation circuit 4 and the output register 5.

The number M of the division operation circuit 4 according to the present invention
Although not limited, at least two of them are arranged in parallel, and it is preferable to set the number to be smaller than the number P for simultaneously taking in the above-mentioned operation data from the viewpoint of simplifying the circuit configuration. That is, it is desirable to maintain the relationship of M <P. Therefore, as one specific example of the present invention,
Assuming that the number P of operation data to be taken in at the same time is four, the number of the division operation circuits 4 is, for example, two.

Next, in the present invention, an operation data latch circuit is arranged for each of the plurality of division operation circuits 4 # 1, 4 # 2... 4 # n. An input operation data latch circuit 6 is provided on the input side of the operation circuit, and an output data latch circuit 7 is provided on the output side. The input operation data latch circuits 6 # 1, 6 # 2,.
.. 6─n indicates that one input operation data is the division operation circuit 4
While the operation is being performed in step (1), other input operation data to be processed in the next cycle of the division operation circuit 4 is latched.

The output data latch circuits 7 # 1, 7 #
2,..., 7─n are other input operation data processed by the division operation circuit 4 in the immediately preceding cycle during a cycle in which one input operation data is being executed by the division operation circuit 4 Is stored. Therefore, to show a specific example of executing the division operation according to the present invention, first, four sets of divisor operation data groups and four sets of dividend operation data groups are respectively composed of the divisor input register 3 # 1 and the dividend input data. When input to the register 3 # 2, the first divisor operation data, which is the head of the
And the dividend operation data of the first division operation circuit 4 # 1
The first division operation circuit 4 # 1 performs the division operation processing while the first division operation circuit 4 # 1 executes the division operation processing.
And the dividend operation data are input to the second division operation circuit 4 # 2 to execute the division operation processing.

Next, while the first division operation circuit 4 # 1 is executing the division operation processing, both the third divisor and the dividend operation data are temporarily stored in the first input operation data latch circuit 6 # 1. While the second division operation circuit 4 # 2 is executing the division operation, the fourth divisor and the dividend operation data are both temporarily stored in the second input operation data latch circuit 6 # 2. And waits in each latch circuit until the operation processing in the division operation circuit is completed.

The first input operation data latch circuit 6 # 1 according to the present invention further comprises a latch circuit 6 # 11 for latching divisor operation data and a latch circuit 6 # 12 for latching the dividend. It is also preferable that the second input operation data latch circuit 6 # 2 further includes a latch circuit 6 # 21 in which the divisor operation data is latched.
And a latch circuit 6 # 22 for latching the dividend.

When the first division operation circuit 4 # 1 completes the division operation processing on the first divisor and the dividend operation data, the operation result data is temporarily stored in a first output data latch circuit 7 # 1. It is stored and waits until operation processing result data relating to the next third operation data is output.
When the second division operation circuit 4 # 2 completes the division operation processing on the second divisor and the dividend operation data, the operation result data is temporarily stored in the second output data latch circuit 7 # 2. , And waits until operation result data on the next fourth operation data is output.

When the division operation processing for the third and fourth divisors and the dividend operation data is completed, the operation result data is sent to the first and second output data latch circuits 7 # 1 and 7 # 2. The first and the second temporarily stored
Along with the operation result data relating to the divisor and dividend operation data, are serially input to the output register 5 in the order of input to the divider and output to the vector register.
The above operation steps are the basic cycle of the division operation processing in the present invention, and these steps are repeated for every four sets of operation data.

In the above embodiment, a plurality of operation data are simultaneously received in the input register in the order of input. However, as described above, the present invention is also used as a divider in a floating point coprocessor. In such a case, a plurality of continuous operation data are sequentially received for each operation data in the input register, division operation processing is executed, and the operation results are sequentially output from the output register in the order of input. If the input timing of the input operation data is early due to the operation speed, the subsequent operation data obtained during execution of the division operation by the previous operation data is temporarily stored in the input operation data latch circuit. To keep
Basically, it is the same as the above-mentioned division operation method.

Next, the flow of the division operation processing of the division operation circuit 4 according to the present invention will be described below. This flow of the division operation processing is shown for a non-restoring division method using a radix of 16.

The structure of the operation data is as described above. Therefore, the number of division loops in this division operation processing flow is fifteen because the mantissa part including the hidden bits is 54 bits. The division operation at that time will be described using the following parameters. Dividend mantissa part: N divisor mantissa part: D partial remainder: PR (i) prediction quotient: QP (i) quotient: Q (i) If the numerical value to be obtained is a double precision IEEE format floating point,
The quotient must accurately determine 56 bits (14 digits). Initialization: PR (0) = N QP (0) = 0 ────────────────────────────────── 1 Round: PR (1) = PR (0)-QP (0) * D QP (1) = predict (PR (1), D) ────────────────── ──────────────── Second time: PR (2) = PR (1)-QP (1) * D QP (2) = predict (PR (2), D) Q (1) = QP (1) modified by PR (1) 's and PR (2)' s sigh-bit ──────────────────────── ────────── Third time: PR (3) = PR (2)-QP (2) * D QP (3) = predict (PR (3), D) Q (2) = QP ( 2) modified by PR (2) 's and PR (3)' s sigh-bit ────────────────────────────── ──── 4th time: PR (4) = PR (3)-QP (3) * D QP (4) = predict (PR (4), D) Q (3) = QP (3) modified by PR ( 3) 's and PR (4)' s sigh-bit ────────────────────────────────── 5th : PR (5) = PR (4)-QP (4) * D QP (5) = predict (PR (5), D) Q (4) = QP (4) modified by PR (4) 's and PR (5)' s sigh-bit ──── ────────────────────────────── ・ ・ ・ ───────────────── ────────────── 14th time: PR (14) = PR (13)-QP (13) * D QP (14) = predict (PR (14), D) Q (13 ) = QP (13) modified by PR (13) 's and PR (14)' s sigh-bit ────────────────────────── ────────── 15th time: PR (15) = PR (14)-QP (14) * DQ (14) = QP (14) modified by PR (14) 's and PR (15) 's sigh-bit に よ り By the above operation, the quotient becomes Obtained as shown. That is,
The format of the quotient obtained by the divider according to the present invention is as follows.
The bit is composed of an exponent part.
The quotients Q1... Q14 in each division operation cycle composed of bits are arranged in that order. still,
The first bit after Q14 is a guard bit.
The second bit is a round bit, and (S) is a sticky bit which is a logical sum of the third bit and all bits of PR (15).

Although PR (15) does not represent a complete remainder (it may be a negative value), it is only necessary to determine whether the sticky bit is 0 or not. Good.

FIGS. 7 and 8 are block diagrams showing one specific example of the overall configuration of the divider according to the present invention. 7 and 8 that are the same as those shown in FIG. 2 are denoted by the same reference numerals. In FIGS. 7 and 8, SEL is a selector.
And 9 are provided, and have a configuration in which necessary operation data can be selected during the division operation processing. Also, the division operation processing circuits 100 # 1 and 100 # in FIGS.
Reference numeral 2 denotes an exponent operation unit, an invalid operation, and an exception detection unit block provided in the division operation processing circuits 4 # 1 and 4 # 2. The processing circuit 100 also executes the processing of the operation data in the same manner as the above-mentioned division operation processing circuit 4. Therefore, a latch circuit group 106 is provided, and the input operation data relating to the exponent part is selectively selected by the selector SEL. It is determined whether the arithmetic data is stored in the register 101 or supplied to a predetermined processing circuit.
The processing is supplied to the exponent addition / subtraction processing unit 104 and the exception invalid operation detection unit 105 through 103 through 103 to execute the operation processing.

The operation result of each operation processing unit is temporarily latched in the exponent register 106 and the exception register 107, respectively, and then output to the rounding unit 11, and the division operation circuit 4 is supplied via appropriate latch circuits 170 and 171. Are successively output to the exception flag register 108 in the same manner as described above.

Next, the operation timing when vector processing is performed using the divider of the present invention shown in FIGS. 7 and 8 will be described with reference to the timing charts of FIGS. Even when the present invention is used as a divider of a floating-point coprocessor, its timing chart is substantially the same as that described below.

As described above, since four sets of operation data, ie, operands, are successively input to the input operation register, first, the first cycle, that is, 0 of the clock waveform (h) is output.
At the position, as shown in waveform (i), the first operand 1
10 is latched in the input register 3 of the divider. Similarly, in the second to fourth cycles, the second to fourth operands 11
1, 112 and 113 are sequentially latched in the input register 3 respectively.

From the second cycle to the fifth cycle, that is, from the position 1 to the position 4 of the clock waveform (h), the operands 110, 111, 1
Each of 12 and 113 is sequentially pre-processed and output from the pre-processing circuit. Therefore, in the second cycle, preprocessing is performed on the first operand, and the output is stored in the partial remainder register 24 and the divisor register 21 of the division operation circuit 4 # 1 on the first surface. (See 110 in waveforms (l) and (m).) During this time, the second operand is simply latched into input register 3. Next, the third cycle, that is, the clock waveform (h)
In position 2, the first operand is the divisor register 2
A division loop is started using a fixed value of 1 (waveform (l) 1
10 op1), the division operation is repeated 15 times up to the 15th cycle, that is, up to the 14th position of the clock waveform (h), and at the same time, the second operand is pre-processed (see 111 of the waveform (k)) The output is latched on the second side, that is, in the input register of the exponent operation unit and the mantissa division unit of the other division operation circuit 4 # 2.

As described above in the third cycle, the third cycle
Is latched in the input register of the divider. In the fourth cycle, ie, position 3 of the clock waveform (h), the second operand starts the division loop in the division operation circuit 4 # 2 on the second surface in the same manner as the waveform (l).
Repeat several times. The third operand 112 performs preprocessing, and outputs its output to the latch circuit 6 # 2 and the divisor register 21 for the partial surplus register 24 in the save register 6 (TMP) of the division operation circuit 4 # 1 on the first surface. It is stored in each of latch circuits 6 # 1. (See 112 in waveform (n).) Also, in the fourth cycle,
The fourth operand 113 is latched in the input register of the divider. At the fifth cycle, that is, at position 4 of the clock waveform (h), the first and second operands 110 and 111 continue the division operation loop, the third operand 112 waits in the save register as it is, and the fourth operand Reference numeral 113 performs preprocessing, and corresponds to the latch circuit 6 # 2 for the partial surplus register 24 and the latch circuit 6 # 1 for the divisor register 21 in the save register 6 (TMP) of the division operation circuit 4 # 1 on the first surface. The result is latched in the save register of the division operation circuit 4 # 2 on the second surface side. The operand latched in the save register is the first operand executed by the first operand.
The division loop of the surface division operation circuit 4 # 1 and the division loop of the second division operation circuit 4 # 2 in which the second operand is executed are finished in the 17th cycle on the first surface side, respectively. The 16th position of the clock waveform (h) on the second surface side is the 18th cycle, that is, the 17th cycle of the clock waveform (h).
Are latched in the input registers of the exponent operation unit and the mantissa division unit, respectively, to execute a division loop. (Waveform (l)
The first operand that has executed the division loop performs rounding processing and output determination processing in the 18th cycle (see 110 in waveform (0) and waveform (p)), and This is stored in the output save register (TMP) 7 of the division operation circuit 4 # 1 on the first surface. (See 110 in waveform (q)). On the other hand, the second operand 111 executed in the division loop on the second surface performs rounding processing and output determination processing in the nineteenth cycle, and the division operation circuit 4 # 2 on the second surface.
Is stored in the output save register (TMP) 7. (See 111 in waveform (r)). Then, the third operand 112 and the fourth operand 113 are output through a rounding process and an output determination block, that is, in the 31st cycle, the output register of the divider first stores the first operand in the first output save register. One operand result, then the second
The result of the second operand stored in the output save register, and the result of the division of the third and fourth operands are latched one cycle at a time in this order. (See 110, 111, 112, 113 of waveform (s))

According to the present invention, there is provided a divider capable of executing a high-speed and accurate division vector operation process, and is downsized so that it can be mounted in a chip composed of a semiconductor integrated circuit. Thus, a divider as hardware can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining the principle of a divider according to the present invention, and is a block diagram showing a specific example of a divider according to the present invention.

FIG. 2 is a block diagram showing a specific example of a division operation circuit used in the divider of the present invention.

FIG. 3 is a diagram showing an example of a format of operation data used in the present invention.

FIG. 4 is a flowchart showing a processing flow in an exponent addition / subtraction unit used in the divider according to the present invention.

FIG. 5 is a diagram showing an example of a circuit configuration in an exponent addition / subtraction unit used in the divider according to the present invention.

FIG. 6 is a block diagram showing an example of a circuit configuration of a rounding unit used in a divider according to the present invention.

FIG. 7 is an overall block diagram showing a specific example of a divider according to the present invention.

FIG. 8 is an overall block diagram showing a specific example of a divider according to the present invention.

FIG. 9 is a timing chart illustrating timings of a division operation process in the divider according to the present invention.

FIG. 10 is a timing chart for explaining the timing of the division operation processing in the divider according to the present invention.

FIG. 11 is a diagram showing a data structure of a quotient obtained by the divider according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Chip 2 ... Divider 3 ... Input register 4 ... Division operation circuit 5 ... Output register 6 ... Input operation data latch circuit 7 ... Output operation data latch circuit 8 ... Selection means 9 ... Selection means 10 ... Preprocessing unit 11 ... Rounding Unit 21: divisor register 22: multiple generating means 23: quotient predictor (predicted quotient register) 24: partial remainder register 25 ... addition / subtraction means 26 ... remainder register 27 ... remainder correction means 28 ... partial quotient generating means 29 ... quotient register 30 ... Type determination unit 100: exponent part division operation circuit 101, 102, 103, register 104: exponent addition / subtraction unit 105: exception invalid operation detection unit 106: exponent register 107: exception register 108: exception flag register 170, 171, 172 register

Claims (10)

(57) [Claims] An input register for receiving operation data of a predetermined length composed of a divisor and a dividend, a plurality of division operation circuits for performing a division operation on the input operation data, and an operation result of the division operation circuit And an input operation data latch circuit for storing a part of operation data between the input register and the division operation circuit. The division operation circuit and the output register And an output data latch circuit for storing data of a result of a part of the arithmetic processing. 2. An input register for receiving operation data of a predetermined length composed of a divisor and a dividend, a plurality of division operation circuits for performing a division operation on the input operation data, and an operation result of the division operation circuit A plurality of output registers that successively receive the operation data, execute a predetermined operation in the division operation circuit, and A divider configured to continuously output a plurality of operation result data. 3. An input register for continuously receiving a plurality of operation data of a predetermined length composed of a divisor and a dividend, a plurality of division operation circuits for performing a division operation on the input operation data, and the division An input operation data latch circuit for storing a part of operation data is provided between the input register and the division operation circuit. 3. The divider according to claim 2, further comprising an output data latch circuit for storing data of a part of the operation processing result between said division operation circuit and said output register. . 4. The division operation circuit includes at least a partial surplus register, a divisor register, a multiple generation unit, an addition / subtraction unit,
4. The divider according to claim 1, further comprising a partial quotient prediction unit and a partial quotient generation unit. 5. The input operation data latch circuit, wherein one input operation data is processed by the division operation circuit in the next cycle while the input operation data is being operated by the division operation circuit. 5. The divider according to claim 1, wherein? Is latched. 6. The output data latch circuit includes, during a cycle in which one input operation data is operated by the division operation circuit, another input operation data processed by the division operation circuit in the immediately preceding cycle. The divider according to any one of claims 1 to 4, wherein the arithmetic processing result data is stored. 7. The divider according to claim 4, wherein said division operation circuit further includes at least an exponent part operation means and invalid and exception operation means. 8. The divider according to claim 1, wherein a pre-processing operation means is provided between said input register and said division operation circuit. 9. The divider according to claim 1, wherein a rounding operation means is provided between the output register and the division operation circuit. 10. The method according to claim 1, wherein the number of the operation data input to the input register at one time is set to be larger than the number of the division operation circuits. The divider as described.