GB2296803A - Apparatus for arithmetically operating floating-points - Google Patents

Abstract

An apparatus for arithmetically operating on floating-point data comprises a normalization circuit 52 for normalizing a result obtained after an addition/subtraction operation for floating-point data a rounding circuit connected to an input of the normalization circuit, and a multiplexing circuit 48 for receiving an output signal from the rounding circuit and determining the operated result on the basis of the received signal. The apparatus reduces the number of steps involved in the sequential processing system from 4 steps, involved in the conventional case, including the exponential data alignment, operation, normalization and rounding to three steps including the exponential data alignment, operation/round estimation and normalization. The rounding can be achieved using an operating adder. <IMAGE>

Description

APPARATUS FOR ARITHMETICALLY OPERATING FLOATING-POINTS The present invention relates to an apparatus for arithmetically operating floating-points. For example, the invention relates to an apparatus for arithmetically operating floating-points, which performs a rounding procedure to ensure an accuracy of result values of addition/subtraction operations for floating-points.

Typically, addition/subtraction operations involved in an arithmetic operation for floating-points are processed in the order of exponential data alignment, addition/subtraction operations, normalization and rounding.

The exponential data alignment is an operation for eliminating an exponent difference between two operands prior to addition/subtraction operations for floatingpoints. The normalization is an operation for adjusting the fixed decimal part of a number such that it is within a pre-defined range without varying a real number part of the number when the number is expressed in accordance with the floating-point representation, thereby adjusting an exponent part of the number. The rounding is an operation for eliminating or omitting digits of a normalized number from its least significant location while adjusting the remaining digits in accordance with a certain rule.

In actual circuits, such a rounding is the procedure of truncating certain digits of the result value of the arithmetic operation (truncation) or adding "1" to the least significant bit (LSB) of the value (increment).

As a result, known devices, which arithmetically operate floating-points, use a separate incrementer or adder for the rounding. Otherwise, they use an operating adder which involves a feedback after the operation so that it can function as a rounding adder. However, such methods have a problem of increasing the size of the floating-point operating device and delaying the processing time because they require the incrementer or adder for the rounding operation.

In accordance with the standard of floating-point operation recommended by IEEE, the fraction part of an operand is expressed by an absolute value signing system.

In the case of such an expression system, when the result of an operation (subtraction) according to the 2's complement system has a negative value, it should be converted into a 2's complement. For such a conversion into the 2's complement, an inverter or incrementer is needed. This incrementer does not have any significant difference from a single adder in terms of the increased chip area and processing speed. In this regard, adder circuits of the 2's complement system should include two adders connected to each other in series or an adder involving a feedback of its operated result.

It is an object of the invention to reduce the abovementioned problems.

In accordance with one aspect, the present invention provides an apparatus for arithmetically operating floating-points, comprising: a normalization circuit for normalizing a result obtained after an addition/subtraction operation for data about floating-points; a rounding circuit connected to an input of the normalization circuit; and a multiplexing circuit for receiving an output signal from the rounding circuit and determining the operated result on the basis of the received signal.

An embodiment of the invention provides an apparatus for arithmetically operating floating-points, which can reduce the processing speed and circuit area of an operator performing a rounding procedure to ensure an accuracy of result values of addition/subtraction operations for floating-points.

In accordance with another aspect, the present invention provides a circuit for generating a rounding signal to process a rounding in parallel to an addition/subtraction operation, wherein guard, round and sticky bits all generated in an exponential data alignment circuit, a bit signal, generated in a l's complement system of an operating unit for performing the addition/subtraction operation and a carry generated in the l's complement system are simultaneously used for the rounding.

Embodiments of the present invention will hereinafter be described, by way of example, with reference to the accompanying drawings in which: Figure 1 is a block diagram showing a subtraction parallel calculation system using the 2's complement system to illustrate the principle of the present invention; Figure 2 is a block diagram showing a subtraction parallel calculation system, which is a combination of the 2's complement system and the l's complement system, to illustrate the principle of the present invention; Figure 3 is a block diagram illustrating an apparatus for arithmetically operating floating-points of the present invention; Figure 4 is a table illustrating a rounding procedure carried out when the result obtained by a subtraction carried out in the apparatus of Figure 3 has a negative value; and Figure 5 is a flow circuit illustrating data processing flows in the rounding circuit and arithmetic operation unit included in apparatus of Figure 3.

Figure 1 is a block diagram illustrating a subtraction parallel calculation system using the 2's complement system. This system performs an operation for two operands by changing locations of the operands by the 2's complement system and selects a correct result.

Figure 2 is a block diagram illustrating a subtraction parallel calculation system which is a combination of the 2's complement system and the l's complement system. This system selects the result obtained by an operation in the 2's complement system when the result obtained by an operation in the l's complement system has a positive value. In the reverse case, the system selects the result obtained by the operation in the l's complement system and then converts it into a l's complement.

Although the system using only the 2's complement system has a parallel structure, it needs two adders. On the other hand, the system of Figure 2 may be structured by adding a simple circuit to an adder such as a carry select adder or conditional sum adder. Where an operating device having the structure of Figure 2 is used it is possible to always obtain an accurately calculated value and a value incremented or decremented from the accurately calculated value by "1" in accordance with the operated result. In the case of the addition, it is possible to obtain an accurately calculated value and a value incremented from the accurately calculated value by "1". In the case of the subtraction, it is possible to obtain an accurately calculated value and a value decremented from the accurately calculated value by "1".

Where these two result values are directly applied to the rounding, it is important to take into consideration the fact that locations of round bits of each operated result value may shift due to a normalization always following either the addition or subtraction.

If the rounding procedure is executed prior to the normalization procedure, then locations of bits may shift in the normalization procedure, thereby generating errors.

If using various characteristics of normalized binary floating-point numbers, it is possible to perform the rounding procedure prior to the normalization without generating errors. In this case, the floating-point operation can be performed at a high processing speed because the rounding procedure is carried out in parallel to the addition operation.

In the case of the addition, the normalization following the operation involves a shift of only one bit toward lower-order bits or does not involve any shift.

When the carry generated after the operation is O, no shift is required. On the other hand, when the carry is 1, a shift of one bit is generated.

In the case of the subtraction, the normalized result has a more complex behaviour than that in the case of the addition. In other words, a shift with a large width is involved in the normalization. However, if a shift of at least 2 bits is generated in the exponential data alignment procedure, then the normalization involves either a shift of one bit toward higher-order bits or no shift. Among numbers which can be expressed in the fraction part, the smallest value one is expressed by "1.00 ..... 0" whereas the largest value one is expressed by "1.11 ..... 1".If subtracting the result, which is obtained after shifting the largest value number of "1.11 ..... 1" by 2 bits toward lower-order bits, from the smallest value one of "1.00 ..... 0", then the following result is obtained: 1.0000 00 ... 00 0000 - 0.0111 11 ... 11 1111 11 0.1000 11 .... 00 0000 01 From this result, accordingly, it is understood that if a shift of at least 2 bits is generated in the exponential data alignment procedure, then the normalization requires either a shift of one bit toward higher-order bits or no shift. Where the normalization involves no shift, guard, round and sticky bits all generated due to an exponential data alignment shift of at least 2 bits are used, as they are, as data for determining the rounding.When a shift of one bit is required for the rounding, round bits become guard bits so that they can be used as data for determining the rounding.

Where either a shift of one bit or no shift is generated in the exponential data alignment procedure, a shift with a large amount of bits may generate in the normalization procedure. In this case, however, only guard bits are generated whereas neither round bit nor sticky bit is generated. As a result, the result obtained after the normalization has only bits of O. Therefore, the data for determining the rounding includes only the guard bits generated in the exponential data alignment procedure.

This data may include no bit if no shift is generated in the exponential data alignment procedure. The following calculation procedure illustrates an example of such a case.

1.0000 00 ... 00 0000 - 0.1111 11 ... 11 1111 1 0.0000 00 ... 00 0000 1 Figure 3 is a block diagram illustrating an apparatus for arithmetically operating floating-points in accordance with the invention. Figure 5 is a flow chart illustrating data processing flows in the rounding circuit and arithmetic operation unit included in the apparatus of Figure 3.

The apparatus of Figure 3 will be exemplarily applied to a "Round to Nearest scheme which is one of four rounding schemes proposed by the IEEE Standard, in order to explain the operation thereof in detail. Where the system according to the present invention is applied to other schemes without any change or alternation, the same effects may be obtained.

"Round to Nearest" is processed using three kinds of rounding bits, namely, a guard bit G, a round bit R and a sticky bit Sy as follows: IF (G==O), truncation; ELSE IF (R==1 I Sy==1), increment; ELSE IF (LSB=-O), truncation; ELSE increment.

The rounding in the addition requires a simple processing procedure. When the carry resulted from the addition is 1, a shift of one bit toward lower-order bits is generated in the normalization procedure. In this case, accordingly, respective functions of guard, round and sticky bits vary. That is, the least significant bit SO of the result obtained after the normalization becomes a guard bit. The guard bit generated in the exponential data alignment procedure serves to a round bit. The round and sticky bits both generated in the exponential data alignment procedure serve to sticky bits. Where the carry is 0, the rounding bits keep their original functions.

In accordance with the following processing procedure, the result obtained by a calculation executed in the l's complement system, wherein 0 is applied to the carry-in of the adder, is selected in the case of the truncation. In the case of the increment, the result obtained by a calculation executed in the 2's complement system, wherein 1 is applied to the carry-in of the adder, is selected. In either case, the selection is made through a multiplexor because either the l's complement system or 2's complement system is performed in a parallel fashion.

IF (C--O), IF (G==O), truncation; ELSE IF (Rs I Sy=-1), increment; ELSE IF (So-=O), truncation; ELSE increment; ELSE IF (So-=O), truncation; ELSE IF (git1 I R==1 I Sy=-1), increment; ELSE IF (Sl==0), truncation; ELSE increment.

In the case of the subtraction, the result has a more complex aspect than that in the case of the addition.

Systems, which are designed for the subtraction, always use a substraction between one operand processed by the exponential data alignment procedure and the other operand.

The other operand is subtracted from the exponentially aligned operand. From such a structure, a processing procedure for the subtraction can be derived. Figure 4 illustrates the processing procedure carried out for the case wherein the result has a negative value (namely, the carry is 0). In the subtraction operation, the guard bit G, round bit R and sticky bit Sy are converted into G1, R1 and Sy1, respectively. At this time, an overflow V1 is also determined. Since the result is assumed to have a negative value, G1, R1 and Syl are inversely converted, thereby generating G2, R2 and Sy2, respectively. When the bit 5n-1 of the result obtained after the operation has a value of 0, shift of at least one bit is generated in the normalization procedure.Accordingly, values of round increment bits are determined from G2, R2 and Sy2 by estimating bit values of the final result from its bit 5n-l to its bit S1 in accordance with the "Round to Nearest" rounding method. For example, when the bit 5n-1 of the result has a value of 0, R1 and Syl become rounding bits.

In this case, accordingly, an overflow V2 is determined from G2, R2 and Sy2 by estimating the round from the above two bits R1 and Sy1. In this case, the value of G2 itself can not be substituted for the value of the bit SO of the result. Therefore, the value of G2 is substituted for the bit SO after being converted using a round complement circuit, shift~rl, prior to the normalization procedure.

When the bit 5n-1 of the result has a value of 1, no shift is generated in the normalization procedure. In this case, accordingly, G2, R2 and Sy2 keep their original functions for the rounding, as in the case of the addition. In the same manner as mentioned above, an overflow V3 is also generated. Finally, when the value of a multiplexor control signal generated for the rounding is 0, the result obtained by an operation executed in the l's complement system is selected. On the other hand, when the multiplexor control signal has a value of 1, the result obtained by an operation executed in the 2's complement system is selected. The final multiplexor control value is determined by "V1 + V2" when the bit S 1 has a value of 0, and by "V1 + V3" when the bit 5n-1 has a value of 1. For example, if both V1 and V2 are 1 when bit 5n-1 is 0, the operation for the final multiplexor control value involves an addition of 1 and a subtraction of 1 from the result of the addition. Consequently, this operation is the same as the addition of 0. The determination made in the case wherein the bit 5n-1 is 1 is based on the same reason as in the case wherein the bit 5n-1 is 0.

Where the result obtained after the subtraction has a positive value, a very simple processing procedure is needed. As mentioned above, the floating-point operating apparatus of the present invention has a structure involving a subtraction between one operand processed by the exponential data alignment procedure and the other operand in such a fashion that the other operand is subtracted from the exponentially aligned operand.

Accordingly, if a shift of at least one bit is generated in the exponential data alignment procedure, then the result obtained after the subtraction always has a negative value.

The result obtained after the subtraction operation may have a positive value only when no shift is generated in the exponential data alignment procedure. In this case, the guard bit, round bit and sticky bit for the rounding always has a value of 0. Therefore, the result obtained in the 2's complement system becomes a correct value. In this case, accordingly, the multiplexor control signal for the rounding has a value of 1 in order to select the result obtained by the calculation carried out in the 2's complement system.

As apparent from the above description, the multiplexor control signal for the rounding is generated by 8 signals generated in the exponential data alignment and operation procedures, in all the cases as mentioned above, the multiplexor control signal is generated in accordance with the following equation: Add (C'G (SO + R + Sy) + CSO (S1' (G + Sy + R) + S2))) + Sub (C'(Sn~l' (RSy + G) + 5n-1 (SO' G + GSy + RG)) + C) where, G: Guard bit; R: Round bit; Sy: Sticky bit; LSB LSB of the result generated in the l's complement system; S1: First bit of the result generated in the l's complement system; Sn~l:Most significant bit (MSB) of the result generated in the l's complement system; C: Carry generated in the l's complement system; Add: Addition operation; and Sub: Subtraction operation.

In designing a circuit using the above equation, the guard, round and sticky bits are generated in the exponential data alignment procedure whereas the bits and S1 are generated in the initial stage of a calculation carried out by the adder. The circuit is first structured on the basis of these bits and then added with the bits 5n-1 and C generated in the final stage of the calculation carried out by the adder. With such a structure, it is possible to prevent the processing delay generated due to the rounding circuit as much as possible.

For the case of Figure 4, a l-bit bidirectional shift is structured to provide the value of S0* to LSB. The shift toward MSB is generated in the case of the subtraction. In this case, its left shift mask has a value of R'G + RSyG'. The shift toward LSB is generated when an overflow is generated in the case of the addition (namely, the value of the output carry is 1). In this case, its right shift mask always has a value of 1).

As apparent from the above description, the present invention provides an apparatus for arithmetically operating floating-points, which includes an improved rounding structure. The apparatus reduces the number of steps involved in the sequential processing system from 4 steps, involved in the conventional case, including the exponential data alignment, operation, normalization and rounding to three steps including the exponential data alignment, operation/round estimation and normalization.

In accordance with the present invention, the operating adder is used for the rounding, thereby reducing the circuit area.

The floating-point operating apparatus of the present invention may be applied to various technical fields, for example, microprocessors and math-auxiliary processors in the computer field, digital signal processors in the multimedia field, industrially automated systems and robotics in the control system field, and location control and scientific calculation systems in the air and space industry field.

Although preferred embodiments of the invention have been disclosed for illustrative purposes, it will be appreciated that various modifications, additions and substitutions are possible, without departing from the scope of the invention as defined in the accompanying claims.

Claims (8)

1. An apparatus for arithmetically operating floatingpoints, comprising: a normalization circuit for normalizing a result obtained after an addition/subtraction operation for data about floating points; a rounding circuit connected to an input of the normalization circuit; and a multiplexing circuit for receiving an output signal from the rounding circuit and determining the operated result on the basis of the received signal.

2. An apparatus as claimed in Claim 1, wherein the data is processed using three sequential processing steps comprising an exponential data alignment, an addition/subtraction operation and rounding processing, and a normalization.

3. An apparatus as claimed in Claim 1 or Claim 2, wherein the rounding circuit performs a rounding in parallel to the addition/subtraction operation during the addition/subtraction operation prior to the normalization for the operated result.

4. An apparatus as claimed in any preceding claim, further comprising a carry select adder for performing the addition/subtraction operation for the floating-points.

5. An apparatus as claimed in any preceding claim, further comprising a subtraction parallel calculator for supporting a rounding for the addition/subtraction-operated result carried out by the rounding circuit, the subtraction parallel calculator being a combination of a l's complement system and a 2's complement system.

6. A circuit for generating a rounding signal to process a rounding in parallel to an addition/subtraction operation, wherein guard, round and sticky bits all generated in an exponential data alignment circuit, a bit signal generated in a l's complement system of an operating unit for performing the addition/subtraction operation and a carry generated in the l's complement system are simultaneously used for the rounding.

7. A circuit as claimed in Claim 6, wherein the signals are used to select a round processed in the l's complement system in parallel to a 2's complement system also included in the operating unit.

8. An apparatus for arithmetically operating floatingpoints substantially as hereinbefore described with reference to the accompanying drawings.