JP3295949B2 - Floating-point operation method and device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a floating-point arithmetic system and a device therefor, and more particularly to a floating-point arithmetic system having a function of executing a data conversion instruction for converting floating-point data into integer data.

[0002]

2. Description of the Related Art As shown in FIG. 2A, a floating-point data format to be used here has a sign part S of 1 bit, an exponent part E of 15 bits, and a bias value of 16384,
It is assumed that the mantissa M is represented by a 48-bit absolute value normalized expression. The bit string of M is represented by M ₀ M ₁ M ₂ ... M ₄₇
Then, the floating point data represents the following values.

[0003]

As shown in FIG. 2B, the target integer data format is 64 bits in format, but the lower 32 bits are a binary number in a signed two's complement representation, and the upper 32 bits. Assume that the bits are undefined. This integer data represents the following values.

[0005]

As shown in FIG. 3, a floating-point adder / subtractor 1 as a conventional floating-point arithmetic unit inputs two input operands OP1 and OP2, which are floating-point data whose mantissa is an absolute value, and the magnitude of the input operands OP1 and OP2. , A right shifter 12 for inputting the mantissa MS of the smaller operand of the comparison result of the comparison selector 11 and performing a right shift for digit alignment, and an output of the right shifter 12 for addition. An inverter 13 that outputs the input value as it is at the time of execution and outputs the one's complement of the input value at the time of subtraction, and inputs and adds the mantissa part ML of the operand of the larger operand which is the output of the inverter 13 and the comparison result of the comparison selector 11 A mantissa adder 14 that outputs a sum of the two at the time of execution and outputs a value obtained by adding “1” having the weight of the least significant bit to the sum of the two at the time of subtraction;
A bit position decoder 15 for detecting the position of the most significant '1' bit in the output of the mantissa adder 14, and an exponent based on the output value of the bit position decoder 15 by inputting the exponent part EL of the larger operand. Updater 1 for updating part
6, a normalizing shifter 17 for shifting the output of the mantissa adder 14 for normalization based on the output value of the bit position decoder 15, and the difference between the exponents of the input operands OP1 and OP2. And an exponent subtractor 18 that outputs

Next, the operation of the conventional floating-point arithmetic system and its device will be described.

The comparator selector 11 converts floating-point data having the format shown in FIG.
P1 and OP2 are input, the magnitude is determined, and the mantissa MS of the smaller operand is output as an input to the right shifter 12. The exponent subtractor 18 subtracts the exponent parts of the input operands OP1 and OP2 and outputs a difference between exponents.
Using that value, that is, the difference between exponents as the shift amount, the right shifter 12 calculates the mantissa M of the input smaller operand.
S is shifted right for digit alignment. The output of the right shifter 12 is input to the inverter 13.

When the execution instruction is addition, the inverter 13 outputs the input as it is. When the execution instruction is subtraction, the inverter 13 outputs the one's complement of the input.

[0010] The mantissa adder 14 adds the output of the inverter 13 and the mantissa part ML of the larger operand which is the output of the comparison and selector 11. At this time, when the execution instruction is addition, the sum of both inputs is output. When the execution instruction is a subtraction, a subtraction using a two's complement is executed in addition to the operation of the inverter 13 by adding “1” having the LSB weight to the sum of both inputs. .

The bit position decoder 15 has a mantissa adder 1
4 is searched, and the most significant bit position of "1" is retrieved.
That is, the position of the most significant '1' bit counted from the MSB to the lower position is detected.

The normalization shifter 17 shifts the output data of the mantissa adder 14 based on the output of the bit position decoder 15 until the most significant bit becomes '1'. At this time, when performing addition, a right shift is required by one bit for correction of overflow, and when performing subtraction, a left barrel shift is required.

In parallel with the above processing, the updating of the exponent is performed by the updater 16. This is realized by inputting the exponent part EL of the larger operand from the comparison selector 11 and subtracting the left shift amount executed by the normalization shifter 17 therefrom.

With the above processing, the floating point addition / subtraction is executed, and the result data R is output.

However, the computer system handles not only floating-point data but also integer data. Therefore, in some cases, it is necessary to execute a data conversion instruction for converting floating point data to integer data.

In a conventional computer system, a floating-point arithmetic unit is used only for floating-point arithmetic. In order to suppress the overhead of the number of elements, hardware for data conversion is not installed in the computer system, and an integer is used. Since the data conversion instruction is executed by controlling the arithmetic unit and the shift circuit for use by a microprogram or the like, the speed of execution of the conversion instruction cannot be increased.

[0017]

The above-mentioned conventional floating-point arithmetic method and its apparatus cannot execute a data conversion instruction for converting floating-point data into integer data which is effective for increasing the speed of a computer system. was there.

It is an object of the present invention to provide a floating-point arithmetic method and a device capable of executing a data conversion instruction by adding a very small amount of hardware.

The floating-point arithmetic method of the first invention is provided with a reverser exponent subtracter and right shifter and mantissa adder, floating
In the decimal point data format, absolute values are expressed for negative values.
In the integer data format used, two's complement table for negative values
In the floating-point arithmetic system using a floating-point adder / subtracter for performing addition and subtraction by inputting first and second input operands of floating-point data whose mantissa is an absolute value representation , the mantissa part is input by the exponent subtractor. The bias value of the exponent part and the bit length of the mantissa part are subtracted from the value of the exponent part of the floating-point data, and the mantissa is shifted by the right shifter for digit alignment using the result of the subtraction as a shift amount, and the right The floating-point data is converted into integer data by converting the output of the shifter into a two's complement representation using the inverter and the mantissa adder.

In the floating-point arithmetic device according to the second aspect of the present invention, the floating-point data format has an absolute value for a negative value.
2 for negative values in integer data format using value representation
Having first and second input units for inputting first and second input operands of floating-point data whose mantissa is an absolute value expression, respectively, wherein the first and second input operands are used. The mantissa of the larger operand of the first and second input operands is the first mantissa, the mantissa of the smaller operand is the second mantissa, and the exponent of the larger operand As a first exponent part, and an exponent subtraction for subtracting the respective exponent parts of the first and second input operands and outputting an exponent difference which is the difference between the exponent parts. And a right shifter for inputting the second mantissa and performing a right shift for digit alignment using the exponent difference as a shift amount. An inverter that outputs a one's complement of the input value during execution, an output of the inverter and the first mantissa part are input, and a sum of the output of the inverter and the first mantissa part is performed during addition; And a mantissa adder that outputs a value obtained by adding “1” having the weight of the least significant bit to the sum when the subtraction is executed, and a most significant bit “1” in the output of the mantissa adder. A bit position decoder for detecting a position, a shifter for normalization for shifting an output of the mantissa adder for normalization based on an output value of the bit position decoder, and the first exponent part. A floating-point adder / subtractor having an updater for updating the exponent part based on the output value of the bit position decoder; a first input operand to be inserted into the first input part; One of the data One of a first selector that outputs the first output, an exponent part of the first input operand that is inserted into an input part of the exponent subtractor, and a constant value that is determined from a bias value of the exponent part. And a second selector for selectively outputting the second input operand as the input of the right shifter by controlling the comparison selector and the inverter and the mantissa adder by a control signal, If the shifter for normalization outputs the input value without performing the shift operation and the sign of the second input operand is negative, the inverter outputs the one's complement of the input value and adds the mantissa. Adder having a weight of the least significant bit to the input value, and if the sign is positive, the inverter and the mantissa adder output the input value as it is. Is what you do.

[0021]

Next, embodiments of the present invention will be described with reference to the drawings.

In this embodiment, as in the prior art, FIG.
The floating-point data format shown in FIG.
Description will be made assuming the integer data format shown in FIG.

The numerical value represented by the floating-point data format shown in FIG. 2A is obtained by converting the bit string of M to M ₀ M ₁ M ₂
When · · · M _47, becomes as shown in the following (1).

[0024]

This value is obtained by moving the decimal point to the lowest place,
It can be rewritten as shown in (2) below.

[0026]

Here, it is assumed that Y = | E-16384-48 |. If E-16384-48 is zero or negative, numerical value (2) can be rewritten as shown in (3) below by further shifting the decimal point position.

[0028]

[0029] is an integer that the _{M 0 M 1 ··· M 46-} Y seek.

Here, the integer data format is shown in FIG.
As shown in (B), the lower 32 bits of the 64-bit length data
The bits represent the actual value. Therefore, floating in the point data format, shifting the bit string of counting from the upper starting from the 17th bit _{M 0 M 1 ··· M 46-} Y, 33 and subsequent bits counted from the upper is in the conversion to an integer data Must. The shift amount for that is Y
It is. That is, the mantissa part of the input floating-point data can be converted to integer data by right shifting by | E-16384-48 | bits. Note that the 32nd bit counted from the higher order includes a sign bit.

Here, assuming that the numerical value (1) represents a negative value, it is necessary to convert this to a two's complement expression. This is because the floating point data format uses the absolute value representation for negative values, while the integer data format uses two's complement representation for negative values.

In order to convert a numerical value into a two's complement number, first, a one's complement number is generated by an inverter, and the value and '1' having an LSB weight may be added by a mantissa adder.

As can be seen from the above description, E-
When the value of 16384-48 is a positive value, overflow occurs when converting floating-point data to integer data. Even if E-16384-48 is a negative value, 46
If -Y is greater than 30, an overflow occurs. The reason is that M ₀ M ₁ ... M _46-Y becomes 32 or more bit strings. The result when an overflow occurs is an undefined value.

Next, an embodiment of the floating point arithmetic unit according to the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a floating point arithmetic unit according to the present invention.

As shown in FIG. 1, the floating-point arithmetic unit of this embodiment includes a floating-point addition / subtraction unit 1 which is a conventional floating-point arithmetic unit and an operand OP1 of a comparison / selection unit 11.
And a selector 4 inserted at the input of the exponent subtractor 18.

As described above, the floating-point addition / subtraction apparatus 1 includes a comparison selector 11, a right shifter 12, and an inverter 13
, A mantissa adder 14, a bit position decoder 15, an updater 16, a normalization shifter 17, and an exponent subtractor 18.

Next, the operation of this embodiment will be described.

First, the floating point addition / subtraction will be described.

In FIG. 1, the selector 2 inputs and outputs OP1 of two input operands OP1 and OP2 of floating-point data having the format shown in FIG. 2A. The comparison selector 11 of the floating-point addition / subtraction apparatus 1 determines the magnitude of the input operands OP1 and OP2 and outputs the mantissa MS of the smaller operand as an input to the right shifter 12 for digit alignment. The output of the right shifter 12 is input to the inverter 13.

Hereinafter, except that the exponent part of the input operand OP1 input to the exponent subtractor 18 passes through the selector 3, it is completely the same as the above-mentioned conventional example. Omitted.

Next, the operation of converting floating point data into integer data will be described.

The floating-point data is input operand OP
2 and the mantissa is controlled by the control signal C so as to be input to the right shifter 12 via the comparison selector 11. The selector 2 outputs data in which all bits are “0”. This data is input to the mantissa adder 14 via the comparison selector 11. The selector 3 has a constant value 164
32 (= 16384 + 48) is selectively output. The exponent subtractor 18 outputs a constant value 16432, which is the output of the selector 3.
Is subtracted from the exponent part E of the input floating-point data, and the difference between the two is output. This difference value corresponds to the aforementioned Y.

The right shifter 12 outputs the output Y of the exponent subtractor 18
Is shifted to the right, the mantissa of the input floating-point data is shifted to the right, and the result is output to the inverter 13.

The inverter 13 plays a role of converting the integer data of the absolute value representation into the integer data of the two's complement representation. Therefore, in accordance with the value of the sign bit S of the input floating-point data format, when the input data is negative, each bit of the data is inverted to output one's complement data.

The mantissa adder 14 receives the data of which all bits are “0” from the comparison selector 11 and the integer data or its one's complement data from the inverter 13 and adds them. However, when the input integer data is negative, a value obtained by further adding “1” having the weight of LSB is output.

As described above, the absolute value expression is converted into a two's complement expression.

Under the control of the control signal C, the normalization shifter 17 passes the input data as it is and outputs the data as it is regardless of the output of the bit position decoder 15.

As described above, conversion from floating point data to integer data is executed. Naturally, the sign of the floating-point data is the sign of the integer data. When an overflow occurs, an undefined value is output.

[0050]

As described above, the floating-point arithmetic method and apparatus according to the present invention can be realized by adding a small circuit of two selectors to a floating-point addition / subtraction apparatus which is a conventional floating-point arithmetic apparatus. There is an effect that it is possible to execute a data conversion instruction which is a conversion of floating-point data into integer data which is effective for speeding up a computer system.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an embodiment of a floating-point arithmetic device according to the present invention.

FIG. 2 is a diagram showing formats of floating-point data and integer data.

FIG. 3 is a block diagram illustrating an example of a conventional floating-point arithmetic device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Floating-point addition and subtraction apparatus 2, 3 selector 11 Comparison selector 12 Right shifter 13 Inverter 14 Mantissa adder 15 Bit position decoder 16 Updater 17 Normalization shifter 18 Exponent subtractor

Claims (2)

(57) [Claims] An exponent subtractor, a right shifter, a mantissa adder, and an inverter, and a negative value in a floating-point data format.
Is negative for integer data format using absolute value representation
In a floating-point arithmetic system using a floating-point addition / subtraction device for performing addition and subtraction by inputting and subtracting first and second input operands of floating-point data whose mantissa part is an absolute value expression using a two's complement representation for a value, The bias value of the exponent part and the bit length of the mantissa part are subtracted from the value of the exponent part of the floating-point data input by the subtractor, and the mantissa part is shifted by the right shifter for digit alignment using the result of the subtraction as a shift amount. Converting the output of the right shifter into a two's complement representation using the inverter and the mantissa adder, thereby converting the floating-point data into integer data. . 2. A negative value in a floating-point data format.
Is negative for integer data format using absolute value representation
A first and second input unit for inputting first and second input operands of floating-point data whose mantissa part is an absolute value expression using a two's complement representation for the value; The magnitudes of the two input operands are compared, and the mantissa of the larger operand of the first and second input operands is the first mantissa, and the mantissa of the smaller operand is the second mantissa and the larger A comparison selector for outputting the exponent part of the operand as a first exponent part,
An exponent subtractor for subtracting the respective exponent parts of the first and second input operands and outputting an exponent difference which is a difference between the exponent parts; and inputting the second mantissa part and shifting the exponent difference A right shifter that performs a right shift for digit alignment as an amount, an inverter that receives an output of the right shifter, outputs an input value as it is when performing addition, and outputs a one's complement of the input value when performing subtraction, The output of the inverter and the first mantissa are input and the sum of the output of the inverter and the first mantissa is output at the time of addition and the weight of the least significant bit is further added to the sum at the time of subtraction. A mantissa adder that outputs a value obtained by adding the value “1”, a bit position decoder that detects the position of the most significant bit “1” in the output of the mantissa adder, and an output value of the bit position decoder. Before for Motozuki normalization A normalizing shifter for shifting the output of the mantissa adder; and an updater for inputting the first exponent part and updating the exponent part based on an output value of the bit position decoder. A floating-point addition / subtraction device; a first selector for selectively outputting one of a first input operand to be inserted into the first input unit and data in which all bits are 0; A second selector for selectively outputting one of an exponent part of the first input operand to be inserted into the input part and a constant value determined from a bias value of the exponent part, The control selector controls the comparison / selector, the inverter, and the mantissa adder to use the second input operand as the input of the right shifter, and the normalization shifter does not perform the shift operation and keeps the input value as it is. Output, If the sign of the second input operand is negative, the inverter outputs the one's complement of the input value, and the mantissa adder outputs the input value with the least significant bit weight '1'. , And if the sign is positive, the inverter and the mantissa adder output the input value as it is.