JPH01125625A - Division device - Google Patents

Abstract

PURPOSE:To increase the arithmetic speed of a division device by using an arithmetic circuit as well as two registers which realize the right and left shifts of the input data and hold the shift numbers required when a divisor and a dividend normalized in the hexadecimal notation are turned into the binary notation. CONSTITUTION:The higher 3 bits of a register 1 are sent to an encoder 2 after the input of a dividend and the reading zero number is detected and held by a register 3. This reading zero number is sent to a shifter 8 as the shift number when a selector 6 selects a signal line 22. When a selector 7 selects an input line 26 and a control circuit 10 instructs the left direction to the shifter 8, the shifter 8 shifts the output of the register 1 to the left by an extent equal to the reading zero number. The dividend normalized into the binary notation is held by a converging binary division circuit 9. Then a divisor also undergoes the same procedure and the circuit 9 carries out the converging division with 2 used as a radix by an instruction of the circuit 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a division device, and more particularly to a division device that performs division of floating point format data with a base of 16 using a convergent division method.

[Conventional technology]

Conventionally, in a division device that uses a convergent division method to divide floating-point format data with a base of 16, only the mantissa part of the divisor is normalized with a base of 2 (hereinafter referred to as @binary normalization) before division. The shift number at this time is held in a register, and based on the output, the mantissa division result (hereinafter referred to as
After performing a correction shift of simply “division result 1”, 1
Normalization using 6 as the base (hereinafter referred to as ``hexadecimal normalization''), or binary normalization of the mantissa before division for the divisor and dividend, and the shift number at this time is divided into two. A method was used in which the division results were held in registers, the outputs of each register were sequentially used, and the division results were corrected and shifted, followed by hexadecimal normalization.

[Problem that the invention seeks to solve]

In the former method in the conventional division device described above, 7\ means that the column of the first part KO of the division result remains, and the lower bits are lost accordingly, resulting in poor precision.After that, hexadecimal normalization is performed. In the latter method, in order to correct the division result, a right shift is performed corresponding to the shift number when binary normalizing the dividend, and the shift number when binary normalizing the divisor is Since it is necessary to shift to the left corresponding to the number, the lower bits are lost when shifting to the right, countermeasures are required in case the upper bits overflow when shifting to the left, and the obtained result needs to be hexadecimal normalized. There is a disadvantage that there is

[Means for solving problems]

The division device of the present invention includes a shifter that can shift input data left and right, two registers that hold shift numbers when binary normalizing a hexadecimal-normalized divisor and dividend, and
The division result obtained from the base-normalized divisor and dividend is 1
Addition a*at*t, -cw, b・7\ [Example] Next Next, the present invention will be explained with reference to FIG. 1st
The figure is a block diagram configuring an embodiment of the present invention.
is a register that temporarily holds the divisor or the mantissa of the dividend; 2 is a priority encoder that outputs the number of leading zeros in the upper three bits of the output of register 1; 3 is a register that holds the number of leading zeros of the dividend; 4
is the register that holds the number of leading zeros in the divisor, 5
6 is an arithmetic circuit that subtracts the output of register l and the output of register 2, and 6 is an arithmetic circuit that subtracts the output of the encoder 2 sent through the signal line 22 and the output of the arithmetic circuit 5 sent through the signal line 23 to the control circuit 10. The first selector 7 selects according to the instruction, the output of register 1 is sent by signal line 26, and the convergence M12 is sent by signal line 29 by 0.
A second selector 8 selects the output of the base/divider circuit 9 according to an instruction from the control circuit 10, which uses the output of the first selector 6 sent via the signal line 24 as the shift number, and selects the output from the signal line 27.
a shifter 9 that shifts the output of the second selector 7 sent by the controller to the left or right according to instructions from the control circuit 10;
1 is a division circuit which has internal registers, multipliers, etc. and performs convergent division with a base of 2, and 10 is a control circuit which controls the inside of this division device.

The operation of this dividing device will be described below based on FIG. First, the mantissa part of the dividend, which is floating point format data with a radix of 16, is input from the outside via the signal line 20, and the register IK is set. Top 3 of register l
The bits are sent to the encoder 2 via a signal line 21,
The number of leading zes p is detected and held in register 3. When the selector 6 selects the signal @22,
This number of leading zeros is the number of shifts.
It will also be sent to The selector 7 selects the input line 26, and the control circuit 10 instructs the shifter 8 to move to the left.
Shifter 8 shifts the output of register 1 (the mantissa part of the dividend) to the left by the number of leading zeros. The dividend thus binary normalized is held at 1 in the dividend register "-1" inside the convergence board binary division circuit.

Next, the mantissa part of the divisor, which is floating point format data with a radix of 16, is input from the outside via the signal il 20 K and set in register 1. The operation is the same as that for the dividend, except that the leading number is held in the register 4, and the binary normalized divisor is held in the divisor register inside the convergent binary division circuit 9. It will be done.

Thereafter, in response to instructions from the control circuit 10, the convergent binary division circuit 9 performs convergent division with a base of 2. Binary convergence division is a method of dividing the mantissa part using the following methods (1) to (3).

(1) Obtain the initial approximate value of the reciprocal of the mantissa part of the divisor by a method such as reading it from ROM, and multiply this by the mantissa part (denominator) of the divisor and the mantissa part (numerator) of the dividend to create a new denominator and numerator. get.

(2) Use a certain algorithm to obtain a value that, when multiplied by the denominator, approaches 1, and then multiply the denominator and numerator again.

(3) By continuing the operation in (2), the denominator is I.
When K converges, the numerator converges to the desired division result.

By the above binary normalization, the result of dividing the mantissa parts of the divisor and dividend is obtained in the following form.

L×××・・・・・・X or 0. IXX・・・・・・× (However, . is the decimal point position.) The bits of this division result may be shifted due to the left shift when the divisor and dividend are normalized in binary, and the decimal point position may be changed due to the convergence division. is shifted from the position based on 16, so the following three shifts are required to correct it.

(1) When the dividend is binary normalized, the division result is shifted to the left by the number of bits shifted to the left (denoted as d, where 0≦d≦3), so it is shifted to the right by d bits.

(2) When the divisor is binary normalized, the division result is shifted to the right by the number of bits shifted to the left (r; O≦r≦3), so it is shifted to the left by r bits.

(3) Since the decimal point position of the division result is shifted 3 bits to the right from the position where the base number is 16, by shifting the division result by 3 bits to the right, the decimal point position is shifted to the position where the base number is 16.

That is, a total right shift of d−r+3 bits must be performed. The calculation of d-r+3 is performed using the output of register 1 (=
d) and the output of the register 4 are input to the arithmetic circuit 5. With this subtraction, the carryout (signal line 25) is O
In this case, the selector 6 selects the signal line 23, so that the output of the adder 11 circuit 5 is sent to the shifter 8, and further,
When the selector 7 selects the signal line 29, the division result of the output of the division circuit 9 is corrected as follows according to the output of the arithmetic circuit 5. However, . is the decimal point position.

(2) When d-r+3-00 ・1×××・・・・
・・・× or ・01X×・・・・・・×03)
When d-r+3=1 -01XX----X
Or, ・001×・・・・・・×(C) d
When −r + 3 = 2 ・001×・・・・・・
・×([) When d-r+3=3 -0001X
-------X or ・0t)OOIX-...
...x-(a) On the other hand, if the carryout (signal line 25) is l, a right shift of 4 bits or more is required,
The signal llA25 notifies the exponent part circuit that the carryout is 1, and subtracts 1 from the exponent part of the quotient to keep the number of shifts to 3 bits or less. Otherwise, the same operation as in the case where the carryout is O is performed.The division result is corrected as follows.・ is the decimal point position.

■ When d−r+3=4 ・1×××・−−−−
X or ・01××・・・・・・×(F5 d
When -r+3=5 @OIXX・----X or ・001×・・・・・・× 4〇)
When d - r + 3 = 6 ・001×...
・・・×・0OOIX・・・・× In other words, except for the (@ in ■), the correction of the division result and the hexadecimal normalization process are performed in only one shift.

The calculation result obtained by K in this way is transmitted to the signal line 28. [Effects of the Invention] As explained above, the present invention is capable of performing division by binary normalizing the divisor and dividend, which are hexadecimal normalized numbers. Add the irregular correction shift number that occurs and the 3-bit correction right shift number generated by the convergent division method, and use the result to shift the division result to the right by -ffiK to prevent the loss of digits in the lower bits and improve accuracy. It has this effect. In addition, the number of shifts for correction is kept to a minimum, and in most cases, the division result is obtained in hexadecimal normalized form, so there is no need for normalization processing after division. In many cases, it also has the effect of improving calculation speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example circuit implementing the invention. 1: Register for setting the divisor and the mantissa of the dividend, 2: Priority encoder, 3: Shift number storage register (for dividend)
, 4...- Schiff) #Storage register (for divisor), 5.
...2-bit adder circuit with carry-out output, 6...Shift number selector, 7...
Shifter input selector, 8...Shifter, 9...
-...Convergent binary division circuit, path. Agent Patent Attorney Susumu Uchihara Figure 1

Claims (1)

[Claims] In a division device using a convergent division method for floating point format data, a shifter for shifting input data left and right;
Two registers that hold the number of shifts when normalizing the mantissa parts of the divisor and dividend normalized to a base of 6 using the shifter, and convergence from the divisor and dividend normalized to a base of 2. an arithmetic circuit that calculates from the two registers a shift number for returning the division result of the mantissa calculated by the type division method to a number normalized with 16 as a base by the shifter and a correction signal for the exponent part of the quotient; A dividing device characterized by having.