JPS63254525A - Dividing device - Google Patents

Abstract

PURPOSE:To perform the division at high speed by using a squaring circuit which can be designed more easily than a dividing circuit of a shift subtraction system with a comparatively small circuit scale and high executing speed. CONSTITUTION:When the arithmetic data to be used has a format using the mean expression, a multiplier 5 always applies (1+M) to the input data M(0<M<1) for multiplication. Therefore the arithmetic is not required for (1+Xn-1) and both multiplication and addition are attained just with a single arithmetic operation. For the square calculation, a divisor stored in a register 2 and a dividend stored in a register 3 are supplied to an arithmetic and logic unit ALU6 and the exponent parts of both the divisor and the dividend are updated with the matissa part of the divisor converted into X even with the arithmetic of a fixed decimal point. Then an arithmetic operation is carried out by the multiplier 5 by means of the values of both registers 2 and 3 storing the converted divisor and dividend. Simultaneously, an arithmetic operation of the fixed decimal point is carried out by a squaring means 4. Thus the arithmetic operations are sequentially carried out and the quotient is obtained in the (n) multiplication frequency. That is, the multiplication frequency is halved compared with the conventional frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a division device that performs convergent division using a floating-point type multiplier, an arithmetic logic unit, and a fixed-point squaring unit.

2. Description of the Related Art As a conventional division device, for example, Japanese Patent Application Laid-Open No. 61-20132
There is a publication No. 7, but the convergent division method is as follows: Q=Mu/B ・・・・・・・・・・・・・・・・・・
...(1) where Q is the quotient, A is the dividend, and B is the divisor.

Here, if B is normalized to 2 ≦ B < 1, then B
If X is determined as =-+-X and the equation (1) is transformed, the following is obtained.

It can be expressed as (2). Here, the denominator is (I X 52), and o (X < 2-1...
・・・・・・・・・・・・・・・・・・ From (3)
0(X32(2”)・・・・・・・・・・・・・・・
・・・・・・・・・・・・・・・(4) If the mantissa data is 32 pits or less, it is expressed as 1 in (1152),
Therefore, the quotient Q can be expressed as follows.

Q=A・ (1+x)(1+x2)(1+x4)(1+
x8)(1+x16)...(5)Here, X(,
= 1-B Let the dividend AO = A and transform equation (5), Q = (Ao +Ao 4o) (1+Xo2) (1+X
o') (1+Xo8) (1+xo16) ・
・・・・・・・・・・・・・・・・・・・・・・・・
・(6) A+ = Ao + Ao Xo, Xt = X
o, equation (6) becomes Q= (A1+A+ 41)(1
+X+2)(1+X1')(1+X+8)''47) Equation (5) can be expressed as the following adaptation expression.

In the division device, the calculations of equations (9) and (101) are repeated. Here, the number of calculations n indicates the number of calculations determined from the divisor or the mantissa data word length of the dividend.

The calculation result An obtained by performing a predetermined number of calculations becomes the quotient Q.

In addition, as an example of other division calculation circuits, there is a shift subtraction calculation circuit as shown in "High-speed calculation method for computers" by Kai Wang, translated by Horikoshi et al. In some cases, there are circuits that calculate the quotient in one machine cycle.

Problems to be Solved by the Invention However, in the above-mentioned convergent division method, calculations using multipliers are required twice as in equation (9) (1 (11) for one divisor and dividend update operation, and It was necessary to perform 2n multiplication operations.Also, as shown in equation (9), there was a process of performing multiplication and summation within one operation cycle.In this way, the conventional convergence type There was a problem with speeding up the division device.

In addition, in the division calculation circuit of the shift subtraction method, the calculation speed is increased like Booth's algorithm like a multiplier.
There was no means to reduce the circuit size, and the problem was that the scale was large and the calculation speed was slow.

In view of this point, it is an object of the present invention to provide a high-speed division device by using a multiplier and a fixed-point squaring circuit (or a fixed-point multiplier).

Means for Solving the Problems The present invention provides a first register that stores a divisor or a multiplication coefficient, a first selector that takes the output of the first register as one input, and a first register that stores a divisor or a multiplication coefficient. an arithmetic logic means having an output as one input; a second selector having an output of the arithmetic logic means as one input; and a multiplier performing a floating point multiplication operation coupled to the other input of the second selector. a second selector inputting the output of the second selector;
and a first register, a multiplication means using the output of the first selector as one input, and a squaring means for performing a fixed-point squaring operation, and the output of the squaring means is the same as the first register. said second input in combination with the other input of the selector.
The output of the register is coupled to the other input of the multiplication means and the other input of the arithmetic logic means, and the control means controls the multiplication means, the squaring means, the arithmetic logic means and the first and second selectors. , is a division device that performs convergent division.

action The present invention performs convergent division using the above-described configuration.

If the calculation data used is in a format using stingy expression, the multiplier always uses input data M (0<M
) is multiplied by (1+M). Therefore, (
9) The operation of (1+xn-1) in the formula is unnecessary,
Multiplication and addition are performed in one operation. Also, (1[1
In the square calculation of Equation 1, also regarding fixed point operations, the divisor stored in the first register and the dividend stored in the second register are first calculated by the arithmetic logic means (hereinafter referred to as MLU).
), update the exponent parts of the divisor and dividend, and convert the mantissa part of the divisor to become X used in equation (9). After that, the converted divisor and dividend are stored in the first and second
Using the value of the register, the calculation of equation (9) is performed using the multiplier, and the fixed-point calculation of the 0-formula is performed using the squarer. The above-mentioned problems of the conventional method can be solved by using a squaring means which is relatively small and has a faster calculation speed than a shift-subtraction type division circuit, which can perform calculations with half the number of multiplications.

Example The present invention is constructed based on a convergent division method.

The basic calculation method is shown in formulas (1) to 01),
Here, the format of the calculation data is expressed stingily, for example, EEEI
The calculation method when using the data shown in FIG. 3 based on the C format will be described.

Q=person/B ・・・・・・・・・・・・・・・
It is expressed as t131, where Q is the quotient, person is the dividend, and B is the divisor.

Now, if we consider the data format as shown in Figure 3, we get: By expressing it as in the equation 00, the mantissa part of the divisor becomes 2'(OjMa(1), which makes it possible to perform calculations using convergence methods such as equations (1) to (111).Here, 1-〇, 1M
When expressed as B-〇 and r, the G-mark type can be transformed as follows.

・・・・・・・・・・・・・・・・・・・・・・・・(
171 If the mantissa data is 32 bits or less, I
2-! ;-1, so (Equation 171 is expressed as follows.

Q = 11MaX(1+o,r)(1+(o,r)2
)(1+(o,r)4) Also, regarding the calculation of the exponent part, 2FA/2FB+1= 2FA-(Fa+1)= 2F
It can be calculated as A+FB , , , , (19).

Here, nine represents the one's complement of FB.

Also, if formula (181) is expressed as acclimatization formulas such as formulas (8) to (111), it can be expressed as follows.

Here, n is a value determined from the mantissa data length; for example, in the case of 32 pits, n=4.

By the way, the multiplier supports stingy expressions such as the IEEF calculation data format, so even if Q and r data are input, 1. Multiplication is performed in the form r. Tsumashi,
In formula I21), the calculation of (1+o, r) becomes unnecessary.

Furthermore, since the multiplication in equation (2) is a fixed-point squaring operation, if the same multiplier is used for the operation, the fixed-point and floating-point operations must be switched. Therefore, by introducing a fixed-point squarer, fixed-point and floating-point operations can be separated, and operations on expressions 121) and (1) can be performed simultaneously, reducing the number of multiplications by half compared to conventional division devices. can.

Taking this as the basic concept of the present invention, the first embodiment of the present invention will be described below.
This will be explained using figures. FIG. 1 is a block diagram showing an embodiment of a division device according to the present invention.

The division device is a multiplier 5゜1LU6 that performs floating point multiplication.
, a squarer (or fixed-point multiplier) that performs fixed-point squaring of the mantissa part4. Selector 1 for switching data input from register 2.3, squarer 4 or register 2.
It is composed of a control section 7 that controls each section of a selector 8 that changes the data input from the ALU 6 or the multiplier 5.

The operation of the division device of this embodiment configured as described above will be explained with reference to FIGS. 1 and 2. FIG. 2 is a flowchart showing the procedure for performing calculations.

First, in step 2, input the divisor data B and dividend data A stored in register 2 to the ALU 6, subtract the 1's complement of the exponent part of the divisor to the exponent part of the dividend, and update the exponent part of the dividend. , and is set in the register 3 through the selector 8. In step ①, the divisor is read out to ALU 6, the exponent part of the divisor is reset to 0, the exponent part of the divisor is updated, the mantissa part of the updated divisor in the exponent part is shifted to the left by 1 bit, 1 is set in the MSB, and the exponent part of the divisor is reset to 0. Set the two's complement of the result in register 2. This result becomes 0, ro, or the multiplication coefficient of equation (2). (Step ■■ is t18 respectively),
Compatible with side type. ) Next, in step 0, read the υ multiplication coefficient 0 and rO from register 2 and input them to the multiplier 5 through the selector 1. Also, read the updated dividend from the register 3 and input it to the multiplier 5, and input their product to the register. 3 as the updated dividend. At this time, the multiplication coefficient is 0.
In the multiplier, ro corresponds to the calculation data format of EEE, so 1. It will be multiplied in the form rQ.

Finally, the calculation of (1-4-o, ro) in the formula 930 becomes unnecessary. Also, when performing these multiplications in the multiplier 5,
The multiplication coefficient output from the selector 1 is input to the squarer 4, which performs a squaring operation on only the mantissa part, and returns to the selector 1. At this time, the squarer 4 performs a fixed/J% several-point operation, so unlike the multiplier 6, it does not square (1+o, ro), but 0. r
Find the square of O.

Next, in step (2), the dividend updated in step 0 is read out from the register 3 and inputted into the multiplier 5, the data from the selector 1Vi squarer 4 is selected, and this updated multiplication coefficient is inputted into the multiplier 5. Input and calculate the product with the dividend. At this time, at the same time, the squarer 4 has a multiplication coefficient of 0. Update ro.

Thereafter, the multiplication coefficient and the dividend are updated a number of times determined by the number of mantissa bits, and the dividend Am stored in the register 3 at the final time becomes the quotient to be obtained. (Step ■) As described above, according to this embodiment, the dividend and the multiplication coefficient can be updated in one step.

Note that the exponent part processing performed in step ■ is performed from step 0 to
(2) Operations may be performed in parallel.

As described in detail, the present invention uses a squaring circuit (second multiplier) that is easier to design than a shift-subtraction type division circuit, has a relatively small circuit scale, and has a high execution speed. As a matter of fact, the division speed can be reduced to about half compared to the conventional convergence method, and the division speed can be increased.

[Brief explanation of the drawing]

1 and 2 show a block diagram and a flowchart of a division device according to an embodiment of the present invention, and FIG. 3 shows a data format diagram of floating point representation. 1.8...Selector, 2.3...Register, 4...Fixed-point squarer, 6...
・Multiplier, 6...ALU17...
・Control unit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
figure

Claims (1)

[Claims] At least a first register that stores a divisor or a multiplication coefficient, a first selector that takes the first output of the first register as one input, and an arithmetic logic that takes the first output as one input. a second selector having one input as the output of the arithmetic logic means; a multiplication means for performing a floating point multiplication operation coupled to the other input of the second selector; a second register having the output as a first input; the multiplication means having the first register and having the output of the first selector as one input; and squaring means for performing a fixed-point squaring operation. the output of the squaring means is coupled to the other input of the first selector, and the output of the second register is coupled to the other input of the multiplication means and the other input of the arithmetic logic means. death,
A division device characterized in that the multiplication means, the squaring means, the arithmetic logic means, the first selector, and the second selector are controlled by a control means.