JPS5853218A - Digital filter - Google Patents

Abstract

PURPOSE:To treat all data which are larger than 1 and less than 2 as the data less than 1 in terms of the absolute value in an arithmetic process, by using an adding frequency controlling circuit which controls a holding register of the result of addition. CONSTITUTION:The output of an input register 12 is replaced with the output of a register 17 and added with the output of a holding register 23 of the result of multiplication which holds the product of a coefficient and the delay data to be compensated at a compensating circuit 15 for the result of addition. The corrected value of sum is held at a register 16 and then shifted to the register 17 which holds the result of addition. Both registers 16 and 17 are controlled by an adding frequency controlling circuit 18 and add twice the product of a coefficient RcosW and the delay data to obtain the same result as the sum of a coefficient 2RcosW and the delay data. This result is fed to an output holding register 24 as well as to a delay data register 19 and then multiplied by the coefficient read out of a storage device 20 through a multiplier 22 to be held at a register 23 which holds the result of multiplication.

Description

[Detailed description of the invention] The present invention relates to digital filters.

With advances in LSI technology, it has become possible to process digital signals in real time with small devices. Digital filters are widely used in this field, and among them, all-pole digital fist filters are used in speech synthesis and the like. The transfer function of an all-pole digital filter is H
(Z) and shown in Z transformation representation, it is expressed as . Among these all-pole digital filters, there is a band-pass digital filter having frequency characteristics as shown in FIG. This digital filter has Z = Rt″″.

(2) It is a full-length digital filter with a pole at , where W is called the resonant frequency and R is called the passband width. The transfer function of this digital filter is given by )(B(Z). Still, this digital filter is
It has the configuration shown in the figure. When considering the stability of this digital filter, the convergence condition for the transfer function HB(Z) is that the pole shown by equation (2) exists within the unit circle on the Z plane, and the characteristics of this digital filter are This is a condition that guarantees stability. Since the pole exists in the unit circle, 1Zl=lR-t''JW1<1...(4) can be said. Also, it is clear that I tthJWI <I...
・・・・・・(5) Therefore IKI ・・・・・・(6)
I can say that. Now, when actually using a digital filter as shown in FIG. 2, binary decimal numbers expressed as signed two's complement numbers are used to simplify the hardware configuration. In this case, when representing an 8-bit value, for example, a decimal point follows the sign bit (in this case, it is 1, so it is negative), and the value is determined from the next digit pit, such as 1.0110100. The range of values given in such a display is 100000
00 to 01111111. On the other hand, the biggest advantage of using a digital filter is that the characteristics of the filter can be changed by changing the values of the coefficients (in the case of Figure 2, 2□□□W and 1⇠2). With advances in software technology, this is possible in real time.

An example of hardware for realizing the digital filter of FIG. 2 is shown in FIG. The input of the digital filter is given from the input register 1, and the output of the input register 1 is input to the switching circuit 2 together with the output of the register 5 which holds the addition result.

The switching circuit 2 switches between the output of the input register 1 and the output of the addition result holding register 5, which are input to the full adder 3.

Another input of the full adder 3 is the output of a multiplication result holding register 10 that holds the multiplication result of the coefficient and delay data. The output of the full adder 3 is sent to a register 4 that holds the addition result.
is input.

The value held in register 4 is shifted to addition result holding register 5. The output of the addition result holding register 5 is input to the delay data register 6 and simultaneously enters the output holding register 11. The value of the coefficient is read from the storage device 7,
After being held in the coefficient holding register 8, it is input to the multiplier 9 together with the output of the delayed data register 6, and the multiplication result of the coefficient and the delayed data is held in the register 1o.

The operation of this circuit will be explained according to the timing chart of FIG. Now, as the input of the digital filter, a
Considering the relation 01alla21a3..., the value after passing through one delay circuit in FIG. 2 is multiplied by a coefficient of d. , dl..., the value after passing through the same two delay circuits multiplied by β0. Let β1 be... Now, it is assumed that all registers other than input register 1 are reset to O before input is input to this digital filter. The input of the digital filter is input register 1 to pa. ,
al, a2. It is given as a3... The output of the switching circuit 2 is a. The output of the input register 1 and the output of the addition result holding register 5 are switched at 1/2 period of the shifting period of the input register 1, as shown in +aQ+al,al,aj+aoβo10a2... It is input to the full adder 3. Another input of the full adder 3 is the output of the multiplication result holding register 10 that holds the multiplication result.The addition result is held in the register 4 at the same timing as the switching cycle of the switching circuit 2, and the contents of the register 4 are It is shifted to the addition result holding register 5 at a timing with a 1/2 cycle delay, and the addition result holding register 5
The output of is 0+aO+aO+al+aOα0+al+aO
It changes as β0+a 2-. The output is transferred to the delayed data register 6 at the same timing as the data output cycle of the input register 1. The coefficients are read out from the storage device 7 at the same timing as the switching cycle of the switching circuit 2 and held in the coefficient holding register 8. Delay data register 6
The output of the coefficient holding register 8 is multiplied by the multiplier 9, and the result is held in the multiplication result holding register 10 at the timing shown in FIG. The output of the addition result holding register 5 is shifted to the delay data register 6 and simultaneously transferred to the output holding register 11. By repeating this operation, the input is filtered. By the way (3)
Equation and (6) equation 6-0≦+2B, part W1≦21 RK2...
...(7) 0< l-R, 21=IR21<1
. . . Since (8) holds true, there is a possibility that 2RcosW, which is a coefficient of the digital filter, takes a value of 1 or more but less than 2. Now, in this system, there is a decimal point after the sign bit, and we are considering numerical values starting from the next bit, but we can only handle absolute values less than 1. In order to incorporate a value of 1 or more but less than 2, for example, 0
It is necessary to consider cases such as 1.010110, where the 1's bit is blank next to the sign bit (in this case O, so it is positive), and the bits after the next digit are numbers below the decimal point.

Therefore, the digital filter with the configuration shown in Figure 3 has a value of 1.0.
It is possible that two types of data must be provided: data such as 110100 and data such as 01.010110. It is not desirable to handle data of different types with different decimal point positions because this greatly increases the number of control circuits required. It is still possible to unify the data to a type like 01.010110, but then
This is also undesirable because the number of significant digits for data less than 1 is reduced by one digit.

In order to eliminate the above-mentioned drawbacks, the present invention provides a circuit that realizes a digital filter that can handle all data less than 1 in arithmetic processing.

The digital filter according to the present invention includes a full adder that adds the product of the digital filter coefficient and data and the output of the addition result holding register, an addition result correction circuit that corrects the output of the full adder, and an addition result correction circuit. a register that holds the output of the register, an addition result holding register that shifts and holds the output of this register, means for inputting the output of the addition result holding register as an input to the full adder, and an addition count control that controls the addition result holding register. It is characterized by having a circuit.

An embodiment of the present invention will be described below with reference to FIG. Fifth
In the figure, an input register 12 provides an input, and its output enters a switching circuit 13 and is switched with the output of a register 17. The output of the switching circuit 1813 is added by the full adder 14 to the output of the register 23 that holds the product of the coefficient and the delayed data. The addition result enters the addition result correction circuit 15 and is corrected. In this addition result correction circuit, even if the absolute values of the two inputs of the full adder 14 are each less than 1, if the absolute value of their sum becomes 1 or more, the sign bit is inverted and the sign of the sum is changed. 1. It has the function of detecting the error of inversion and fixing the sum value to the largest value with the same sign as the addand and the summand and the absolute value less than 1. For example, in the case of 8-bit data, the maximum values are 01111111 and 100oooooo. This circuit is generally necessary when the sum of the addend and summand carries up, and when handling data in which the most significant digit used in this example is a sign bit and the next digit is a decimal point value. This circuit, which is not a special circuit only required, satisfies that the absolute value of the sum is less than 1. The corrected sum value is held in register 16 and further shifted to addition result holding register 17. A signal from the addition number control circuit 18 is input to the register 16 and the addition result holding register 17. This circuit 9- allows data with an absolute value of 1 or more and less than 2 to be treated as data in the same format as data with an absolute value of less than 1.

The output of the addition result holding register 17 is switched by the switching circuit 13 and enters the full adder 14, but the product of the coefficient 2RC00W, which is another input of the full adder 14, and the predicate data has an absolute value of 1 or more and less than 2. Therefore, the absolute value of the product of FLCOOW and the delayed data can be set to be less than 1 in the storage device 20, and the absolute value of both inputs of the full power ρ calculator 14 is less than 1. In this way, it is guaranteed that the absolute value of all data handled within this digital filter is less than 1. By the way, coefficient 2) 1・coo W
By adding the product of and the delayed data twice, the coefficient 2Rco
The same result as adding oW times the delayed data can be obtained. The addition number control circuit 18 is a side leg circuit that controls the register 16 and the addition result holding register 17 to add RcooW and the delay data corruption twice. 7
The output of the J11 arithmetic and holding register 17 is input to the delay data register 19 and simultaneously input to the output holding register 24 (10-). The coefficient read from the storage device 20 is held in the coefficient holding register 21, multiplied by the delay data that is the output of the delay data register 19 in the multiplier 22, and the product is held in the multiplication result holding register 23, and the total addition is performed. 140 inputs.

An example of the configuration of the addition number control circuit 18 is shown in FIG.

Signals 25 and 26 are clock signals that drive the shift registers 30 to 33, and the switching circuit 34 switches the output of the shift registers $31 and 33 according to the switching circuit control signal 27.

The output of the switching circuit 34 becomes the reset input of the 5-channel flip-flop 29, and the set input is the signal 28. S-R
The output of flip-flop 29 is clock pulse 25 and A
N1) Enters the gate 35 and its output becomes the adder circuit control signal.

FIG. 7 shows the operation of the addition number control circuit. The 8-flip 70 tube 29 is nipped by the set signal 28 and its output is shifted from the shift register 30 to the shift register 31 according to the clock signal 25,26. vJ
The switching circuit 34 carries the output of the shift register 31 by the switching circuit control signal 27 and the output of the shift register 31 when the shift control signal 27 is at low level. Immediately after the output of the D gate 35 goes high, the signal shifted to the shift register 31 by the clock signal 26 resets the Norinob flop 29 in S-1. Until -h clip-flop is set, the increase number control signal is...
It doesn't have to be VC. The output of the S-R flip-flop set at 9 o'clock is selected as the output of the shift register 33 is selected. During this time, the addition number control signal becomes 2 times as shown in FIG. When 27 is low level, the addition number control signal is 1 time]
・When the switching circuit control signal 27 is at the level No. 1, the arithmetic number control signal Ig becomes high twice. Such a 71p calculation number control signal is transmitted to the switching circuit 13 and the register 1.
6. Controls the addition result holding register 17, and when the second addition count control signal is high, the addition result holding register 17
By using the output of the multiplication result holding register 23 as an input to the full adder 140 via the switching circuit 13 and adding the output of the multiplication result holding register 23 again, a value twice the value held in the multiplication result holding register 23 is added. becomes possible.

FIG. 8 shows a block diagram of another embodiment of the present invention in which the digital number filters of FIG. 2 are connected in series. The signal is inputted from the input register 36 to the switching circuit 37 via the bus 41, and is then switched to the bus 49 and inputted to the data shift register 38. The output of the data shift register 38 is transferred to the switching circuit 37 via the bus 41.
is input to the multiplication 43. The coefficients of the digital filter read from the storage device 52 are input from the bus 49 through the switching circuit 39 to the coefficient shift register 40, and the output of the coefficient shift register 40 is multiplied by the switching circuit 39 via the bus 42. 13- becomes the input of the device 43. The delay data register 19 in FIG. 5 is replaced with a data shift register 38, and the coefficient holding register 23 is replaced with a coefficient shift register 40, and the number of stages of the two shift registers is Determined by the number of stages of digital filters connected in series. Data shift register, z38. ! :The output of the multiplier 43 which received the input from the coefficient shift register 40 is held in the multiplication result holding register 44, and the output is sent to the full adder 4.
5 along with the output of the addition result holding register 48.

The output of the total adder 45 is corrected by the n* result correction circuit 46 and held in the register 47. The output of the register 47 is shifted to the addition result holding register 48, which is controlled by the addition number control circuit 50. The output of the addition result holding register 48 is inputted via the bus 49 to the I/O unit 45, the output holding register 51, and the switching circuits 37 and 39. Digital according to the present invention
In the filter, the coefficient of the digital filter is halved and stored in the storage device, and the product of the coefficient and the delayed data is added twice using the addition number control circuit.
It is also possible to adopt a configuration in which the product of the coefficient of 1/n and the delayed data is added n times using the addition number control circuit. Furthermore, in this embodiment, the format of the data processed in the digital filter was considered as a sign bit in the highest digit and a binary decimal number from the next digit, but this does not impose any limitations on the present invention. It's not something to add.

As described above, according to the present invention, by having a circuit that limits the number of additions, it is possible to obtain a digital filter that can process data in a single data format with a small increase in hardware. .

[Brief explanation of the drawing]

Figure 1 is a diagram showing an example of the frequency characteristics and width of a full-square digital filter, Figure 2 is a block diagram of the digital filter, and Figure 3 is a digital filter? FIG. 4 is a timing chart explaining the operation of the digital filter; FIG. 5 is a diagram showing an embodiment of the present invention; FIG. FIG. 2 is a timing chart for explaining. FIG. 8 is a block diagram showing an embodiment of the (i-port) of the present invention. 1.12.36... Input register, 2, 13,
37.39...Switching circuit, 3,14.45...
... Full adder, 15.46 ... Addition result correction circuit, 4, 16.47 ... Register, 5.1
7.48... Well result holding register, 18.5
0... Addition number control circuit, 6.19...
・Delay data register, 7, 20.52...Storage device, 8, 2]...Coefficient holding register, 9,
22,43...Su device, 10,23°44...
...Multiplication result holding register, 11, 24.51...
...Output holding register, 25, 26...Clock signal, 27...Switching circuit control 'i+11
Signal, 28...Sect signal, 29...
5-) L flip-flop, 30, 31, 32° 33.
...Shift register, 34...Switching circuit, 35...AND gate, 38...
Data shift register, 40...1 series shift register, 41° Fig. 1 Fig. 2 Fig. 3 Fig. 5 Fig. 6

Claims (1)

[Claims] A full power nn unit that calculates the product of the digital filter coefficient and data and the output of the addition result holding register by 7JD, an addition result correction circuit that corrects the output of the full adder, and a register that holds the output of the addition result correction circuit. , an addition result holding register for shifting and holding the output of this register, and means for inputting the output of the addition result holding register as an input to a full adder;
A digital filter characterized by having an addition count control circuit that controls an addition result holding register.