JPS61179678A - Signal processing system - Google Patents

Abstract

PURPOSE:To detect the average level of a video signal with the minimum delay by digitizing a video signal, integrating the result over a prescribed period and obtaining a mean level of the video signal with the said integrated value thereby allowing the level of the video signal to follow up sufficiently the mean level even if it changes rapidly. CONSTITUTION:A pulse (r) of a digital integration device 20 is generated at each time just before the net horizontal scanning is started during the vertical blanking period. An integration value (bd) appearing at the output of the digital integration device 20 is the result of integration of digital video signals (ad) in a field just before the relevant field. The integration value (bd) has a means value of the video signal (a) with a delay of one field as its information. Even if the lightness of an object is changed rapidly at a time t03, the abnormity in a digital video signal (dd) undergoing flair correction is caused in one field period only from the time t03 to a time t04, thereby suppressing the abnormity period to the minimum value.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a video signal correction method, and more particularly to a signal processing method for correcting unnecessary components occurring in a video signal in relation to the average value of the video signal. .

[Prior art and its problems]

Video signals obtained from video equipment such as video fist cameras require various types of processing such as correction.

To explain this using Fig. 2, this Fig. 2 shows a so-called three-tube color video camera.
R (red), G by Y lens 2 and color separation prism 3
(Green) and B (Blue), each colorant is imaged in the camera tubes 4-R, 4-G, and 4-BK, and the preamplifier 5
-J It is designed to obtain signals corresponding to the subject images of each color from 5-G and 5-B, and if the subject 1 at this time is as shown in Fig. 3, the signals shown in Fig. 4 are obtained. A signal with a waveform like this will be obtained. In these figures 3 and 4,! 1 to j6 are the scanning lines, set 1,
represent return lines, respectively, from time t6 to t.

The return line! The period , becomes the so-called retrace period. Note that the image formed by these scanning lines j1 to j6 is called 1 field,
Normally, two fields χ are combined to form one image.
It is well known that the system is a so-called 2-field, 1-frame system.

The video signals thus obtained at the outputs of the preamplifiers 5-R, 5-G, and 5-B are processed by a correction circuit 6-)L that removes unnecessary signal components generated by the imaging optical system and corrects them to the correct signal state. , 6-G, 6-B,
After a predetermined correction process is performed, a luminance signal 0 color difference signal is created by an encoder, and is output as a color video signal of a predetermined standard system called NT8C, PAL, or SRCAM.

By the way, as mentioned above, in such video cameras, etc., correction circuits 6-R, 6-G, and 6-B are provided so that correction of the various types cannot be performed by kneading. One of the most common types of correction processing is correction processing that is performed based on the average value of a video signal, and one typical example of this is flare correction.

This flare is caused by the lens or prism during imaging.

This refers to development in which light is reflected on the surface of the image pickup tube, etc., and then enters the entire surface of the image pickup tube as diffused light, resulting in the dark areas (black areas) of the image becoming slightly darker (gray).

By the way, in order to perform this 7-rea stomach correction, it is sufficient to subtract the flare amount from the video signal including the 7-rea.

However, in order to do this, it is necessary to extract only the flare component from the video signal containing flare χ, but this is generally quite difficult because there must be a black part in the subject. be.

On the other hand, since this flare is caused by scattering of light in the optical system as described above, it has the property of occurring in proportion to the amount of incident light.

Therefore, as flare correction, a method has conventionally been used in which the flare component is estimated from the amount of incident light using a predetermined proportionality coefficient, making use of such properties of flare. That is, in this method, as shown in FIG.
K is input, and a signal representing the average value is extracted.

Then, input this signal by flare amount ratio output circuit 1,
A calculation is performed based on a predetermined proportionality coefficient determined in advance through experiments, etc., and the flare component C is output, and the subtracter 12
is used to subtract the flare component CV from the signal a, and output the video signal from which the flare has been removed to the dll terminal out.

By the way, as is clear from FIG. 5, such a flare correction circuit 6 includes a circuit 6a that generates a signal b'2 representing the average value from a video signal a including flare, and a circuit 6a that generates a signal b'2 representing the average value of the video signal a including flare, and a circuit 6a that performs signal processing using this signal bχ. Conventionally, a low-pass filter 10 has been used as this circuit 6a. An example of this low-pass filter 10 is shown in FIG.

However, when the low-pass filter 10 is used as described above, since the video signal a has a scanning line configuration in the step 5 shown in FIG.
A stable signal cannot be obtained unless the time constant of the integrating circuit consisting of 0a and capacitor 10b is set to be sufficiently longer than the field period of the video signal.

As a result, in a conventional correction circuit using such a low-pass filter, if the brightness of the subject suddenly changes, the video signal will remain abnormal for a long period of time, spanning several fields. The disadvantage was that it caused

This Ik: will be explained with reference to FIG.

FIG. 7 shows the level of each signal on the vertical axis, including the video signal 3 including flare, the flare component C/ contained in this video signal, the output b of the low-pass filter 10, and the corrected video signal 3. The signal dlil shows the current time to1.
Assume that the brightness of the subject suddenly decreases to a fraction of the original value.

Then, as a matter of course, the video signal a and the flare component C' decrease to a fraction of that at this time to1.

However, as mentioned above, the output signal requires a time constant that spans several fields in the low-pass filter 10, so it does not immediately follow the change in the video signal a at time to1, but at time to1 several fields later. , the video signal a (the corresponding value will be reached).

On the other hand, as described above, the flare amount calculation circuit 11 calculates [flare component C1k] based on the output signal, so the flare amount calculation circuit 11 calculates the flare component C1k at time t. 1 to t(, 2), but when it does not follow the video signal a, this flare component C no longer corresponds accurately to the flare component C', and therefore the video signal d that is output does not follow the video signal a at the time. During the period from t01 to t02,
When an abnormality occurs, the flare component C, which is higher than the level actually present in the video signal a, is subtracted and the image is canceled out. It happens.

[Invention σ] Purpose] An object of the present invention is to eliminate the drawbacks of the prior art described above, to be able to sufficiently follow even if the average level of a video signal changes rapidly, and to minimize the delay. A signal processing method that can detect the average level of the video signal and always correct the video signal correctly? It is on offer.

[Summary of the invention]

In order to achieve this object, the present invention is characterized in that the video signal χ is digitized and integrated over a predetermined period, and the average level of the video signal is determined from the integrated value 1c.

[Embodiments of the invention]

The signal processing method according to the present invention will be described in detail below using the illustrated embodiment.

FIG. 1 shows an embodiment of the present invention, in which 19 is an analog-to-digital converter (referred to as A/D), 20 is a digital integrator, 21 is a digital flare value calculation circuit, 22 is a digital subtracter, and others. is the same as in FIG.

The A/D 19 functions to convert the video signal at containing flare to the digital video signal ad with a predetermined number of bits at a predetermined sampling rate. The frequency must be at least twice the highest frequency component of the
Further, as the number of bits, for example, 8 bits is used.

The digital integrator 20 has an integration function for input digital video signals ad and a buffer function for holding the integration results, and each time a pulse r is applied to the terminal p, it outputs the integrated value wlRrs that has been integrated up to that point. It is held in the buffer function (and the integration function is reset, and when the pulse r is turned off, it starts integrating the signal ad again, thereby outputting the integrated value bd of the video signal ad for each predetermined period. The pulse rK will be described later.

Based on the integrated value bd, the digital flare value calculation circuit 21 outputs a digital fist flare value Cd1 having a predetermined proportional relationship with respect to the integrated value bd.

The digital subtracter 22 subtracts the digital flare value cd from the digital video signal ad and outputs the flare-corrected digital video signal to the ddy terminal out.

Next, I will explain the operation of this embodiment! This will be explained using the time chart shown in FIG.

Now, if the pulse rt to the digital integrator 20 is generated immediately before the start of the next horizontal scan during the vertical retrace period as shown in FIG.
The integrated value bd appearing in the output of is the integrated result of the digital video signal ad in the field immediately before that field.

Therefore, this integration result is the average value (proportional value) of the digital video signal ad, so in the end, this integration value bd has as information the average value of the video signal a delayed by one field. It turns out.

Therefore, according to this embodiment (according to this example), even if the brightness of the subject changes rapidly at time tea, the DigiMole video signal ddK error that has undergone flare correction occurs only at time to.
The period from s to '04 is only 1 field period, and therefore, the abnormal period can be minimized (suppressed).

Incidentally, in recent years, digital video equipment has been increasingly used, but in this case, the digital video signal dd% obtained at the terminal OUT in the embodiment of FIG.
- You can use it as is, but in the case of an analog system like the conventional example shown in Figure 2, a digital-to-analog converter (called D/A) is not required after the terminal OUT in Figure 1. Needless to say.

By the way, according to the embodiment shown in FIG. 1, it is possible to suppress the abnormality that occurs in the video signal after the correction due to flare correction to one field period. Since the average value can be detected with a minimum delay and an accurate delay time, for example, with a delay time of exactly one field as in the embodiment shown in Fig. 1, this characteristic can be used to detect flare correction. It is also possible to completely eliminate the above-mentioned abnormalities that occur in the corrected video signal.

FIG. 9 shows an embodiment of the present invention that enables flare correction without causing any abnormality in the video signal.
Is it field memory etc? This is the video signal delay circuit used for one field period, and the rest is the same as the embodiment shown in Figure @1.

According to this embodiment, the video signal input to the digital subtracter 22 becomes a signal ad' delayed by one field period with respect to the digital video signal ad, so that the video signal of the nth field in FIG. The signal a is subtracted by the flare value cd extracted in the (n+1)th field, so that the video signal and the flare component for correction thereto can be of completely the same period, and therefore, Even if the brightness of the subject suddenly changes, no abnormality will occur in the video signal after flare correction (and appropriate flare correction can always be performed).

Next, FIG. 10 shows a specific embodiment of the digital integrator 20, in which 26.27 is an FF (7 lip-flops), 28
is a clock oscillator, 29 is a digital adder, and 30 is an inverter.

A predetermined number of F'F'25 are provided in parallel corresponding to the maximum number of bits of the integrated value bd, and the output data a of the adder 29 is
! It functions to remember things.

The FFs 27 are provided in parallel in a number equal to the number of bits required to represent the maximum value of the integrated value bd, and function as a buffer that captures and holds the output data ad' of the adder 29 at a predetermined timing. do.

The clock oscillator 28 functions to generate a clock pulse C with a frequency equal to the sampling pulse of the A/D 19 (Figure 111 or Figure !9), or a frequency that is an integer fraction thereof.
"f"ru.

The digital adder 29 receives the digital video signal ad and the FF
The function of adding the data a and d' obtained from 26 during integration? do.

The inverter 30 functions to obtain the pulse r' by delaying the pulse r by a predetermined time.

Next, the operation of the integrator shown in FIG. 10 will be explained with reference to the time chart shown in FIG.

The FF 26 captures and stores the output ad'% of the adder 29 at the edge portion every time the clock pulse cj is generated. Further, the FF 27 is connected to the adder 29 every time the pulse r rises.
The output ad#w is captured and stored. Furthermore, when the pulse r' rises slightly after this pulse r, the FF 26 is reset.

Therefore, at time tos after entering the current field period, it is assumed that the digital video signal ad, which had been zero until then, becomes level X and continues until time toe. Then, the output a d of the adder 29
' increases at an increasing rate corresponding to this level X from time 'os to toe, and at time Ntos the signal ad
When the level of is null to zero, this output a d' also stops increasing. Next, when the level of the signal ad becomes y at time to7, the output ad' also increases at an increasing rate corresponding to the level y. Then, when the level of the signal ad becomes zero at time 'os, the increase in the output adI also stops.

- 10,000, When a pulse ``is generated in the vertical retrace period between each field of the video signal a, this pulse r is first supplied to the clock input of the FF 27, so this FF 27 generates one pulse immediately before entering each field. adder 2 in previous field
9's output ad'Y is newly taken in and held as a signal bd until the next field. In other words, in FIG. 11, in the field including times tos to tos, the value A of the signal a d' in the immediately previous field is held as the signal bd, and in the one field period after the time "os" It is held as a level B9 signal bd.

Therefore, according to the embodiment of FIG. 10, a predetermined number of F
By providing the FFI, it is possible to obtain the integrated value Y of the necessary number of bits, and the digital integrator 20 can be easily realized.

Next, FIG. 12 shows another embodiment of the digital integrator 20, in which the digital video signal ad has n bits. In the figure, 32.1 to 32#n are AND gates; ~34・n is a counter, 36・1 ~ 36・n
1 is a weighting circuit, 37 is a digital adder, and the rest is the same as the embodiment shown in FIG.

In this embodiment, each bit of the digital video signal ad is
Number of 0" or '1"? Counter 34 provided for each bit
・Count each independently from 1 to 34・n, and obtain these counting results? The integrated value is obtained by weighting each and then adding them.The digital video signal ad input to this circuit is first passed through an AND gate 3.
2.1 to 32.nK are respectively ANDed with clock cl. This is because even if level 1 appears consecutively, the successive times are used to separate the levels by Y in the chronological direction to enable counting. Next, each bit is inputted to the counters 34.1 to 34.n, and counting is performed for each period of the pulse r.

The integrated value of each bit counted in this way is weighted by x2 to x2n for each bit by circuits 36.1 to 36.n to become signals a d'el to a d'.n. . Then, these signals are added by an adder 37 to obtain an integrated output ad'.

The operation of each part when the signal ad+l shown in FIG. 11 is applied to this circuit will be explained with reference to the time chart of FIG. 13.

During the period from time 'If to t1□, the level of signal ad is XVc
Therefore, it is assumed that only the lower bit signal ad@1 becomes level 1. Then, only the counter 34a1 receives a pulse to the ck terminal during this period.
As shown in the figure, from time t1□ to time t1.2 in 5, the integrated value ad'a1 of the signal ad.1 increases with time. Since the signal ad is at the level OO) at time t<t>2 to '13, the signals admL to ad@n are all 0, and the counter 34-
The outputs of 1 to 34·n do not change. Time 113-t14
In this case, the bits at level l are the signal ad*n and the signal ad@l, and these are input to the ck terminal and are counted by the counter 34*n and the counter 34.1, and each integrated value ad'sn .

a d'·n increases as shown in the figure. And each of these integrated values a d'・n 4 a d・1 is 211−
Weighting is done by multiplying by 1 to 2 degrees, and
The adder 37 outputs the integrated value a d'.

Then, at time t15 * j16 K: is the pulse Xr
, pulse r' causes the FF 27 to check the integrated output ad' indicated by the value BY, and resets the counters 34.1 to 34.n, thereby completing a series of integrated operations. In addition, the integrated value B at this time is B=S,X2""+----・
・-+81X2'.

Next, a specific example of the flare value calculation circuit 21 will be described.

This flare value calculation circuit 21 outputs a digital flare value cdyl- which has a predetermined functional relationship with respect to the integrated value bd based on the integrated value bd. A multiplier 60't' is used, the flare occurrence rate mY is used as a multiplier, and the integrated value b is used as a multiplicand.
One possibility is to give dQ.

In another embodiment, a memory 64 as shown in FIG. 15 is used, and data to be stored in each address of the memory 64 is used. , correspond to the address value function,
Input the integrated value bd to the address terminal and connect the data terminal to 7.
Rare CD? You may also take it out.

According to the embodiment shown in FIG. 15, even in a special case where the relationship between the flare value and the amount of incident light is not linear, the functional relationship is set as a function f(bd) of the integrated value bd,
The table function created based on this can be easily handled by simply storing it in the t memory 64, and the range of application can be widened (
can do.

By the way, the present invention relates to a signal processing method related to the correction of a video signal.
The idea of doing this can be applied to many things other than flare correction, such as a mechanism called auto iris that keeps the video signal level constant despite changes in subject brightness. Then responsiveness,
Needless to say, a significant improvement can be obtained in terms of control accuracy and the like.

Furthermore, as mentioned above, when the present invention is applied to digital video signal processing equipment, especially A/D-
? Since there is no need to use D/AF, the cost increase can be reduced.

Also, is the average value of the video signal? The idea of the present invention of calculating by integrating video signals should theoretically be possible using an analog integrator, but in reality, it is difficult to realize this analog method for the reasons described below. .

That is, first, when using the analog method, a capacitor is required to hold the integrated level, but this capacitor inevitably has leakage, and therefore accurate integration cannot be obtained. Further, this capacitor must be discharged at each integration period, but this inevitably involves noise, increasing the risk of adverse effects such as changes in the DC level of the video signal.

Therefore, it is appropriate to adopt a digital system as in the present invention, which allows high stability and high precision to be maintained.

〔Effect of the invention〕

As explained above, according to the present invention, the average value of the video signal can be detected with a minimum and always accurately with a constant delay time, so that it is possible to correct the video signal without the drawbacks of the prior art. It can be performed stably and accurately, and with good response.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the signal processing method according to the present invention, FIG. 2 is a block diagram showing an example of a video camera, and FIGS. 3 and 4 show the relationship between signals due to the subject and scanning lines. 5 is a circuit diagram showing a conventional flare correction method, and FIG. 6 is a circuit diagram showing an example of a low-pass filter. Is Figure 7 the operation of the conventional example in Figure 5? The time chart shown in FIG. 8 is the operation of the embodiment shown in FIG. 1? The ninth factor is a circuit diagram showing another embodiment of the present invention, and the first factor is a time chart shown in FIG.
Figure 0 is a circuit diagram showing an example of a digital integrator, @1
Figure 1 is a time chart showing the operation of the embodiment in Figure 10).
FIG. 12 is a circuit diagram showing another embodiment of the digital integrator, FIG. 13 is a flowchart showing the operation of the embodiment of FIG. 12, and FIG. 14 is an explanatory diagram of an embodiment of the flare value calculation circuit. FIG. 15 is an explanatory diagram showing another embodiment of the flare value calculation circuit. 6... Flare correction circuit, 19... Analog-to-digital converter, 20... Digital integrator, 21... Digital flare value calculation circuit, 22 ...Digital adder. Figure 1 and Figure 2-B Figure 3 Figure 4 and 4 pulses m1IItot, t213 t415
t6/. Figure 5 Mutual/C/D Figure 6 Figure 7 txt, *=ノ Figure 8 Figure 9 Figure 1O Figure 1I Figure 73' tllt12tlJ//4t15t16 Figure 14 Figure 15

Claims (1)

[Claims] In a signal processing method in which a video signal is corrected by subtracting a correction signal generated according to an average value of the video signal, there is provided a means for digitizing the video signal, and a means for digitizing the digitized video signal every predetermined period. means for determining an integrated value of the video signal, and the average value of the video signal is obtained from the integrated value.