JPS62274425A - Adder with shifter - Google Patents

Abstract

PURPOSE:To eliminate an exclusive rounding adder, and to contrive the reduction of the time required for a rounding addition, by executing the rounding addition after the right shift, by using an adder having a usual carry input. CONSTITUTION:When an input data is inputted to a shifter 2 as input signals I1, I2...In, and also, a shift control 3 is inputted, the shifter 2 outputs data of H0, H1...Hn in accordance with a shift amount. This signal becomes one input of an adder, and H0 is inputted to the carry input CIN of the adder. Ji, J2...Jn being the input data of the other are inputted at the same time as H0, H1...Hn being outputs of the shifter, therefore, the adder 1 executes addition by H1, H2...Hn and J1, J2...Jn. In such case, if a value of H0 is '1', the simultaneous addition is executed as a carry input from the carry input CIN, and K1, K2...Kn are outputted as outputs.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an adder used in electronic computers, etc., and particularly relates to an adder with a shifter that simultaneously performs a digit alignment operation including a rounding operation between inputs and an addition operation. It comes out.

[Conventional technology]

FIG. 4 and FIG. 5 show an example of implementation using the conventional technology when using a fixed-point fish-shaped arithmetic unit. When adding two numbers with different decimal point positions, it is necessary to perform a shift operation to the left or right before adding them.

In the example shown in Figure 4, input data A is shifted to the left by 3 bits to match the decimal point position of input data B, and then addition is performed. , the result of addition of 1M bits per bit causes an overflow, and a correct result cannot be obtained. Therefore, it is necessary to align the decimal point by shifting to the right, and addition by shifting to the right is required as in the example of FIG. In this example, input data Ef is shifted to the right by 5 bits to match the decimal point position of input data A before addition is performed, so the addition result does not cause overflow. However, as in the example shown in FIG. 5, when shifting to the right, 5 bits of ALL "1" data lose digits, making it impossible to obtain accurate results. Therefore, it is necessary to ensure accuracy by rounding and adding the data of the most significant bit of this digit loss to the least significant bit after being shifted to the right.

[Problem that the invention seeks to solve]

Conventional adders of this type have disadvantages in that, when independently implementing the shift function, rounding addition function, and addition function, an increase in the amount of node hardware and a slight increase in processing time are caused. Further, if the rounding function and addition function are shared, the increase in hardware amount can be suppressed, but there is a drawback in that it causes a significant increase in processing time.

[Means for solving problems]

The present invention is an adder with a shifter that solves the conventional problems and reduces calculation time and eliminates the need for a rounding adder. The main requirement is to have a chic with a carry output consisting of a bit output, and the first input is the first data input of the first input data width and the carry input, and the second An adder having a second input that receives a second data input having an input data width, and a shifter connected to the first data input, the first input being subjected to arithmetic shifting by the shifter. the first input data,
In the case of a left shift and no shift, "0" data is used as a carry input, and in the case of a right shift, the most significant bit data with digit loss is used as a carry input. By performing the addition of the first input and the second input, a digit adjustment operation including a rounding operation between the first input and the 20th manual input and an addition operation are performed simultaneously. Examples will be described below based on the drawings.

〔Example〕

In FIG. 1, 1 is an adder with a carry input, 2 is a chic that outputs the most significant bit of digit loss when shifting to the right;
3 is shift control, 4 is calculation control, 111I2...
In is the input signal of the shifter, Jl, I2...1% is the other input of adder 1, Hl, HQ...H% is the output of the shifter and one input of adder 1, HQ is the input signal of adder 1. Most significant bit output from shifter 2 and adder 1
Carry input to K1. 2...Kn is adder 1
This is the output of Note that the bit positional relationship of these input/output data is as shown in FIG. 2.) The outer side of the subscript is the upper 6 bits, and the side of the subscript 1 is the lower bit.

This circuit operates as follows. The input data is the input signal 11. I2...Input to shifter 2 as In,
And when shift control 3 is input, shifter 2 shifts to shift k.
-1! ! -Vr l-il-/n U1M') ,-
Outputs 0・-M-t71 ghee J6. This signal is input to one input of the adder; for HO, it is input to the carry input (CIN) of the adder. On the other hand, the O input data Jl, I2...Js are the shifter outputs HO, Hl
...Since it is input at the same time as H%, adder 1 is inputted at the same time as H%.
l, HQ...Hn and Jl.

I2...Addition is made with 1%. At that time, if the HOO value is "1", simultaneous addition is performed as a carry input from the carry input (CCIN), and the output is K1. 2...
...Kst is output.

In addition, as shown in Figure 2, the most significant bit of the digit loss in shifter 2 is assumed to have a 1 bit input, and a 0 bit further down the order, and is input by AND in the same way as the bit shift of the pond.
Just configure it with an OR gate and create a carry output. In addition, when using a commercially available IC shifter, the data bit position on the input side and the data bit position on the output side are paired, and up to this i, the most Since the upper bits cannot be output, the least significant bit of the input/output is an empty bit, data 0 is input to the input, and the entire input/output data is shifted by 1 bit to the upper bit. By adding this to the adder's carry power, rounded addition can be similarly realized. I in this case
An example of how to use the C shifter is shown in FIG. 3 α, b along with an example of its original usage. 3.6 shows the original usage, and FIG. 3.6 shows the usage according to the present invention.

Although this embodiment has been explained in the case of a fixed-point fish-shaped arithmetic unit, it is similarly applicable to the case of a floating-point number.

〔Effect of the invention〕

As described above, the present invention uses an adder with a normal carry input for rounding addition after right shifting, so there is no need for a dedicated rounding adder, and this can be achieved by simply adding wiring for carry. This reduces the time required for rounding and addition.

[Brief explanation of drawings]

Figure 2 is the bit arrangement of input/output data, Figure 3 a and b are how to use the IC shifter, Figure 4 is an example of shifting data to the left and adding it, Figure 5 is shifting the data to the right and adding it. This is an example. 1...Adder with carry input, 2...Switcher with °carry output, 3...Shift control, 4...Arithmetic control patent applicant Nippon Telegraph and Telephone Corporation's representative patent attorney Hisashi Tamamushi Part 5 (2 people) Fig. 1 shows an embodiment of the adder with 77 data according to the present invention, K1.
K2. - Kn Output data Embodiment of the configuration of the shift tie calculation system of the present invention Figure 1 Bi-soto position (upper) n ・・・・・・・・・・・・
...321 (lower) input data:
In the mouth==-==-=]=13. n, 10 output Te"-
Ta J: Giant five ====] === 璽T fan 丙σ 工郎 input/output data bit array ELL is a diagram 2 Figure 3

Claims (1)

[Claims] A first input having a first data input and a carry input having a first input data width; and a second input having a second data input having a second input data width. an adder having an input, and a shifter connected to the first data input, the first input being: the first input data arithmetic shifted by the shifter; left shift and no shift; consists of a carry input in which "0" data is used as a carry input, and in the case of a right shift, the most significant bit data with digit loss is used as a carry input, and in the adder, the first input and the second input are An adder with a shifter, characterized in that by performing addition, a digit alignment operation including a rounding operation between the first input and the second input and an addition operation are performed simultaneously.