JPH0619700B2 - Arithmetic unit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an arithmetic device having a function of clamping an arithmetic result to a maximum value or a minimum value when an arithmetic result overflows.

[Technical background of the invention]

In an arithmetic unit used for conventional digital signal processing, when an arithmetic result overflows, the maximum value data or the minimum value data is written as a software process into a register that holds the arithmetic result of the arithmetic unit and clamped. The processing was realized.

[Problems of background technology]

For this reason, there is a problem in that software must be developed in consideration of the clamp processing, and there is a drawback that the processing load is imposed on the software and the processing speed is reduced. In particular, when a continuous operation instruction is executed, the number of registers for storing the operation result becomes plural, and the above drawbacks are increased.

[Object of the Invention]

The present invention has been made in view of the drawbacks of the conventional arithmetic device as described above, and an object thereof is to accurately execute a continuous arithmetic instruction that causes an overflow.
It is an object of the present invention to provide an arithmetic unit that has a small software load and can increase the processing speed.

[Outline of Invention]

Therefore, in the present invention, the first and second registers each storing n-bit (n is an integer) data are operated with the n-bit data, and the resulting n-bit data is output and the operation is performed. A clamp control signal is output when a result overflows, while a clock is applied to one of the first and second registers during execution of a concatenated operation instruction to control selection of a register for storing an operation result, and When an overflow occurs in the operation of the higher-order data, a flag is set to indicate the overflow, and the clamp control signal is used to output the output data of the main operation unit as it is, the maximum of n bits or A concatenation operation of the main control unit and a logic circuit that creates one of the minimum n-bit data and outputs it to the first and second registers. In response to the operation at the time of executing the command, when the flag is set, there is provided means for clamping the data of the register in which the lower data of the first and second registers is stored. Then, the arithmetic unit was constructed. Further, in the present invention, each is n (n is an integer)
First and second registers in which bit data is stored,
An n-bit data operation is performed, the resulting n-bit data is output, and a clamp control signal is output when an overflow occurs in the operation result, while the concatenation operation instruction is executed when the instruction is executed. A main arithmetic operation section for outputting a control signal as shown and for controlling selection of a register for storing a calculation result by applying a clock to one of the first and second registers; and the main arithmetic operation using the clamp control signal. The output data of the part as it is,
A logic circuit that creates one of n-bit maximum or minimum n-bit data and outputs the data to the first and second registers, a control signal indicating execution of a concatenation operation instruction, and the clamp control signal , 1-bit data obtained by controlling the most significant bit of the output of the main control unit using these control signals is sent to the register in which the lower data of the first and second registers is stored. The arithmetic unit is configured to include the third logic circuit that outputs the clock to the register on the higher side and outputs the clock to the register on the lower side.

Example of Invention

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In the figure, reference numeral 1 indicates a main calculation unit. The main operation section 1 is capable of calculating the 16-bit operation result of the data of the most significant bit output data of the code bits and the fixed-point arithmetic is performed with 16-bit result data the data lines 4 _1,
Output to 4 ₂ , 4 ₃ , ..., 4 ₁₆ . When an overflow occurs in the operation result, the main operation unit 1 outputs the maximum clamp control signal from the signal line 8 when the overflow occurs with positive data, and outputs the minimum clamp control signal when the overflow occurs with negative data. Output from line 9. Output data lines 4 ₁ , 4 ₂ , 4 ₃ from the main operation unit 1,
The data output to 4 ₁₆ is the AND gates 21 ₁ and 21
_It is given to ₂ , 21, ₃ , ..., 21 ₁₆ . In this embodiment, both the maximum clamp control signal and the minimum clamp control signal are
It is high active and is at low level when it does not overflow. Therefore, AND gate 21
_A high level signal is given to ₁ via the inverter 22 _1, and a high level signal is given to the AND gates 21 ₂ , 21 ₃ , ..., 21 ₁₆ via the inverter 22 ₂ , and the output data line The data output to 4 ₁ , 4 ₂ , 4 ₃ , ..., 4 ₁₆ is passed through the AND gates 21 ₁ , 21 ₂ , 21 ₃ , ..., 21 ₁₆ to the OR gates 23 ₁ , 23 ₂ , 23 ₃ , ……, given to 23 ₁₆ The minimum gate control signal is given to the OR gate 23 ₁ via the inverters 22 ₂ and 22 ₃ , and the OR gates 23 ₂ and 23 ₃ , ...
..., 23 ₁₆ is provided with the maximum clamp control signal.
The operation data output from the OR gates 23 ₁ , 23 ₂ , 23 ₃ , ..., 23 ₁₆ are calculated data lines 5 ₁ , 5 ₂ , 5 ₃ , ..., 5
_It is given to 16-bit register 2 or 16-bit register 3 via 16. Here, the main arithmetic unit 1 outputs a clock to one of the clock line 6 and the clock line 7 to control whether the register for storing the arithmetic data is the register 2 or the register 3.

The clamp processing by such an arithmetic device will be described. 16
In operation of the bit data, an overflow in the positive data occurs, since the main operating unit 1 is active up to clamp control signal, the OR gate 23 _2, 23 ₃ via a signal line 8, ..., 23 ₁₆ Is supplied with a high level signal, and the AND gate 21 ₁ is supplied with a low level signal via the inverter 22 ₁ . For this reason, AND Gate 21
Output of ₁ is prohibited, AND gate 23 ₁ has AND gate
A low-level signal is applied via the 21 ₁ and the inverter 22 ₁ . Therefore, from the OR gate 23 ₁ to the operation data line 5
₁ to the data is output in "0", the OR gate 23 _2, 2
From 3 ₃ , ..., 23 ₁₆ the calculation data lines 5 ₂ , 5 ₃ , ...,
Data of “1” is output to 5 ₁₆ . That is, the data clamped to "7FFF _H " which is the maximum positive value as all data is stored in the register 2 or the register 3 from the operation data lines 5 ₁ , 5 ₂ , 5 ₃ , ..., 5 _16. .

Further, in the operation of 16-bit data, an overflow occurs in the negative data, the main calculating portion 1 since the minimum clamp control signal active, via the signal line 9 and the inverter 22 _2, AND gate 21 _2, 21 ₃ , ……, 2
A low level signal is applied to 1 ₁₆ and a high level signal is applied to the AND gate 21 ₁ via the inverter 22 ₁ . Therefore, the outputs of the AND gates 21 ₂ , 21 ₃ , ..., 21 ₁₆ are prohibited, and the OR gates 23 ₂ , 23 ₃ , ..., 23 ₁₆ are given a low level signal by the maximum clamp control signal, and the operation data line 5 _2, 5 _3, ..., and outputs the data of "0" to 5 _16. Further, the OR gate 23 ₁ is an inverter 23 ₃
Since always receives a high level signal via the outputs data of "1" to the arithmetic data lines 5 _1. In other words, the data clamped to "8000 _H ", which is the minimum negative value for all data, is the calculation data lines 5 ₁ , 5 ₂ , 5 ₃ , ..., 5
_{From 16} is stored in register 2 or register 3.

Therefore, when overflow occurs in the 16-bit arithmetic range, the clamp processing is completely performed by hardware, the processing speed is increased, and the load of software can be reduced.

A case will be described in which, in this arithmetic unit, an arithmetic operation (concatenation arithmetic operation) is performed which becomes data of 32 bits which is double the 16 bits which can be operated by the main arithmetic unit 1 and an overflow occurs in the operation result. For example, when the register 3 is used as a lower data register, the data is already stored in the register 3 when the data to be stored in the register 2 is being calculated. Therefore, the clamp processing can be realized by hardware for the data of the register 2, but the data of the register 3 is processed by software. For example, an overflow flag is prepared in the main operation unit 1, and when an overflow occurs in the operation of 32-bit data, the flag is set and the data in the register 3 is clamped by software. As a result, a part of the clamp processing by hardware, which has not been conventionally performed, is incorporated, so that the processing speed can be increased and the software load can be reduced accordingly.

In the embodiment, the data of each bit is converted by the AND gate, the inverter and the OR gate so that the data of the operation result output from the main operation unit 1 becomes the data of the positive maximum value based on the maximum clamp control signal. Based on the first logic circuit that controls and outputs and the minimum clamp control signal, the data of each bit is controlled so that the data of the operation result output from the main operation unit 1 becomes the data of the negative minimum value. Although a logic circuit including the output second logic circuit is configured, it does not necessarily have to be based on this. For example, the same effect may be obtained by changing the configuration of each gate. Also, the data may be clamped to only one of the maximum and minimum data. That is, it is possible to use an arithmetic unit that handles only one of positive and negative data.

Next, another embodiment of the present invention will be described with reference to FIG. In the figure, the components designated by the same reference numerals as those in FIG. 1 are the same as those in FIG. The main arithmetic unit 1'is
In addition to the maximum clamp control signal and the minimum clamp control signal, when an ADD WITH CARRY (addition with carry) command is received, the ADD WITH CARRY control signal is output via signal line 10, and SUB WITH BORROW (subtraction with carry) ) When receiving the command, the SUB WITH BORROW control signal is output via the signal line 11. The ADD WITH CARRY control signal is applied to one input terminal of the OR gate 24 ₁ , and the SUB WITH BORROW control signal is applied to the other input terminal of the OR gate 24 ₁ . The OR gate 24 _2, maximum clamp control signal and the minimum clamp control signal is given, is applied to the AND gate 25 ₁ and the output of the OR gate 24 and _second output and the OR gate 24 _1. Signal the AND gate 25 ₁ is output to the signal line 12 is a new input clock control signal, during the execution results linking instructions carry with addition and subtraction (concatenation operation instruction), when an overflow occurs, the active ( high level)
Becomes This new input clock control signal is AND gate 25
₂ , given to the exclusive OR gate (hereinafter referred to as EX-OR gate) 26. To the AND gate 25 ₂ of the other input terminal, a clock line 6 'is given clock supplied to the register 2. The output of the AND gate 25 ₂ is given to one input terminal of the OR gate 24 ₃ and
4 clock is applied from the clock line 7 ₃ to the other input terminal. The output of OR gate 24 ₃ is clock line 1
It is given as a clock to register 3 via 3. That is, the register 3 is not only in the mode for receiving the data of the operation result from the main operation unit 1 as shown in FIG. 1, but also when the overflow occurs at the time of executing the concatenation instruction of the result of the carry addition / subtraction, the clock line 13 The clock is given via. In addition, the EX-OR gate 26, and a new input clock control signal described above, the output is given OR gate 23 _1. The output of the EX-OR gate 26 is given to the most significant bit of the register 3 as new input most significant bit data via the operation data line 14. New input the most significant bit data, if a new input clock control signal is inactive, but as it is the output of the OR gate 23 _1, if the new input clock control signal is active, positive overflow or negative data by the data It depends on the overflow. That is, at the overflow due to positive data, the output of the OR gate 23 ₁ is “0”, and therefore the data of “1” is output from the EX-OR gate 26.
At the overflow due to the negative data, the output of the OR gate 23 ₁ is "1", so that the EX-OR gate 26 outputs the data of "0".

The arithmetic operation of 16-bit data by this arithmetic unit is the same as in FIG. A case will be described in which a concatenation operation instruction (in this embodiment, an operation instruction that becomes 32-bit data) is executed in this arithmetic unit and an overflow occurs. Data has already been stored in the register 3.

Now, assuming that the ADD WITH CARRY instruction has been issued, the main operation unit 1 ′ outputs the ADD WITH CARRY control signal as active from the signal line 10. If an overflow occurs in the positive data, the main arithmetic unit 1'outputs the maximum clamp control signal to the signal line 8 as active. Then, via the signal line 8, the OR gate 23 ₂ , 2
A high level signal is applied to 3 ₃ , ..., 23 ₁₆ and a low level signal is applied to the AND gate 21 ₁ through the inverter 22 ₁ . Therefore, the output of the AND gate 21 ₁ is prohibited, and a low level signal is given to the OR gate 23 ₁ via the AND gate 21 ₁ and the inverter 22 ₃ .
Therefore, the data of “0” is output from the OR gate 23 ₁ to the operation data line 5 ₁ , and the OR gates 23 ₂ , 23 ₃ , ...
, 23 ₁₆ outputs data of "1" to the operation data lines 5 ₂ , 5 ₃ , ..., 5 ₁₆ . In other words, the data clamped to "7FFF _H ", which is the maximum positive value for all data, is transferred from the operation data lines 5 ₁ , 5 ₂ , 5 ₃ , ..., 5 ₁₆ to the register 2 by the clock on the clock line 6. Is stored. On the other hand, since both the ADD WITH CARRY control signal and the maximum clamp control signal are active, the AND gate 25 ₁
The new input clock control signal, which is the output of, becomes active. In addition, the EX-OR gate 26 has “0” from the OR gate 23 _1.
Is given, the output becomes the data of "1",
16-bit data of all "1" is input to the register 3 by the clock line 6 ', AND gate 25 ₂ , OR gate 24 ₃ ,
It is stored in synchronism with the clock applied via the clock line 13. Therefore, the registers 2 and 3 contain "7FF
F _H "," FFFF _H "is stored, so that the 32-bit data is stored is clamped.

Next, if the SUB WITH BORROW command was issued,
The main operation unit 1'outputs the SUB WITH BORROW control signal as active from the signal line 11. When the negative data overflows, the main arithmetic unit 1'activates the minimum clamp control signal. Therefore, the AND gates 21 ₂ , 21 ₃ , ... via the signal line 9 and the inverter 22 ₂ .
The low-level signal is given to 21 ₁₆ and AND gate
A high-level signal is given to 21 ₁ via an inverter 22 ₁ . Therefore, AND gate 21 ₂ , 21 ₃ , ……, 21 ₁₆
Is prohibited, and the OR gates 23 ₂ , 23 ₃ , ..., 23 ₁₆ are given a low level signal by the maximum clamp control signal, and "0" is input to the operation data lines 5 ₂ , 5 ₃ , ..., 5 ₁₆ . The data of is output. Further, the OR gate 23 ₁ is the inverter 2
Since always receives a high level signal through the 3 _3, and outputs the data of "1" to the arithmetic data lines 5 _1. That is,
The data clamped to "8000 _H ", which is the negative minimum value for all data, is the calculation data line 5 ₁ , 5 ₂ , 5 ₃ , ...,
From 5 ₁₆ it is stored in register 2 by the clock on clock line 6. On the other hand, since both the SUB WITH BORROW control signal and the minimum clamp control signal are active,
New input clock control signal which is the output of the AND gate 25 ₁ is active. Further, since the EX-OR gate 26 is supplied with "1" from the OR gate 23 ₁ , its output becomes data of "0" and all "0" is stored in the register 3.
16-bit data is stored in synchronism with the clock given through the clock line 6 ', the AND gate 25 ₂ , the OR gate 24 ₃ , and the clock line 13. Therefore, the register _{2,3, "8000 H", "} 0000 H" is stored, so that the 32-bit data is stored is clamped.

As described above, according to the present embodiment, not only the overflow in the 16-bit range but also the overflow in the 32-bit range is completely clamped by hardware, and the processing speed can be increased. It is possible to reduce the load on the software. Also, there is an advantage that the software of the arithmetic unit can be extremely easily developed because the clamp processing can be executed without using any software.

In the embodiment, the OR gates 24 ₁ , 24 ₂ , 24 ₃ , AND gates 25 ₁ , 25 ₂ , and EX-OR gate 26 form a third logic circuit, and the third logic circuit Data of each bit is controlled and output so that it becomes a part of the maximum or minimum data that can be represented when a concatenated operation instruction is executed, to the register that stores the data of the operation result. However, the third logic circuit may have any other structure as long as it has the above-described function.

Further, in FIGS. 1 and 2, the number of registers is two,
Although separate ones are used, the number of registers is not limited, and it is also possible to adopt a system in which a predetermined bit of data is divided and held in a series of registers.

〔The invention's effect〕

In the case of a concatenation operation instruction, the lower-order n-bit data is changed at the time of overflow of the upper-side n-bit data, so that accurate processing is possible, and at least the upper-side processing at the time of overflow Since it is performed by hardware called a logic circuit, the processing speed is increased and the load of software can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of another embodiment of the present invention. 1, 1 '... Main operation unit 2, 3 ... Registers 21 ₁ , 21 ₂ , 21 ₃ , ..., 21 ₁₆ , 25 ₁ , 25 ₂ ... AND gate 22 ₁ , 22 ₂ , 22 ₃ ... Inverter 23 ₁ , 23 ₂ , 23 ₃ , ..., 23 ₁₆ , 24 ₁ , 24 ₂ , 24 ₃ ... OR gate 26 ... EX-OR gate (22 ₁ , 22 ₂ , 22 ₃ , 21 ₁ , 21 ₂ , 21 ₃ , ......, 21 ₁₆ , 23 ₁ , 2
3 ₂ , 23 ₃ , ……, 23 ₁₆ ) …… Logic circuit (24 ₁ , 24 ₂ , 24 ₃ , 25 ₁ , 25 ₂ , 26) …… Third logic circuit

Claims (4)

[Claims] 1. A first register and a second register, each of which stores n (n is an integer) bit of data, and an operation of the n-bit data, and outputs the resulting n-bit data, and an operation. A clamp control signal is output when a result overflows, while a clock is applied to one of the first and second registers during execution of a concatenated operation instruction to control selection of a register for storing an operation result, and When an overflow occurs in the operation of the higher-order data, a flag is set to indicate the overflow, the clamp control signal is used, the output data of the main operation unit is unchanged, and the maximum of n bits or A logic circuit that creates one of the minimum n-bit data and outputs it to the first and second registers, and a concatenation operation instruction of the main control unit. In response to the operation at the time of execution, when the flag is set, there is provided means for clamping the data of the register in which the lower data of the first and second registers is stored. An arithmetic unit characterized by. 2. The main arithmetic unit outputs a maximum clamp control signal when the arithmetic result data overflows with positive data and a minimum clamp control signal which outputs when the overflow occurs with negative data. The logic circuit controls and outputs each bit data so that the data of the operation result output from the main operation unit based on the maximum clamp control signal becomes the data of the positive maximum value. 1 logic circuit, and a second logic for controlling and outputting data of each bit so that the data of the operation result output from the main operation unit based on the minimum clamp control signal becomes the data of the negative minimum value. An arithmetic unit according to claim (1), characterized in that it comprises a circuit. 3. A first register and a second register, each of which stores n (n is an integer) bit of data, and an operation of the n-bit data, and outputs the resulting n-bit data and the operation. When the result overflows, a clamp control signal is output, while a concatenated operation instruction is executed, a control signal indicating the execution of the instruction is output and a clock is given to one of the first and second registers. A main arithmetic unit that performs selection control of a register that stores the arithmetic result, and data that is the same as the output data of the main arithmetic unit and n-bit maximum or minimum n-bit data, using the clamp control signal. A logic circuit that creates one and outputs it to the first and second registers, a control signal indicating execution of a concatenated operation instruction, and the clamp control signal are received, and these controls are performed. 1-bit data obtained by controlling the most significant bit of the output of the main control unit using a signal is output to the register in which the lower data of the first and second registers is stored. And a third logic circuit for outputting a clock given to a register on the upper side to a register for storing data on the lower side. 4. The main operation unit outputs a maximum clamp control signal when the operation result data overflows with positive data and a minimum clamp control signal output when the overflow occurs with negative data. The logic circuit controls and outputs each bit data so that the data of the operation result output from the main operation unit based on the maximum clamp control signal becomes the data of the positive maximum value. 1 logic circuit, and a second logic for controlling and outputting data of each bit so that the data of the operation result output from the main operation unit based on the minimum clamp control signal becomes the data of the negative minimum value. An arithmetic unit according to claim (3), characterized in that it comprises a circuit.