JPH0573267A - Arithmetic processor - Google Patents

Abstract

PURPOSE:To round a value to the maximum or minimum one capable of expression within the range of the operation accuracy by providing a detection means detecting the overflow and underflow due to the operation result and a rounding processing means rounding the operation result after the overflow and the underflow processing. CONSTITUTION:A detection means 2 receives a signal from an operation means 1, judging a positive or negative overflow from the combination of the highest two bits. In the case of the expression of the complement 2, the positive overflow is judged when the highest two bits are '01', and the negative overflow is judged when '10'. The detection means 2 sends a signal to a rounding processing means 3 according to the detection result. The rounding processing means 3 sets the output value to the positive maximum value at the time of overflow and to the negative maximum value at the time of underflow. Thus, the color missing at the time of a video signal processing and the sound missing at the time of a voice signal processing can be prevented by resetting the operation result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvements in arithmetic processing units.

[0002]

2. Description of the Related Art In a conventional arithmetic processing unit, when an overflow or underflow occurs as a result of an operation, it is detected, but since it has no means for rounding the operation result, the operation is stopped at that time, It only outputs the information such as the overflow flag and does not compensate the output of the correct operation result.

[0003]

In the conventional arithmetic processing unit, for example, in an application field represented by real-time image processing, the processing cannot be stopped just because an overflow or an underflow occurs. .. Moreover, the user of the conventional arithmetic device needs to recognize whether or not overflow or underflow has occurred as a result of the arithmetic operation.

In order to obtain a correct calculation result, it is necessary to provide an external circuit externally or deal with it by software, which is a processing burden.

If appropriate processing is not performed, for example, the overflowed value is often output as a small value that is far from the maximum value. For image data, color skipping is performed, and for audio data, sound skipping is performed. Becomes

[0006]

In the present invention, there are provided detecting means for detecting overflows and underflows resulting from the operation, and rounding processing means for rounding the overflowed and underflowed operation results.

[0007]

The detecting means detects the overflow and the underflow by the operation result having the bit width necessary for detecting the overflow and the underflow, and when the overflow occurs, the maximum value that can be expressed by the number of output data bits is obtained. When an underflow occurs in the numerical value of, it can be rounded to the minimum numerical value that can be expressed by the rounding processing means.

[0008]

FIG. 1 is a block diagram of an embodiment of the present invention.

The calculation means 1 is a normal calculation means,
In the present invention, the most significant 1 bit is used for overflow determination in combination with the next bit. Therefore, when the arithmetic precision requires 12 bits, 1 bit is added to this and the sum is added. A 13-bit arithmetic means is used. Hereinafter, a rounding process at the time of overflow of an integer calculation result having a calculation precision of 12 bits will be described as an example.

The output of the computing means 1 is sent to a detecting means 2 and a rounding processing means 3 for detecting an overflow. The output of the detection means 2 is further sent to the rounding processing means 3.

The detecting means 2 receives the 13-bit signal from the computing means 1 and judges from the combination of the most significant 2 bits whether it is a positive overflow or a negative overflow.
In the case of the two's complement representation, it can be determined that the most significant two bits are "01" and the overflow is negative, and the overflow is negative. The detection means 2 sends a signal to the rounding processing means 3 according to the detection result.

When there is no positive or negative overflow, the rounding processing means 3 does not operate, and the calculation result of the calculating means 1 is output through the rounding processing means 3 as it is.

The rounding processing means 3 receives the signal from the detection means 2 and outputs a positive maximum value 0111 at the time of positive overflow.
The output value is set to 11111111 at the maximum negative value 100000000000000 at the time of negative overflow.

FIG. 2 shows an example of the logic circuit configuration of the positive and negative overflow detecting means 2 and the rounding processing means 3. The input unit 10 receives a 13-bit operation result DI from the operation means.
0 to DI12 are input. Positive or negative overflow is detected from the most significant 2 bits DI12 and DI11 in this signal, and 12-bit output signals DO0 to DO11 are obtained from the output section 21.

The most significant bit input DI12 is EXN
It is sent to the OR circuit 11 and the NOR circuit 12. EXN
The output of the OR circuit 11 is sent to the NOR circuit 12 and the inverter 18, and the output of the inverter 18 is the selector 20.
Is sent to the terminal S and the flag terminal 19.

The next highest input DI11 is EXNOR.
It is sent to the circuit 11. The output of the EXNOR circuit 11 is also sent to the NOR circuit 12 and further sent to the positive / negative maximum value generation unit 15 via the inverters 13 and 14.
The output of the inverter 14 becomes a signal of "1" when positive overflow, that is, when DI12 and DI11 are "01".

The output of the EXNOR circuit 11 becomes "0" at the time of positive or negative overflow. Therefore, at the time of positive or negative overflow, the signal of “1” is output from the flag terminal 19 connected to the inverter 18,
It can be displayed that the rounding processing means described later is operating.

The positive / negative maximum value generator 15 is composed of, for example, four EXOR3 circuits, and has the uppermost terminal A3.
Are connected to the input terminal 17 which supplies "1". The terminals A1 and A2 of the uppermost EXOR3 circuit and the terminals A1, A2 and A3 of the other EXOR3 circuits are connected to the input terminal 16 which gives "0".
The terminal B of each EXOR3 circuit is connected to the output of the inverter 14.

When "0" is input to the terminal B, each EXOR3 circuit outputs the inputs of the terminals A1, A2 and A3 as they are to the corresponding terminals Y1, Y2 and Y3. When "1" is input to the terminal B, the terminal A1,
The inputs of A2 and A3 are inverted and the corresponding terminals Y1,
Output to Y2 and Y3 respectively.

The respective terminals A1, A2 and A3 of the lower three EXOR3 circuits and the terminals A1 and A2 of the upper one EXOR3 circuit are given "0" from the input terminal 16 and the upper one terminal. A3 is given "1" from the input terminal 17 because it is 12-bit data 10000000.
This is because 0000 is given as a constant. This value is 1
It is the maximum negative value in 2-bit two's complement representation. When the output of the inverter 14 is “1”, 12 bits are inverted and the positive maximum value 0111111111111 is obtained, which is input to the selector 20.

Note that, instead of using four EXOR3 circuits, twelve EXOR circuits can be used.
That is, by connecting the output of the inverter 14 to one of the terminals of all 12 EXOR circuits and inputting "0" or "1" to each of the other terminals, 4
The output of "0" or "1" is obtained from the 12 output terminals corresponding to the terminals Y1, Y2 and Y3 of the EXOR3 circuits.

In the 2-input selector 20, the inputs DI0 to DI11 are input to the terminals B0 to B11 on the left side, and the positive and negative maximum value generator 1 is connected to the terminals A0 to A11 adjacent to them.
The respective terminals Y1, Y2 and Y3 of the EXOR3 circuit of No. 5 are sequentially connected. Further, since the output of the inverter 18 is also added to the terminal S of the selector 20, the terminal S
The data to be output to the output terminals Y0 to Y11 on the right side of the selector 20, depending on the potential applied to
It is selected from any of A11 or B0 to B11.

The configuration of each section is as described above, but these operate as follows.

The EXNOR circuit 11 and the NOR circuit 12 which constitute the positive and negative overflow detecting means process the signals of the inputs DI12 and DI11. 1 "is output, and when it is" 10 ", the inverter 14 outputs" 0 "because it is a negative overflow. Further, when it is “01” or “10”, the inverter 18 outputs “1” to the terminal S of the selector 20, and when it is neither, it outputs “0” to the terminal S of the selector 20.

The positive / negative maximum value generator 15 and the 2-input selector 20 constitute a rounding processing means.

The positive / negative maximum value generator 15 includes an inverter 14
When the output of is 0, the maximum negative value is 10000000
0000 is output. When the output of the inverter 14 is "1", since "1" is input to each terminal B of the EXOR3 circuit, the negative maximum value is logically inverted and the positive maximum value 011111111111 is output.

The 2-input selector 20 has a terminal S of "0".
Is input, the operation results DI0 to DI11 are selected and the lower 12 bits are output as they are. On the contrary, if "1" is input to the terminal S, it means that the overflow is positive or negative, so the above-mentioned positive maximum value or negative maximum value is selected, and the 12 output terminals of the output unit 21 It is output as 12-bit output signals DO0 to DO11.

The above is the circuit configuration in the case of the integer representation, but in the case of the floating point representation etc., the same function can be easily realized by only the overflow detecting means and the representation of the positive and negative maximum values being different.

[0029]

According to the present invention, since the operation result can be rounded to the maximum positive or negative value, the positive maximum value is detected when the positive overflow is detected, and the negative value is detected when the negative overflow is detected. By resetting the calculation result to the maximum value of, it is possible to avoid color skips during video signal processing and sound skips during audio signal processing.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is an example of a logic circuit of overflow detection means and rounding processing means of the present invention.

[Explanation of symbols]

 1 computing means 2 detecting means 3 rounding processing means 10 input section 11 EXNOR circuit 12 NOR circuit 13, 14, 18 inverter 15 positive / negative maximum value generating section 20 selector

Claims (1)

[Claims] 1. An arithmetic processing device comprising: detection means for detecting overflow and underflow resulting from arithmetic operations; and rounding processing means for rounding the arithmetic results of overflow and underflow.