JPH0764768A - Absolute value accumulator - Google Patents

Abstract

PURPOSE:To sufficiently shorten the time required for accumulation as the whole regardless of a large. number of negative values at the time of executing the accumulation of absolute values. CONSTITUTION:When inputted data 1 is a positive value, the accumulation processing is performed once in an adder 14 in the same manner as usual. When inputted data us a negative value, the value obtained by inverting all of bits, the accumulated value, and the carry are subjected to the addition processing once by the adder 14 having the normal constitution. The absolue value of the negative value is obtained by inversion of all of bits and addition of carry '1'. Consequently, the accumulation processing speed is fixed independently of the sign of the inputted value, and the operation is performed at a high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an absolute value cumulative addition device used in an arithmetic operation for cumulatively adding absolute values of input data and obtaining a result thereof.

[0002]

2. Description of the Related Art For example, in the field of image processing, when cumulatively adding the distances between a certain point in an image and several points in the vicinity thereof, the X and Y coordinates of each point are The absolute value of each difference is obtained, and cumulative addition is performed using an adder or the like. For this purpose an absolute value cumulative addition device is used. FIG. 2 shows a block diagram of a conventional absolute value cumulative addition device. This device is data 1
, A inverter 2 and an adder 4 for obtaining the complement of data 1, a code determination unit 5 for determining the sign of data 1, an adder 6 for performing cumulative addition, and a cumulative value storage unit 7. It

In a general computer, a numerical value is represented by a two's complement in order to handle a number with a sign. For such a numerical value, if it is a positive number, it is unchanged, and if it is a negative number, this value is logically inverted and “1” is set.
The absolute value is obtained by adding. The selector 2 shown in FIG. 2 accepts the data 1 having a positive value at one input terminal as it is, and in the case where the data 1 is negative, the inverter 3 logically inverts it and the adder 4 The addition of 1 "is received in the other terminal.

Which of the inputs of the selector 2 is selected depends on the output of the code determination section 5. Regarding the numerical value represented by 2's complement, for example, when the most significant bit is "0", it can be determined as a positive number, and when it is "1", it can be determined as a negative number. The sign determination unit 5 inputs such a determination result to the selector 2, directly accepts and outputs the data 1 in the case of a positive number, and accepts and outputs the output of the adder 4 in the case of a negative number. Take control.

The adder 6 receives the output of the selector 2 at the A terminal and receives the output of the cumulative value storage unit 7 at the B terminal. The cumulative value storage unit 7 is composed of a register that receives and holds the output of the adder 6. Therefore, for example, in the initial state, the content of the cumulative value storage unit 7 is “0”, and the value input to the A terminal of the adder 6 and the value “0” input to the B terminal are added to store the cumulative value. It is stored in the unit 7. After that, the accumulated value obtained last time is input to the B terminal, the absolute value of the value input this time is input to the A terminal, and this is added by the adder 6 and output. In this way, the cumulative value 8 of the absolute value of the data 1 is output from this circuit.

[0006]

The conventional absolute value cumulative addition device as described above has the following problems to be solved. In the device shown in FIG. 2, the input data 1
When is a positive number, the data 1 passes through the selector 2 and is immediately input to the adder 6 to execute the cumulative addition process. However, when the input data 1 is a negative number, the adder 4 once executes an arithmetic process for obtaining an absolute value. After that, the result is input to the adder 6 through the selector 2, and the cumulative addition processing is executed together with the output of the cumulative value storage unit 7.

In this way, one adder 6 processes positive numbers and two adders 4 process negative numbers.
Since 6 and 6 sequentially perform the addition process once, the addition process of a negative number takes nearly twice as long as the addition process of a positive number. Therefore, when the input data 1 includes many negative numbers, there is a problem that the time for obtaining the cumulative addition result becomes very long. Particularly in the case of image processing, when trying to cumulatively add the distances between one point in the image and a large number of points around it, the negative number to be input becomes approximately the same as the positive number, and Since the amount of data is huge,
The calculation processing time is very long and cannot be ignored.

The present invention has been made by paying attention to the above points, and when executing cumulative addition of absolute values, it is possible to sufficiently reduce the time required for cumulative addition as a whole even when there are many negative numbers. It is an object of the present invention to provide an absolute value cumulative addition device that can be used.

[0009]

SUMMARY OF THE INVENTION An absolute value cumulative addition device of the present invention sequentially receives data consisting of arbitrary integer values represented by two's complement, and cumulatively adds the absolute values of these data by an adder. A sign determining unit that determines whether the input data is positive or negative, and supplies a carry having a value of 1 to the adder when the input data is a negative number,
When the input data is a positive number, the data is sent to the adder as it is, and when the input data is a negative number, all bits constituting the data are inverted and sent to the adder, and the addition A cumulative value storage unit for storing the addition result output from the adder, wherein the adder receives the outputs of the logical inversion unit and the cumulative storage unit and a carry and adds them to obtain a new cumulative value. To do.

[0010]

In this device, when the input data is a positive number, the cumulative addition process is performed by the same operation as the conventional one. Further, when the input data position is a negative number, the adder having a normal configuration adds the value obtained by inverting all the bits, the accumulated value, and the carry at once. When all bits are inverted and carry "1" is added, a negative absolute value is obtained. Therefore, regardless of whether the input value is positive or negative, the cumulative addition processing speed becomes similar, and high-speed calculation becomes possible.

[0011]

The present invention will be described in detail below with reference to the embodiments shown in the drawings. FIG. 1 is a block diagram showing an embodiment of an absolute value cumulative addition device of the present invention. This apparatus executes a logical addition unit 11 that receives data 1, a code determination unit 12 that determines the code of the data 1, a carry generation unit 13 that generates a carry from the output of the code determination unit 12, and a cumulative addition process. It includes an adder 14 and a cumulative value storage unit 15.

Also in the apparatus of the present invention, the data used for this cumulative addition is an arbitrary integer value represented by 2's complement. The logic inverting section 11 is a circuit for performing an operation of outputting the input data 1 as it is when it is a positive number and inverting and outputting all the bits when it is a negative number. The logic inversion unit 11 is configured to receive the output of the sign determination unit 12 and switch the processing when a positive number is input and when a negative number is input. The details will be described later with reference to FIG.

The sign judging section 12 is composed of a circuit for judging whether the input data is positive or negative, and for example outputting "0" when the input data is positive and outputting "1" when the input data is negative. . A specific example of this circuit configuration will be described later with reference to FIG. The carry generation unit 13 is configured by a circuit that receives the output of the code determination unit 12 and outputs a carry to the adder 14. This is composed of, for example, a 1-bit register that receives the output of the sign determination unit 12 and holds the value during the operation of the adder 14.

The adder 14 has the same structure as that used in the conventional apparatus, and has a structure in which the numerical values input to the A terminal and the B terminal are added and output to the Y terminal. In addition,
When the carry is input, the adder 14 performs an operation of adding "1" to the least significant bit. That is, the carry is accepted as a carry signal of the lower adder, and the process of adding "1" to the least significant bit is executed at the same time as the adding process. This function is the same as that provided in the conventional adder.

The cumulative value storage unit 15 is composed of a register or the like that receives and holds the output of the adder 14. With the above configuration, when new data 1 is successively input to this circuit, the cumulative value 8 is obtained.
It should be noted that by the operation of the adder 14, the adder 1
4 has the effect of apparently adding the data input to the A terminal and the data input to the B terminal and simultaneously adding "1" to the data.

FIG. 3 shows a wiring diagram of a concrete example of the apparatus of the present invention. The operation of the device of the present invention will be described in more detail with reference to specific wiring diagrams. In this embodiment, the input data is 2
It is an integer represented by the complement of and has a data width of 8 bits. The data represented by these 8 bits is
From "-128" of "10000000" to "11111"
Negative numbers up to "-1" of "111" and "0000000"
An integer from "0" to "127" of "01111111" can be represented.

In the case of data represented by 2's complement as described above, the most significant bit thereof is a code representing the sign of the data. That is, when the most significant bit is "0", it is positive, and when it is "1", it is negative. In this figure, IN
[7: 0] indicates all 8-bit data, and IN [7]
It indicates the most significant bit of the data.

In this embodiment, a logical inversion circuit 21 that receives all bits of input data and an adder 1 that receives 8-bit data on the output side and performs cumulative addition processing.
4 and a cumulative value holding register 25 that receives and holds the 8-bit data output from the adder 14. The output of the logic inverting circuit 21 is input to the A terminal of the adder 14, and the output of the cumulative value holding register 25 is B of the adder 14.
It is configured to input to the terminal. Further, the most significant bit IN [7] of the input data is directly input as the carry of the adder 14.

That is, in this embodiment, since the most significant bit of the input data is used as it is to control the logic inverting circuit 21 and is used as the carry of the adder 14, the circuit for code judgment and carry generation. No element is provided. That is, the line for inputting a part of the input data to the adder 14 directly functions as the code determination unit and the carry generation unit. In addition, the logic inversion circuit 21
The signal to be input from the sign determination unit to the logical inversion circuit 21
It is configured to branch inside.

FIG. 4 shows a concrete block diagram of such a logic inverting circuit. As shown, this circuit has 8
20 exclusive or gates 20
-0 to 20-7 are provided. Here, each bit of the input data is separated into pieces, and the lower 7 bits are exclusive OR gates 20-0 to 20-20.
Each of them is input to -6 and the upper bit IN [7] is input to the other input terminals of all the exclusive OR gates 20-0 to 20-7. Exclusive OR gate 20-7 that accepts the most significant bit
Has a configuration in which the most significant bit IN [7] is input to both input terminals.

The operation of the exclusive OR gate as described above is well known in the prior art. When the most significant bit IN [7] input as a control signal is "0",
The 8-bit signal input to the other terminal is taken out as it is, and when the control signal is "1", all the input signals are logically inverted and output.

On the other hand, when carry is input to the adder 14, "1" is added to the least significant bit of the addition result, as described above. Therefore, in the device of the present invention, when the input data of the adder 14 is positive, the signal input to the A terminal and the signal input to the B terminal are added as they are to obtain a cumulative value. On the other hand, when the input data is a negative number, all bits of that number are logically inverted and the carry value is added to the least significant bit to obtain its absolute value and the accumulated value input to the B terminal. The addition processing with the value is executed at the same time.

Therefore, substantially similarly to the conventional apparatus shown in FIG. 2, even in the case of a negative number, the absolute value thereof is obtained and the cumulative addition process is performed. Moreover, in the apparatus of the present invention, such processing is simultaneously executed by one adder 14, so that even if a negative number is input, cumulative addition processing is performed in the same time as when a positive number is input. Be done.

FIG. 5 shows a concrete operation explanatory view of the apparatus of the present invention. The figure shows the output of the result obtained by performing the cumulative value addition processing of the data successively input to the circuit shown in FIG. 3 between times T1 and T7. In the horizontal direction of this figure,
It shows the input data, the output of the logical inversion circuit, the accumulated value up to the previous time stored in the accumulated value holding register 25, the contents of the carry, and the output of the adder 14. In addition,
In this table, in addition to 8-bit binary numbers, enclose in () and
It also displays the expression in decimal notation.

First, at time T1, when decimal data with a value of "1" is input, since this value is a positive value, it passes through the logic inverting circuit 21 as it is and is input to the adder 14. Since this cumulative processing is the first time, the content of the cumulative value holding register 25 is "0". Further, since the input data is positive, the carry is "0". Therefore, the adder 14 adds the input value "1" and the accumulated value "0" to obtain an output "1".

At the next time T2, data of a decimal number of -5 is input. Since the input data is a negative value,
All input data is inverted and output from the logic inversion circuit 21. Therefore, if the value is converted into a decimal number, it becomes "4". The previous cumulative result stored in the cumulative value holding register 25 is “1”. Further, since the input data is a negative number, the carry is "1". Adder 1
As for 4, the value of "4" is input to the A terminal and the value of "1" is input to the B terminal. As a result, the addition result of the adder 14 is "5", but since the carry is "1" and this is added to the least significant bit, the result is "4", "1" and "1". The value "6" obtained by adding is obtained as an output.

This is equal to the sum of the absolute value of the data "-5" just input and the cumulative value "1". Time T3
Then, the value "-18" in decimal is input as data. Since this is a negative number, all the bits are inverted by the logic inverting circuit 21 and the value becomes "17" and is input to the adder 14. The accumulated value up to the previous time is "6", and since carry is input as "1", the output of the adder 14 becomes "24". Thereafter, similar processing is executed from time T4 to time T6. And at time T7,
The final accumulated value is obtained from the accumulated value holding register 25,
Output to external circuit.

The present invention is not limited to the above embodiments. In the above embodiment, the example in which the input data is 8 bits has been shown, but the number of bits may be arbitrary. In this case,
The configurations of the logic inverting circuit, the adder, the cumulative value holding register, and the like may be changed. Further, in the above embodiment, the most significant bit of the input data is directly used to determine the sign of the input data. However, for example, it is output by another arithmetic unit that processes the data before inputting to this circuit. A code flag or the like may be used. Further, the sign of the data may be determined by other well-known processing, the operation of the logic inverting unit may be controlled, or the carry may be input to the adder.

[0029]

As described above, the absolute value cumulative addition device of the present invention determines whether the input data is positive or negative when the absolute value of an arbitrary integer value represented by 2's complement is cumulatively added by the adder. Then, when the input data is a negative number, a sign determination unit that supplies a carry with a value of "1", and a logic determination unit that inverts all bits and sends the result to the adder when the value is negative, A cumulative value storage unit that stores the output result of the adder is provided, and in the adder, the output of the logical inversion unit and the output of the cumulative value storage unit receive the carry input from the positive / negative determination unit and perform addition processing. Therefore, a single adder can perform cumulative addition of absolute values for both positive and negative numbers at once. As a result, it is possible to increase the speed of this kind of arithmetic processing, and to speed up the overall arithmetic speed of the information processing apparatus such as image processing.

[Brief description of drawings]

FIG. 1 is a block diagram of an absolute value cumulative addition device of the present invention.

FIG. 2 is a block diagram of a conventional absolute value cumulative addition device.

FIG. 3 is a connection diagram of a specific example of the device of the present invention.

FIG. 4 is a wiring diagram of a logic inversion circuit.

FIG. 5 is a specific operation explanatory diagram of the apparatus of the present invention.

[Explanation of Codes] 1 Data 8 Cumulative Value 11 Logical Inversion Unit 12 Sign Judgment Unit 13 Carry Generation Unit 14 Adder 15 Cumulative Value Storage Unit

Claims (1)

[Claims] 1. A method of sequentially accepting data consisting of arbitrary integer values represented by two's complement and accumulating the absolute values of these data by an adder, determining whether the input data is positive or negative, and inputting If the input data is a negative number, a sign determination unit that supplies a carry with a value of 1 to the adder, and if the input data is a positive number, the data is sent to the adder as it is, and a negative number In the case of, a logical inversion unit that inverts all the bits that make up the data and sends it to the adder, and a cumulative value storage unit that stores the addition result output by the adder, the adder, An absolute value cumulative addition device, characterized in that the outputs of the logical inversion unit and the cumulative storage unit and the carry are received and added to obtain a new cumulative value.