JPH06259231A - Integral divider - Google Patents

Abstract

PURPOSE:To reduce the number of times of arithmetic to be repeated in the same cycle and to perform arithmetic at much higher speed by defining difference between a value, which is provided by shifting a dividend for 1 or 2 bits, and a divisor as the next dividend when the difference between this dividend and this divisor can not be calculated. CONSTITUTION:A shift means 3 outputs a dividend Rj, value Rj' provided by shifting this value for 1 bit, and value Tj'' provided by shifting this value for 2 bits. Adders 10a and 10b calculate Rj-D and Rj'-D from the respective values Rj and Rj' and the complementary of 2 of a divisor D. A selector 11a outputs either of them which enables arithmetic as a next dividend Rj. An adder 10c similarly calculates Rj''-D and when the arithmetic is disabled at the adders 10a and 10b, a selector 11b defines this Rj''-D as the next dividend Rj and outputs a partial remainder Rj+1 to a latch 8. The latch 8 latches the Rj+1 and a carry output and returns to the shift means 3. The following calculation is similarly performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an iterative integer type divider capable of high speed operation.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing the basic structure of a conventional iterative integer type divider. The dividend Rj or the partial remainder is supplied to one input terminal of the first adder 50a and the first selector 51a. The 2's complement of the divisor D is connected to the other input end of each of the first and second adders 50a and 50b. The addition output and the carry output of the first adder 50a are connected to the first selector 51a via a signal line 55a and a carry signal line 57a, respectively. The output terminal of the first selector 51a is the second adder 50.
It is connected to one input end of b. Second adder 50
The addition output and the carry output of b are connected to the second selector 51b via the signal line 55b and the carry signal line 57b, respectively. The addition result Rj + 1 of the cycle is output from the second selector 51b.

FIG. 5 is a block diagram showing a specific configuration of a conventional iterative integer type divider. FIG. 5 shows the configuration of only the data path unit excluding the control circuit of the repetitive integer type divider for the sake of simplicity. The operation of the integer divider of FIG. 5 will be described below. In the first cycle, the most significant bit of the dividend Rj is supplied to the signal line 66a, and in the subsequent cycles, the value obtained by shifting out the dividend from the most significant bit by 2 bits per cycle is the signal line 66.
is supplied to a. The two's complement of the divisor is supplied to the signal line 66b. In the first cycle, the first selector 71
a selects the most significant 1 bit of the dividend Rj of the signal line 66a and outputs it to the signal line 64a. First adder 70a
Is the most significant 1 bit of this signal line 64a and the signal line 66b.
And the two's complement of the divisor of. When the divisor D cannot be subtracted from the dividend or the partial remainder in the first adder 70a, the carry output is not output to the signal line 77a. In this case, the second selector 71b outputs the upper 2 bits of the dividend or the partial remainder supplied from the signal line 66b to the input signal line 76a of the second adder 70b. On the other hand, when the carry output is output to the signal line 77a, the output signal line 7
The addition result is output to 5a. In this case, the second selector 71b shifts this addition result by 1 bit, inserts the dividend Rj of the signal line 66b or the next higher 1 bit of the partial remainder into the least significant bit of this addition result, and 7
6a outputs to the second adder 70b. After this, the second
Of the signal line 76a from the selector 71b and the signal line 6
The 2's complement of the divisor of 6b is added by the second adder 70b. In the second adder 70b, when the carry output is not output to the signal line 77b, the output on the signal line 76a is selected by the third selector 71c and output to the signal line 76c. The latch 72 latches this addition result.
On the other hand, when the carry output is output to the signal line 77b, the third selector 71c selects the addition result of the output signal line 75b of the second adder 70b and outputs it to the signal line 76c.
In the second cycle, the first selector 71a operates the latch 7
The result of the addition of the first cycle from the second output signal line 78 is shifted by 1 bit, and the least significant bit is the next higher 1 bit of the dividend or partial remainder of the signal line 66a, that is, 3 bits lower than the most significant bit. A bit signal is inserted and output to the signal line 64a. After that, the same operation as the previous cycle is repeated until the division is completed. An example of operation when 8-bit operation is performed by the conventional iterative integer type divider of FIG. 5 is shown below. Dividend = 10010011 Divisor = 10010010 Two's complement of divisor = 01101110 Quotation = Q ADD0 ADD1 Q Carry 1 1st cycle 01101110 0 None 10 01101110 0 None 100 Second cycle 01101110 0 None 1001 01101110 0 None 10010 Third cycle 01101110 0 None 100100 01101110 0 None 1001001 4th cycle 01101110 0 None 10010011 01101110 1 Yes

As a result of the operation, carry is present and the quotient Q = 1 is obtained for the first time in the second adder 70b in the fourth cycle.
The quotient Q is 00000001 and the remainder is 1. When an operation is performed by this conventional integer type divider, four cycles are required until the operation is completed.

[0005]

When performing a multi-bit operation by a conventional iterative integer type divider, if the same cycle time (critical path of the same length) is used, a large number of cycles, that is, a large number of cycles. However, there is a problem in that it is impossible to perform high-speed calculation.

The present invention has been made in order to solve the above problems, and provides an iterative integer type divider which can reduce the number of repetitive operations at the same cycle time and can perform operations at higher speed. The purpose is to provide.

[0007]

In order to solve the above-mentioned problems, the present invention inputs a dividend, and based on the carry output obtained in the previous operation cycle, calculates the dividend at the same timing from a higher bit to a predetermined bit. Shifting means for shifting and outputting, inserting means for sequentially inserting the dividend in the lower bits of the dividend shifted by the shifting means from the upper bits in accordance with the number of bits to be shifted, and generating subtraction data; A plurality of subtracting means arranged in parallel according to the number of predetermined bits and subtracting the divisor for each bit from the subtraction data, and an arithmetic output of the subtracting means according to a carry output output from the plurality of subtracting means. Selecting means for selecting and outputting either of the subtraction data generated by the inserting means and the subtracting data generated by the inserting means; First holding means for sending this output to the shift means as the dividend of the cycle, second holding means for holding the carry output output from the plurality of subtraction means and sending it to the shift means, and the plurality of subtractions A detection means for detecting the completion of the required calculation cycle from the calculation output of the means.

[0008]

When the divisor D is subtracted from the dividend Rj, the divisor D is also subtracted from the value Rj 'obtained by shifting the dividend Rj by 1 bit at the same timing. In addition, a value Rj ″ obtained by shifting the dividend Rj by 2 bits is prepared. When the divisor D cannot be subtracted by the operation of Rj-D and the operation of Rj′-D can be performed, this operation result is Is used as the dividend Rj of R. If the calculation of Rj'-D is not possible, the value Rj "
Is used for the next operation. Therefore, when the operation of Rj-D is possible, the quotient Q is 2 bits in one cycle, while when the operation of Rj-D is not possible, the quotient Q is 3 bits in one cycle. As described above, in the present invention, a plurality of bits of the dividend are simultaneously calculated in the same calculation cycle.

[0009]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the basic configuration of an iterative integer type divider according to the present invention. An input terminal of the shift means 3 is connected to the dividend Rj, and an output terminal of the dividend Rj that is not shifted, a value Rj ′ obtained by shifting the dividend Rj by 1 bit, and a value Rj ″ obtained by shifting the dividend Rj by 2 bits is the first adder. One end of the (ADD0) 10a, one end of the second adder (ADD1) 10b, and the first selector 1
It is connected to 1a. The shift means 3 can actually output the dividend Rj up to a value obtained by shifting it by N bits at the same timing. First adder 10a and second adder 1
0b are arranged in parallel, and the addition output and the carry output are connected to the first selector 11a by the output lines 5a, 5b and the output lines 6a, 6b, respectively. The adder is actually N
Can be placed in parallel. The output terminal of the first selector 11a is connected to one input terminal of the third adder (ADD2) 10c and the second
Of the selector 11b. Third adder 10
The addition output and carry output of c are the second selector 11b.
It is connected to the. The two's complement of the divisor D is connected to the other input terminal of each of the first, second and third adders 10a, 10b and 10c. The partial remainder Rj + 1 is output from the second selector 11b to the latch 8. The latch 8 latches the partial remainder Rj + 1 and the carry output and then returns them to the shift means 3. The shift means 3 outputs a partial remainder Rj + 1, a value Rj + 1 ′ obtained by shifting the partial remainder Rj + 1 by 1 bit, and a value Rj + 1 ″ obtained by shifting the partial remainder Rj + 1 by 2 bits, and the same operation is performed thereafter. The timing signals supplied to the respective parts are not shown in FIG.

FIG. 2 is a block diagram showing the configuration of an embodiment of the repetitive integer type divider of the present invention. In this embodiment, N adders 20-1 ... 20-N are arranged in parallel in one stage. The first selector 21a, the first latch 22a, the (N + 1) -bit barrel shifter 23a, and the second
The shifter 23b corresponds to the shift means 3 in FIG. Second
The output of the shifter 23b is connected to one input terminal of the N adders, and the 2's complement of the divisor D is connected to the other input terminal of the N adders. 21b is a second selector, 22b is a second latch for latching the dividend,
22c is a third latch for latching a carry. N
The operation output of each adder is connected to the second selector 21b, and the carry output is connected to the second selector 21b and the third latch 22c. The barrel shifter 23a carries out a plurality of bits of digit movement at a time, and the shift amount is controlled by the carry output from the latch 22c. The dividend Rj is supplied to the first selector 21a, and the two's complement of the divisor D is supplied to one input terminal of each adder 20-1 ... 20-N.

Next, the operation of the iterative integer type divider shown in FIG. 2 will be briefly described. In the first cycle, the first selector 21a selects the signal of the dividend Rj from the upper bits and sends it to the first latch 22a. The first latch 22a latches this and then sends it to the barrel shifter 23a. The barrel shifter 23a receives the signal of the dividend Rj from the first latch 22a and shifts it according to the carry output from the third latch 22c, but since there is no carry output from the third latch 22c in the first cycle. The dividend Rj is output as it is without any shifting. Here, the signal output from the barrel shifter 23a to the signal line 19a is always the upper N + 1-bit value of the dividend (or partial remainder) signal. The output of the barrel shifter 23a is sent to the shifter 23a by the signal line 19a, and at the same time, returned to the first selector 21a by the signal line 19b and latched by the first latch 22a. In the first cycle, the second
Shifter 23b outputs the signal of the most significant bit to the first adder 20-1, and outputs the signal of the most significant bit and the signal of one bit lower to the second adder 20-2. The signal of the most significant bit to the signal of 2 bits lower is output to the adder 20-3 of No. 3, and similarly, the signal of the most significant bit to the signal of N bits lower is output to the Nth adder. Is output. The second shifter 23b is connected to the signal line 2
The dividend (or partial remainder) is also output to the second selector 21b via 4-N + 1. Each adder adds the signal from the second shifter 23b and the 2's complement signal of the divisor from the signal line 16b. The signal of the addition result of each adder is output to the second selector 21b. As a result of addition, if each adder has a carry output, each adder has its own signal line 2
It outputs to the 2nd selector 21b and the 3rd latch 22c by 7-1 ... 27-N. The third latch 22c latches the carry output and sends it to the barrel shifter 23a. The second selector 21b responds to the carry output signal of each adder by adding the signal of each addition result of each adder and the shifter 2 to each other.
Selection is performed for signals from the most significant bit to the N least significant bits of the dividend (or partial remainder) sent from 3b via the signal line 24-N + 1. That is, in the second selector 21b, when the carry is output from the first adder 20-1, the signal of the addition result of the first adder 20-1 is selected. When the carry is not output from the first adder 20-1 and the carry is output from the second adder 20-2, the signal of the addition result of the second adder 20-2 is selected. It When the carry is not output from the first adders 20-1 and 20-2 and the carry is output from the third adder 20-3, the addition result of the third adder 20-3 is The signal is selected.
First, second and third adders 20-1, 20-2 and 2
No carry is output from 0-3 and the fourth adder 2
When the carry is output from 0-4, the signal of the addition result of the fourth adder 20-4 is selected. Hereinafter, the same selection is performed by the second selector 21b according to the carry output.
Performed in. When no carry is output from any of the adders, the second selector 21b selects the signal from the most significant bit to the N least significant bit of the dividend (or partial remainder) from the shifter 23b. The second selector 21b sends the selected signal to the second latch 22a,
The second latch 22a latches this and shifter 23b
Send to.

In the next cycle, the barrel shifter 23a determines the shift amount of the dividend based on the carry signal received from the third latch 22c. For example, when the carry is not output from the first and second adders 20-1 and 20-2 and the carry is output from the third adder 20-3, the barrel shifter 23a operates as the first shifter. The dividend supplied from the latch 22a is shifted by 3 bits.
As a result, values from the most significant bit of the dividend to the least significant 4 bits to the least significant number of N + 4 bits are output from the barrel shifter 23a to the shifter 23b. When no carry is output from any of the adders in the previous cycle, the dividend supplied from the first latch 22a is shifted by N + 1 bits in the barrel shifter 23a. The value after the shift, that is, the partial remainder is sent from the barrel shifter 23a to the shifter 23b. The partial remainder after shifting output from the barrel shifter 23a is used for the calculation of the next cycle by the first selector 21.
It is latched by the first latch 22a via a. A value obtained by shifting the partial remainder from the second latch 22b by 1 bit and inserting the most significant bit of the output of the shifter 23b is input to the first adder 20-1. To the second adder 20-2, the value obtained by shifting the partial remainder from the second latch 22b by 2 bits and inserting the signal of the most significant bit and the one bit lower bit of the output of the shifter 23b is input. Similarly, the value obtained by shifting the partial remainder from the second latch 22b by N bits and inserting the signal of the bits from the most significant bit to the N least significant bits of the output of the shifter 23b into the nth adder 20-n. Is entered. The same operation is repeated in the subsequent cycles.

FIG. 3 is a block diagram showing a specific configuration of the repetitive integer type divider of the present invention. The arithmetic operation of the iterative integer type divider of the present invention will be specifically described with reference to FIG. 3 and the following arithmetic example. In this example,
The adder has two stages. The dividend (“10010011” in the calculation example) is given to the input line 36a, and the two's complement of the divisor (“01101110” in the calculation example) is given to the input line 36b. In the first cycle, the dividend Rj is selected by the first selector 41a and latched by the first latch 42a. The barrel shifter 43b does nothing in the first cycle and directly outputs the dividend input from the first latch 42a. The output of the barrel shifter 43b is sent to the first selector 41a via the signal line 39b.
The signal of the most significant bit (“1” in the calculation example) of the output of the barrel shifter 43b is sent to the first adder 40a, and the first adder 40a adds this signal and the two's complement of the divisor. The signal of the most significant bit and the one bit lower bit (“10” in the operation example) of the output of the barrel shifter 43b is sent to the second adder 40b, and the second adder 40b outputs this signal and the two's complement of the divisor. And are added. The signal of the upper 3 bits (“100” in the calculation example) of the output of the barrel shifter 43b is directly sent from the barrel shifter 43b to the second selector 41b via the signal line 44c. The carry outputs of the first adder 40a and the second adder 40b are the second selector 41
b and a third latch 42c for carry. As a result of the addition by the first adder 40a, if there is a carry output on the signal line 47a, the second selector 41b outputs the first output.
The addition result of the adder 40a is selected. First adder 4
If 0a has no carry output and second adder 40b has a carry output, second selector 41b selects the addition result of second adder 40b. When there is no carry output from both the first and second adders 40a and 40b, the signal on the signal line 44c is selected by the second selector 41b. (In the calculation example, the first and second adders 4
Since no carry output is output to 0a and 40b, the barrel shifter 43b outputs the signal "100" of the upper 3 bits of the dividend to the third adder 40c. ) The selected signal is output from the second selector 41b to the third adder 4
0c and the third selector 41c. The third adder 40c adds the signal (“100” in the calculation example) from the second selector 41b and the two's complement of the divisor. The carry output of the third adder 40c is sent to the third selector 41c and the third latch 42c. Third selector 41
c selects the addition result of the third adder 40c when the carry is output from the third adder 40c, and selects the signal from the second selector 41b when the carry is not output. And outputs it to the second latch 42b.
(In the calculation example, this carry is not output.) Both outputs of the second and third latches 42b and 42c are sent to the barrel shifter 43b.

In the second cycle, the first selector 41a operates as the barrel shifter 43 in the first cycle.
The output signal of b is selected, and the first latch 42a latches it and outputs it to the barrel shifter 43b. The barrel shifter 43b changes the shift amount of its output according to the output signal of the third latch 42c. That is, the barrel shifter 43b
Shifts the output of the first adder 40a to the left by one bit when the carry output is present in the first adder 40a.
If there is no carry output in a and there is a carry output in the second adder 40b, that output is shifted to the left by 2 bits, and if there is no carry output in both the first and second adders 40a and 40b. Shift its output 3 bits to the left. The barrel shifter 43b includes a first adder 40a,
Output signal of the second latch 42b (“100” in the calculation example)
Is shifted to the left by one bit, and the value (“1001” in the operation example) in which the signal of the most significant bit (“1” in the operation example) of the signal from the first latch 42a is inserted into the least significant bit is output. The barrel shifter 43b shifts the output signal of the second latch 42b to the left by 2 bits to the second adder 40b, and shifts the output signal of the second latch 42b to the left by 2 bits and shifts the most significant bit of the signal from the first latch 42a and 1 bit lower. Signal (1 in the calculation example
The value ("10010" in the calculation example) with "0") inserted is output. The barrel shifter 43b includes a third adder 40c,
A value obtained by shifting the output signal of the second latch 42b to the left by 3 bits and inserting the signals from the most significant bit to the lower 2 bits of the signal from the first latch 42a into the lower 3 bits (“100100” in the operation example). ) Is output. The first, second, and third adders 40a, 40b, and 40c perform the two's complement of the divisor and addition, and thereafter return to the first cycle,
The same operation is repeated until the division is completed. (In the calculation example, the quotient Q is not obtained in the first cycle and the second cycle, and the quotient Q = 1 and the remainder =
1 has been obtained. ) An example of operation using the iterative integer type divider of FIG. 3 is shown below. Dividend = 10010011 Divisor = 10010010 Two's complement of divisor = 01101110 ADD0 (40a) ADD1 (40b) ADD2 (40c) Q 1 10 1st cycle 01101110 01101110 00 100 01101110 0 1001 10010 2nd cycle 01101110 01101110 00 100100 01101110 0 1001001 10010011 Third cycle 01101110 01101110 01 1 01101110 0

[0015]

As described above, according to the integer type divider of the present invention, the integer type divider operates at almost the same operation speed as that of the conventional integer type divider, and the number of repetitive operation cycles is reduced with the same cycle time. The operation can be executed, and thus the division can be performed at a higher speed than the conventional one.

[Brief description of drawings]

FIG. 1 is a block diagram showing the basic configuration of a repetitive integer type divider according to the present invention.

FIG. 2 is a block diagram showing the configuration of an embodiment of an iterative integer type divider of the present invention.

FIG. 3 is a block diagram showing a specific configuration of a repetitive integer type divider according to the present invention.

FIG. 4 is a block diagram showing a basic configuration of a conventional iterative integer type divider.

FIG. 5 is a block diagram showing a specific configuration of a conventional iterative integer type divider.

[Explanation of symbols]

 10a ・ ・ 10d, 40a ・ ・ 40c Adder 1c, 11,11a, 11b, 12,60a, 60c, 60d Selector 1a, 60b Barrel shifter 1d, 8a, 8b, 12,50a ・ ・ 50c Latch 3 shifter

Claims (1)

[Claims] 1. A shift means for inputting a dividend and shifting the dividend from the upper bits at the same timing as a predetermined bit based on a carry output obtained in the previous operation cycle and outputting the dividend, the shift means shifting the dividend. Inserting means for sequentially inserting the dividend into the lower bits of the dividend according to the number of bits to be shifted and generating subtraction data from the higher bits, and the insertion means arranged in parallel according to the number of the predetermined bits to be shifted, from the subtraction data A plurality of subtracting means for subtracting the divisor for each bit, and either the arithmetic output of the subtracting means or the subtraction data generated by the inserting means is selected according to the carry output output from the plurality of subtracting means. Selecting means for outputting, and the shifting means for holding the output selected by the selecting means and for using this output as the dividend of the next operation cycle. A first holding means for sending, a second holding means for holding the carry output output from the plurality of subtracting means and sending to the shift means, and a necessary operation cycle is completed from the operation outputs of the plurality of subtracting means. An integer-type divider comprising: a detection unit that detects the above.