JPH03116327A - Multiplication system - Google Patents

Abstract

PURPOSE:To execute multiplication at a high speed by calculating the partial product between two bits of multiplier data and multiplicand data by one addition of an adder. CONSTITUTION:A selector 22 selects multiplicand data A held in a register 11 or data C held in a register 12 and supplies selected data to one input of an adder 15. A selector 23 selects lower two-bit data B1-0 of multiplier data B held in a register 13 or data '10' and supplies selected data to a selector 14'. The selector 14' selects one data from data '0 to 0', multiplicand data A, two-fold value data 1A of multiplicand data A, and three-fold value data D(=3A) of multiplicand data A in accordance with these selection and supplies it to the other input of the adder 15. Since the partial product between two bits of multiplier data and multiplicand is obtained by one operation, multiplication is executed at a high speed.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a multiplication method, and particularly relates to a multiplication method in which multiplier data and multiplicand data are multiplied using one adder circuit. .

(Prior Art) Conventionally, a multiplication circuit using one adder circuit is configured as shown in FIG. This multiplication circuit consists of three registers 11, 12, 13, a selector 14, and an adder circuit 1.
5.

The operation in this multiplication circuit is executed in the following procedure according to the flowchart of FIG.

First, to set initial data, multiplier data B is set in the register 13 (step A1), and similarly, data "0~0" is set as data C in the register 12 (step A2), and Multiplicand data A is set in 11 (step A3).

The calculations from step A4 are then repeatedly executed.

First, the least significant bit (L
SB) is sent to the selector 14. The selector 14 selects data “when the least significant bit of multiplier data B is “0”.
When the least significant bit is "1", the multiplicand data A of the register 11 is selected.

For example, when the lower 4 bits of multiplier data B are "1101", the least significant bit is "1°", so first, selector 14 selects multiplicand data A and outputs it to adder 15. Data C, that is, data “0-0” is output from the register 12 to the adder 15.

Then, the adder 15 adds the multiplicand data A and the data C, and the addition result data A1C is input to the register 12. At this time, the addition result data A+C is shifted one bit to the right (downward), and the least significant bit of the addition result data A+C is shifted into the register 13. As a result, multiplier data B in register 13 is also shifted to the right by one bit.

As a result, data C in register 12 becomes 1/2 of addition result data A+C, and data in register 13 becomes B/2.
(Step A4).

Next, the process moves to step A5, but this time register 1
Since the least significant bit of the multiplier data B of 3 is "0°", the selector 14 selects the data "0~0". Then, the data "0~02" and the data C of the register 12 are added by the adder 15, and from then on Processing similar to step A4 is performed.

By repeating the above operations in steps A6, A7, . . . , the multiplication result of multiplier data B and multiplicand data A is finally stored in registers 12 and 13.

In this way, the conventional multiplication circuit is configured to obtain the partial product of 1 bit of multiplier data B and multiplicand data B in one operation, so for example, when multiplier data B is n bits, the operation is It is necessary to repeat this process n times.

Therefore, when the bit length n of the multiplier data B is large, the number of operations required to obtain the multiplication result increases, resulting in a drawback that a large amount of time is required for the operations.

(Issue 8 to be solved by the invention) Conventionally, the calculation method is to calculate the partial product of 1 bit of multiplier data and multiplicand data in one operation, so it takes a lot of time to obtain the multiplication result. There is a drawback.

The present invention has been made in view of these points, and an object of the present invention is to provide a multiplication method that can perform multiplication at a sufficiently high speed.

[Structure of the Invention (Means and Effects for Solving the Problems) This invention provides a multiplication method in which multiplier data and multiplicand data are multiplied using one adding circuit. Data that sequentially selects data that is 0 times, 1 time, 2 times, or 3 times the multiplicand data according to the content of each bit, and supplies the selected data to the first input of the addition circuit. The adder further comprises: a selection means; and a data storage means for storing the result of addition of data by the adder circuit with a 2-bit downshift and supplying the stored data to a second input of the adder circuit; The partial product of the 2 bits of the multiplier data and the multiplicand data is calculated by one addition.

In this multiplication method, data of 0 times, 1 times, 2 times, and 3 times the multiplicand data is selectively supplied to the adder circuit according to the contents of the lower two bits of the multiplier data.
A partial product of 2 bits of multiplier data and the multiplicand data is calculated by one addition. Therefore, if the multiplier data is n bits, the multiplication result can be obtained by adding n/2 times.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a circuit configuration according to an embodiment of the present invention.

This multiplier R route has a configuration that uses one adder 15 to perform multiplication like the conventional multiplier circuit shown in FIG. The configuration is such that a partial product between and multiplicand data can be calculated.

That is, in this multiplication circuit, in addition to the conventional circuit configuration, a register 21, selectors 22, 23, and a flip-flop 24 are provided, and a selector 14' is used instead of the selector 14 used conventionally. There is.

The register 21 is for holding data D (-3A), which is the triple value of the multiplicand data A held in the register 11. 15.

The selector 14' selects four pieces of data, that is, data "0~" according to the 2-bit output data from the selector 23.
0'', multiplicand data A, double value data 2A of multiplicand data A, and 3-neighbor data D of multiplicand data A (-3
Select one data from A) and add it to adder 1.
5 to one input.

That is, the selector 14' selects data "0~0" when receiving data "00" from the selector 23,
Data A is selected when data "01" is received, data 2A is selected when data "10#" is received, and data D (-3A) is selected when data "11" is received.

The selector 23 is for controlling the selector 14', and depending on the state of the flip-flop 24, it selects two pieces of data, that is, multiplier data B held in the register 13.
Either the lower two bit data B1-0 or the data "10" is selected and supplied to the selector 14'.

That is, the selector 23 selects data "10" when the flip-flop 24 is in the reset state, and selects data B1-0 when the flip-flop 24 is in the set state.

The selector 22 selects either one of two pieces of data, that is, the multiplicand data A held in the register 11 and the data C held in the register 12, according to the state of the flip-flop 24. is supplied to the other input of the adder 15.

That is, the selector 22 selects data A when the flip-flop 24 is in the reset state, and selects data C when the flip-flop 24 is in the set state.

The flip-flop 24 is for controlling the selectors 22 and 23, and is in a reset state when data is initialized, and is maintained in a set state during calculation after initialization.

Next, the arithmetic processing operation of this multiplication circuit will be explained with reference to the flowchart of FIG.

First, in order to set initial data, multiplier data B is set in the register 13 (step Bl).Similarly, "0~0" is set as data C in the register 12 (step B2), and in the register 11. is set to multiplicand data A (step A3).

Next, in response to the flip-flop 24 in the reset state, the selector 23 selects data "10", and the data "10" is supplied to the selector 14'.

As a result, data 2A is selected by selector 14' and supplied to one input of adder 15.

On the other hand, in the selector 22, multiplicand data A is selected in response to the flip-flop 24 in the reset state,
It is supplied to the other input of adder 15.

As a result, the adder 15 executes addition of data 2A and data A, and the addition result data 3A is stored in the register 21 as data D (step B4).

At the time when the addition result data 3A is stored in the register 21, the flip-flop 24 is switched from the reset state to the set state, and thereafter remains in the set state until the calculation is completed.

The calculations from step B5 are then executed.

In step B5, first, the lower two bits of data B l-0 of the multiplier data B of the register 13 are transferred to the selector 2B.
sent to. In selector z3, flip-flop 24
is in the set state, data B 1-0 is selected.

Assume now that the lower middle bit of multiplier data B is "110001". In this case, the lower two bits of data B1-0 of the multiplier data B are "01", so the data "01" is transferred from the selector 23 to the selector 14'.
is supplied to As a result, the selector 14' selects the multiplicand data A, which is supplied to one input of the adder 15. On the other hand, the selector 22 selects the data C of the register 12, that is, the data "0 to O", and supplies it to the other input of the adder 15.

Then, the adder 15 adds the multiplicand data A and the data C, and the addition result data A+C is input to the register 12. At this time, the addition result data A+C is shifted 2 bits to the right (downward), and the least significant bit of the addition result data A+C and its most significant bit are shifted into the register 13. As a result, multiplier data B in register 13 is also shifted to the right by 2 bits.

As a result, 1/4 of the addition result data A1C is set as data C in the register 12, and B/4 is set as data B in the register 13 (step B5).

Next, the process moves to step B6, but this time the register I
Since the required lower bit of the multiplier data B of 3 is "00", the selector 14' selects data "0~0" and supplies it to one input of the adder 15. data C, that is, data A0C of 17
4 is selected and fed to the other input of adder 15.

Then, the adder 15 adds the data "0 to 0" and the data C, and the addition result data "0 to 0" 10 is input to the register 12. At this time, the addition result data “0~
0"10 is shifted to the right by 2 bits (digit down), and the least significant bit of the addition result data "0~0"+C and its upper 1 bit are shifted into the register 13. As a result, the data in the register 13 B is also shifted two bits to the right.

As a result, the register 12 stores the addition result data “0 to
1/4 of 0''+C is newly set as data C, and B/4 is newly set as multiplier data B in register 3 (step Be).

Next, the process of step B7 is executed. Next evening, data 3A is selected and supplied to one input of the adder 15. On the other hand, in the selector 22, the register 12
data C is selected and supplied to the other input of the adder 15.

Then, the adder 15 adds data 3A and data C, and the addition result data 3A and C are input to the register 12. At this time, the addition result data 3A+C is shifted 2 bits to the right (downward), and the least significant bit of the addition result data 3A+C and its most significant bit are shifted into the register 13.

As a result, data B in register 13 is also shifted to the right by 2 bits.

As a result, the addition result data 3A+ is stored in the register 12.
1/4 of C is newly set as data C, and B/4 is newly set as multiplier data B in the register 13 (step B7).

By sequentially performing the above operations, the result of multiplication of multiplier data B and multiplicand data A is finally stored in registers 12 and 13.

In this way, in this embodiment, multiplier data B is calculated in one operation.
Since the configuration is to calculate the partial product of 2 bits of and multiplicand data B, for example, if multiplier data B is n bits,
The multiplication result can be obtained with n/2 operations.

[Effects of the Invention] As described above, according to the present invention, multiplication can be executed at a sufficiently high speed with a simple hardware configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a circuit configuration according to an embodiment of the present invention, FIG. 2 is a flowchart explaining the multiplication processing operation in the circuit of FIG. 1, and FIG. 3 is a block diagram showing the configuration of a conventional multiplication circuit. 4 are flowcharts illustrating the multiplication processing operation in the circuit of FIG. 3. 11, 12.13.21... register, 14',
22.23...Selector, 15...Adder, 24.
··flip flop.

Claims (1)

[Claims] In a multiplication method in which multiplier data and multiplicand data are multiplied by using one adder circuit, the multiplier data is multiplied by zero according to the content of each lower two bits of the multiplier data. , 1x, 2x, and 3x data, and supplying the selected data to a first input of the adding circuit; and data storage means for storing the data with bits lowered and supplying the stored data to a second input of the adder circuit, and one addition by the adder circuit combines the two bits of the multiplier data with the data of the multiplier data. A multiplication method characterized by calculating partial products with multiplicand data.